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  1. # Note that I basically converted
  2. # u-boot/include/asm-arm/arch/comcerto_100.h
  3. # defines
  4. # this is a work-around for 'global' not working under Linux
  5. # access registers by calling this routine.
  6. # For example:
  7. # set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
  8. proc regs {reg} {
  9. return [dict get [regsC100] $reg ]
  10. }
  11. proc showreg {reg} {
  12. echo [format "0x%x" [dict get [regsC100] $reg ]]
  13. }
  14. proc regsC100 {} {
  15. #/* memcore */
  16. #/* device memory base addresses */
  17. #// device memory sizes
  18. #/* ARAM SIZE=64K */
  19. dict set regsC100 ARAM_SIZE 0x00010000
  20. dict set regsC100 ARAM_BASEADDR 0x0A000000
  21. #/* Hardware Interface Units */
  22. dict set regsC100 APB_BASEADDR 0x10000000
  23. #/* APB_SIZE=16M address range */
  24. dict set regsC100 APB_SIZE 0x01000000
  25. dict set regsC100 EXP_CS0_BASEADDR 0x20000000
  26. dict set regsC100 EXP_CS1_BASEADDR 0x24000000
  27. dict set regsC100 EXP_CS2_BASEADDR 0x28000000
  28. dict set regsC100 EXP_CS3_BASEADDR 0x2C000000
  29. dict set regsC100 EXP_CS4_BASEADDR 0x30000000
  30. dict set regsC100 DDR_BASEADDR 0x80000000
  31. dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000]
  32. dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000]
  33. dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000]
  34. dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000]
  35. dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000]
  36. dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000]
  37. dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000]
  38. dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000]
  39. dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000]
  40. dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000]
  41. dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000]
  42. dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000]
  43. dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000]
  44. dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
  45. dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
  46. dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000]
  47. dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000]
  48. dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000]
  49. dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000]
  50. dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000]
  51. dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000]
  52. dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000]
  53. dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000]
  54. #////////////////////////////////////////////////////////////
  55. #// AHB block //
  56. #////////////////////////////////////////////////////////////
  57. dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00]
  58. dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04]
  59. dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08]
  60. dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C]
  61. dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00]
  62. dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04]
  63. dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08]
  64. dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C]
  65. dict set regsC100 IDMA_MASTER 0
  66. dict set regsC100 TDMA_MASTER 1
  67. dict set regsC100 USBIPSEC_MASTER 2
  68. dict set regsC100 ARM0_MASTER 3
  69. dict set regsC100 ARM1_MASTER 4
  70. dict set regsC100 MDMA_MASTER 5
  71. #define IDMA_PRIORITY(level) (level)
  72. #define TDM_PRIORITY(level) (level << 4)
  73. #define USBIPSEC_PRIORITY(level) (level << 8)
  74. #define ARM0_PRIORITY(level) (level << 12)
  75. #define ARM1_PRIORITY(level) (level << 16)
  76. #define MDMA_PRIORITY(level) (level << 20)
  77. dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18]
  78. dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19]
  79. dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20]
  80. dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21]
  81. dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22]
  82. dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23]
  83. dict set regsC100 MEMORY_BASE_ADDR 0x80000000
  84. dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10]
  85. dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14]
  86. dict set regsC100 ROM_REMAP_EN 0x1
  87. #define HAL_asb_priority(level) \
  88. #*(volatile unsigned *)ASA_PRI_REG = level
  89. #define HAL_aram_priority(level) \
  90. #*(volatile unsigned *)ASA_ARAM_PRI_REG = level
  91. #define HAL_aram_arbitration(arbitration_mask) \
  92. #*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
  93. #define HAL_aram_defmaster(mask) \
  94. #*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
  95. #////////////////////////////////////////////////////////////
  96. #// INTC block //
  97. #////////////////////////////////////////////////////////////
  98. dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18]
  99. #////////////////////////////////////////////////////////////
  100. #// TIMER block //
  101. #////////////////////////////////////////////////////////////
  102. dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00]
  103. dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04]
  104. dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08]
  105. dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C]
  106. dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18]
  107. dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10]
  108. dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14]
  109. dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C]
  110. dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20]
  111. dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24]
  112. dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28]
  113. dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C]
  114. dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40]
  115. dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
  116. dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
  117. dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0]
  118. dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4]
  119. dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8]
  120. #////////////////////////////////////////////////////////////
  121. #// EBUS block
  122. #////////////////////////////////////////////////////////////
  123. dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00]
  124. dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04]
  125. dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08]
  126. dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C]
  127. dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10]
  128. dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14]
  129. dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18]
  130. dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C]
  131. dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20]
  132. dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24]
  133. dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28]
  134. dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C]
  135. dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30]
  136. dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34]
  137. dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38]
  138. dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C]
  139. dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40]
  140. dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44]
  141. dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48]
  142. dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C]
  143. dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50]
  144. dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54]
  145. dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58]
  146. dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C]
  147. dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60]
  148. dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64]
  149. dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68]
  150. dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C]
  151. dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
  152. dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
  153. dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104]
  154. dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108]
  155. dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C]
  156. dict set regsC100 EX_CLK_EN 0x00000001
  157. dict set regsC100 EX_CSBOOT_EN 0x00000002
  158. dict set regsC100 EX_CS0_EN 0x00000002
  159. dict set regsC100 EX_CS1_EN 0x00000004
  160. dict set regsC100 EX_CS2_EN 0x00000008
  161. dict set regsC100 EX_CS3_EN 0x00000010
  162. dict set regsC100 EX_CS4_EN 0x00000020
  163. dict set regsC100 EX_MEM_BUS_8 0x00000000
  164. dict set regsC100 EX_MEM_BUS_16 0x00000002
  165. dict set regsC100 EX_MEM_BUS_32 0x00000004
  166. dict set regsC100 EX_CS_HIGH 0x00000008
  167. dict set regsC100 EX_WE_HIGH 0x00000010
  168. dict set regsC100 EX_RE_HIGH 0x00000020
  169. dict set regsC100 EX_ALE_MODE 0x00000040
  170. dict set regsC100 EX_STRB_MODE 0x00000080
  171. dict set regsC100 EX_DM_MODE 0x00000100
  172. dict set regsC100 EX_NAND_MODE 0x00000200
  173. dict set regsC100 EX_RDY_EN 0x00000400
  174. dict set regsC100 EX_RDY_EDGE 0x00000800
  175. #////////////////////////////////////////////////////////////
  176. #// GPIO block
  177. #////////////////////////////////////////////////////////////
  178. # GPIO outputs register
  179. dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00]
  180. # GPIO Output Enable register
  181. dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04]
  182. dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08]
  183. dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C]
  184. # GPIO input register
  185. dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10]
  186. dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14]
  187. dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18]
  188. dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C]
  189. dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30]
  190. dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40]
  191. dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38]
  192. dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44]
  193. dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50]
  194. dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001
  195. dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002
  196. dict set regsC100 GPIO_IOCTRL_A19A21 0x00000004
  197. dict set regsC100 GPIO_IOCTRL_TMREVT0 0x00000008
  198. dict set regsC100 GPIO_IOCTRL_TMREVT1 0x00000010
  199. dict set regsC100 GPIO_IOCTRL_GPBT3 0x00000020
  200. dict set regsC100 GPIO_IOCTRL_I2C 0x00000040
  201. dict set regsC100 GPIO_IOCTRL_UART0 0x00000080
  202. dict set regsC100 GPIO_IOCTRL_UART1 0x00000100
  203. dict set regsC100 GPIO_IOCTRL_SPI 0x00000200
  204. dict set regsC100 GPIO_IOCTRL_HBMODE 0x00000400
  205. dict set regsC100 GPIO_IOCTRL_VAL 0x55555555
  206. dict set regsC100 GPIO_0 0x01
  207. dict set regsC100 GPIO_1 0x02
  208. dict set regsC100 GPIO_2 0x04
  209. dict set regsC100 GPIO_3 0x08
  210. dict set regsC100 GPIO_4 0x10
  211. dict set regsC100 GPIO_5 0x20
  212. dict set regsC100 GPIO_6 0x40
  213. dict set regsC100 GPIO_7 0x80
  214. dict set regsC100 GPIO_RISING_EDGE 1
  215. dict set regsC100 GPIO_FALLING_EDGE 2
  216. dict set regsC100 GPIO_BOTH_EDGES 3
  217. #////////////////////////////////////////////////////////////
  218. #// UART
  219. #////////////////////////////////////////////////////////////
  220. dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
  221. dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
  222. dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
  223. dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
  224. dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
  225. dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
  226. dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
  227. dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C]
  228. dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10]
  229. dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14]
  230. dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18]
  231. dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C]
  232. dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
  233. dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
  234. dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
  235. dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
  236. dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
  237. dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
  238. dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
  239. dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C]
  240. dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10]
  241. dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14]
  242. dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18]
  243. dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C]
  244. # /* default */
  245. dict set regsC100 LCR_CHAR_LEN_5 0x00
  246. dict set regsC100 LCR_CHAR_LEN_6 0x01
  247. dict set regsC100 LCR_CHAR_LEN_7 0x02
  248. dict set regsC100 LCR_CHAR_LEN_8 0x03
  249. #/* One stop bit! - default */
  250. dict set regsC100 LCR_ONE_STOP 0x00
  251. #/* Two stop bit! */
  252. dict set regsC100 LCR_TWO_STOP 0x04
  253. #/* Parity Enable */
  254. dict set regsC100 LCR_PEN 0x08
  255. dict set regsC100 LCR_PARITY_NONE 0x00
  256. #/* Even Parity Select */
  257. dict set regsC100 LCR_EPS 0x10
  258. #/* Enable Parity Stuff */
  259. dict set regsC100 LCR_PS 0x20
  260. #/* Start Break */
  261. dict set regsC100 LCR_SBRK 0x40
  262. #/* Parity Stuff Bit */
  263. dict set regsC100 LCR_PSB 0x80
  264. #/* UART 16550 Divisor Latch Assess */
  265. dict set regsC100 LCR_DLAB 0x80
  266. #/* FIFO Error Status */
  267. dict set regsC100 LSR_FIFOE [expr 1 << 7]
  268. #/* Transmitter Empty */
  269. dict set regsC100 LSR_TEMT [expr 1 << 6]
  270. #/* Transmit Data Request */
  271. dict set regsC100 LSR_TDRQ [expr 1 << 5]
  272. #/* Break Interrupt */
  273. dict set regsC100 LSR_BI [expr 1 << 4]
  274. #/* Framing Error */
  275. dict set regsC100 LSR_FE [expr 1 << 3]
  276. #/* Parity Error */
  277. dict set regsC100 LSR_PE [expr 1 << 2]
  278. #/* Overrun Error */
  279. dict set regsC100 LSR_OE [expr 1 << 1]
  280. #/* Data Ready */
  281. dict set regsC100 LSR_DR [expr 1 << 0]
  282. #/* DMA Requests Enable */
  283. dict set regsC100 IER_DMAE [expr 1 << 7]
  284. #/* UART Unit Enable */
  285. dict set regsC100 IER_UUE [expr 1 << 6]
  286. #/* NRZ coding Enable */
  287. dict set regsC100 IER_NRZE [expr 1 << 5]
  288. #/* Receiver Time Out Interrupt Enable */
  289. dict set regsC100 IER_RTIOE [expr 1 << 4]
  290. #/* Modem Interrupt Enable */
  291. dict set regsC100 IER_MIE [expr 1 << 3]
  292. #/* Receiver Line Status Interrupt Enable */
  293. dict set regsC100 IER_RLSE [expr 1 << 2]
  294. #/* Transmit Data request Interrupt Enable */
  295. dict set regsC100 IER_TIE [expr 1 << 1]
  296. #/* Receiver Data Available Interrupt Enable */
  297. dict set regsC100 IER_RAVIE [expr 1 << 0]
  298. #/* FIFO Mode Enable Status */
  299. dict set regsC100 IIR_FIFOES1 [expr 1 << 7]
  300. #/* FIFO Mode Enable Status */
  301. dict set regsC100 IIR_FIFOES0 [expr 1 << 6]
  302. #/* Time Out Detected */
  303. dict set regsC100 IIR_TOD [expr 1 << 3]
  304. #/* Interrupt Source Encoded */
  305. dict set regsC100 IIR_IID2 [expr 1 << 2]
  306. #/* Interrupt Source Encoded */
  307. dict set regsC100 IIR_IID1 [expr 1 << 1]
  308. #/* Interrupt Pending (active low) */
  309. dict set regsC100 IIR_IP [expr 1 << 0]
  310. #/* UART 16550 FIFO Control Register */
  311. dict set regsC100 FCR_FIFOEN 0x01
  312. dict set regsC100 FCR_RCVRRES 0x02
  313. dict set regsC100 FCR_XMITRES 0x04
  314. #/* Interrupt Enable Register */
  315. #// UART 16550
  316. #// Enable Received Data Available Interrupt
  317. dict set regsC100 IER_RXTH 0x01
  318. #// Enable Transmitter Empty Interrupt
  319. dict set regsC100 IER_TXTH 0x02
  320. #////////////////////////////////////////////////////////////
  321. #// CLK + RESET block
  322. #////////////////////////////////////////////////////////////
  323. dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00]
  324. dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04]
  325. dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08]
  326. dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C]
  327. dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10]
  328. dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14]
  329. dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18]
  330. dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C]
  331. dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20]
  332. dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24]
  333. dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40]
  334. dict set regsC100 ARM_PLL_BY_CTRL 0x80000000
  335. dict set regsC100 ARM_AHB_BYP 0x04000000
  336. dict set regsC100 PLL_DISABLE 0x02000000
  337. dict set regsC100 PLL_CLK_BYPASS 0x01000000
  338. dict set regsC100 AHB_PLL_BY_CTRL 0x80000000
  339. dict set regsC100 DIV_BYPASS 0x40000000
  340. dict set regsC100 SYNC_MODE 0x20000000
  341. dict set regsC100 EPHY_CLKDIV_BYPASS 0x00200000
  342. dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT 16
  343. dict set regsC100 PUI_CLKDIV_BYPASS 0x00004000
  344. dict set regsC100 PUI_CLKDIV_SRCCLK 0x00002000
  345. dict set regsC100 PUI_CLKDIV_RATIO_SHIFT 8
  346. dict set regsC100 PCI_CLKDIV_BYPASS 0x00000020
  347. dict set regsC100 PCI_CLKDIV_RATIO_SHIFT 0
  348. dict set regsC100 ARM0_CLK_PD 0x00200000
  349. dict set regsC100 ARM1_CLK_PD 0x00100000
  350. dict set regsC100 EPHY_CLK_PD 0x00080000
  351. dict set regsC100 TDM_CLK_PD 0x00040000
  352. dict set regsC100 PUI_CLK_PD 0x00020000
  353. dict set regsC100 PCI_CLK_PD 0x00010000
  354. dict set regsC100 MDMA_AHBCLK_PD 0x00000400
  355. dict set regsC100 I2CSPI_AHBCLK_PD 0x00000200
  356. dict set regsC100 UART_AHBCLK_PD 0x00000100
  357. dict set regsC100 IPSEC_AHBCLK_PD 0x00000080
  358. dict set regsC100 TDM_AHBCLK_PD 0x00000040
  359. dict set regsC100 USB1_AHBCLK_PD 0x00000020
  360. dict set regsC100 USB0_AHBCLK_PD 0x00000010
  361. dict set regsC100 GEMAC1_AHBCLK_PD 0x00000008
  362. dict set regsC100 GEMAC0_AHBCLK_PD 0x00000004
  363. dict set regsC100 PUI_AHBCLK_PD 0x00000002
  364. dict set regsC100 HIF_AHBCLK_PD 0x00000001
  365. dict set regsC100 ARM1_DIV_BP 0x00001000
  366. dict set regsC100 ARM1_DIV_VAL_SHIFT 8
  367. dict set regsC100 ARM0_DIV_BP 0x00000010
  368. dict set regsC100 ARM0_DIV_VAL_SHIFT 0
  369. dict set regsC100 AHBCLK_PLL_LOCK 0x00000002
  370. dict set regsC100 FCLK_PLL_LOCK 0x00000001
  371. #// reset block
  372. dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100]
  373. dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104]
  374. dict set regsC100 RNG_RST 0x1000
  375. dict set regsC100 IPSEC_RST 0x0800
  376. dict set regsC100 DDR_RST 0x0400
  377. dict set regsC100 USB1_PHY_RST 0x0200
  378. dict set regsC100 USB0_PHY_RST 0x0100
  379. dict set regsC100 USB1_RST 0x0080
  380. dict set regsC100 USB0_RST 0x0040
  381. dict set regsC100 GEMAC1_RST 0x0020
  382. dict set regsC100 GEMAC0_RST 0x0010
  383. dict set regsC100 TDM_RST 0x0008
  384. dict set regsC100 PUI_RST 0x0004
  385. dict set regsC100 HIF_RST 0x0002
  386. dict set regsC100 PCI_RST 0x0001
  387. #////////////////////////////////////////////////////////////////
  388. #// DDR CONTROLLER block
  389. #////////////////////////////////////////////////////////////////
  390. dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000
  391. dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00]
  392. dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08]
  393. dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10]
  394. dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18]
  395. dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20]
  396. dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28]
  397. dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30]
  398. dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38]
  399. dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40]
  400. dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48]
  401. dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50]
  402. dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58]
  403. dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60]
  404. dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68]
  405. dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70]
  406. dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78]
  407. dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80]
  408. dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88]
  409. dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90]
  410. dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98]
  411. dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0]
  412. # 32-bit value
  413. dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44]
  414. # 8-bit
  415. dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D]
  416. # 8-bit
  417. dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A]
  418. # 8-bit
  419. dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F]
  420. # 8-bit
  421. dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50]
  422. # 8-bit
  423. dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51]
  424. # 8-bit
  425. dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52]
  426. # end of proc regsC100
  427. }