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  1. /***************************************************************************
  2. * Copyright (C) 2015 by David Ung *
  3. * *
  4. * Copyright (C) 2018 by Liviu Ionescu *
  5. * <ilg@livius.net> *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. ***************************************************************************/
  21. #ifdef HAVE_CONFIG_H
  22. #include "config.h"
  23. #endif
  24. #include <helper/replacements.h>
  25. #include "armv8.h"
  26. #include "arm_disassembler.h"
  27. #include "register.h"
  28. #include <helper/binarybuffer.h>
  29. #include <helper/command.h>
  30. #include <stdlib.h>
  31. #include <string.h>
  32. #include <unistd.h>
  33. #include "armv8_opcodes.h"
  34. #include "target.h"
  35. #include "target_type.h"
  36. #include "semihosting_common.h"
  37. static const char * const armv8_state_strings[] = {
  38. "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
  39. };
  40. static const struct {
  41. const char *name;
  42. unsigned psr;
  43. } armv8_mode_data[] = {
  44. {
  45. .name = "USR",
  46. .psr = ARM_MODE_USR,
  47. },
  48. {
  49. .name = "FIQ",
  50. .psr = ARM_MODE_FIQ,
  51. },
  52. {
  53. .name = "IRQ",
  54. .psr = ARM_MODE_IRQ,
  55. },
  56. {
  57. .name = "SVC",
  58. .psr = ARM_MODE_SVC,
  59. },
  60. {
  61. .name = "MON",
  62. .psr = ARM_MODE_MON,
  63. },
  64. {
  65. .name = "ABT",
  66. .psr = ARM_MODE_ABT,
  67. },
  68. {
  69. .name = "HYP",
  70. .psr = ARM_MODE_HYP,
  71. },
  72. {
  73. .name = "SYS",
  74. .psr = ARM_MODE_SYS,
  75. },
  76. {
  77. .name = "EL0T",
  78. .psr = ARMV8_64_EL0T,
  79. },
  80. {
  81. .name = "EL1T",
  82. .psr = ARMV8_64_EL1T,
  83. },
  84. {
  85. .name = "EL1H",
  86. .psr = ARMV8_64_EL1H,
  87. },
  88. {
  89. .name = "EL2T",
  90. .psr = ARMV8_64_EL2T,
  91. },
  92. {
  93. .name = "EL2H",
  94. .psr = ARMV8_64_EL2H,
  95. },
  96. {
  97. .name = "EL3T",
  98. .psr = ARMV8_64_EL3T,
  99. },
  100. {
  101. .name = "EL3H",
  102. .psr = ARMV8_64_EL3H,
  103. },
  104. };
  105. /** Map PSR mode bits to the name of an ARM processor operating mode. */
  106. const char *armv8_mode_name(unsigned psr_mode)
  107. {
  108. for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
  109. if (armv8_mode_data[i].psr == psr_mode)
  110. return armv8_mode_data[i].name;
  111. }
  112. LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
  113. return "UNRECOGNIZED";
  114. }
  115. static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
  116. {
  117. struct arm_dpm *dpm = &armv8->dpm;
  118. int retval;
  119. uint32_t value;
  120. uint64_t value_64;
  121. switch (regnum) {
  122. case 0 ... 30:
  123. retval = dpm->instr_read_data_dcc_64(dpm,
  124. ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, regnum), &value_64);
  125. break;
  126. case ARMV8_SP:
  127. retval = dpm->instr_read_data_r0_64(dpm,
  128. ARMV8_MOVFSP_64(0), &value_64);
  129. break;
  130. case ARMV8_PC:
  131. retval = dpm->instr_read_data_r0_64(dpm,
  132. ARMV8_MRS_DLR(0), &value_64);
  133. break;
  134. case ARMV8_xPSR:
  135. retval = dpm->instr_read_data_r0(dpm,
  136. ARMV8_MRS_DSPSR(0), &value);
  137. value_64 = value;
  138. break;
  139. case ARMV8_FPSR:
  140. retval = dpm->instr_read_data_r0(dpm,
  141. ARMV8_MRS_FPSR(0), &value);
  142. value_64 = value;
  143. break;
  144. case ARMV8_FPCR:
  145. retval = dpm->instr_read_data_r0(dpm,
  146. ARMV8_MRS_FPCR(0), &value);
  147. value_64 = value;
  148. break;
  149. case ARMV8_ELR_EL1:
  150. retval = dpm->instr_read_data_r0_64(dpm,
  151. ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64);
  152. break;
  153. case ARMV8_ELR_EL2:
  154. retval = dpm->instr_read_data_r0_64(dpm,
  155. ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64);
  156. break;
  157. case ARMV8_ELR_EL3:
  158. retval = dpm->instr_read_data_r0_64(dpm,
  159. ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64);
  160. break;
  161. case ARMV8_ESR_EL1:
  162. retval = dpm->instr_read_data_r0(dpm,
  163. ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value);
  164. value_64 = value;
  165. break;
  166. case ARMV8_ESR_EL2:
  167. retval = dpm->instr_read_data_r0(dpm,
  168. ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value);
  169. value_64 = value;
  170. break;
  171. case ARMV8_ESR_EL3:
  172. retval = dpm->instr_read_data_r0(dpm,
  173. ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value);
  174. value_64 = value;
  175. break;
  176. case ARMV8_SPSR_EL1:
  177. retval = dpm->instr_read_data_r0(dpm,
  178. ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value);
  179. value_64 = value;
  180. break;
  181. case ARMV8_SPSR_EL2:
  182. retval = dpm->instr_read_data_r0(dpm,
  183. ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value);
  184. value_64 = value;
  185. break;
  186. case ARMV8_SPSR_EL3:
  187. retval = dpm->instr_read_data_r0(dpm,
  188. ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value);
  189. value_64 = value;
  190. break;
  191. default:
  192. retval = ERROR_FAIL;
  193. break;
  194. }
  195. if (retval == ERROR_OK && regval)
  196. *regval = value_64;
  197. else
  198. retval = ERROR_FAIL;
  199. return retval;
  200. }
  201. static int armv8_read_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
  202. {
  203. int retval = ERROR_FAIL;
  204. struct arm_dpm *dpm = &armv8->dpm;
  205. switch (regnum) {
  206. case ARMV8_V0 ... ARMV8_V31:
  207. retval = dpm->instr_read_data_r0_64(dpm,
  208. ARMV8_MOV_GPR_VFP(0, (regnum - ARMV8_V0), 1), hvalue);
  209. if (retval != ERROR_OK)
  210. return retval;
  211. retval = dpm->instr_read_data_r0_64(dpm,
  212. ARMV8_MOV_GPR_VFP(0, (regnum - ARMV8_V0), 0), lvalue);
  213. break;
  214. default:
  215. retval = ERROR_FAIL;
  216. break;
  217. }
  218. return retval;
  219. }
  220. static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
  221. {
  222. struct arm_dpm *dpm = &armv8->dpm;
  223. int retval;
  224. uint32_t value;
  225. switch (regnum) {
  226. case 0 ... 30:
  227. retval = dpm->instr_write_data_dcc_64(dpm,
  228. ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, regnum),
  229. value_64);
  230. break;
  231. case ARMV8_SP:
  232. retval = dpm->instr_write_data_r0_64(dpm,
  233. ARMV8_MOVTSP_64(0),
  234. value_64);
  235. break;
  236. case ARMV8_PC:
  237. retval = dpm->instr_write_data_r0_64(dpm,
  238. ARMV8_MSR_DLR(0),
  239. value_64);
  240. break;
  241. case ARMV8_xPSR:
  242. value = value_64;
  243. retval = dpm->instr_write_data_r0(dpm,
  244. ARMV8_MSR_DSPSR(0),
  245. value);
  246. break;
  247. case ARMV8_FPSR:
  248. value = value_64;
  249. retval = dpm->instr_write_data_r0(dpm,
  250. ARMV8_MSR_FPSR(0),
  251. value);
  252. break;
  253. case ARMV8_FPCR:
  254. value = value_64;
  255. retval = dpm->instr_write_data_r0(dpm,
  256. ARMV8_MSR_FPCR(0),
  257. value);
  258. break;
  259. /* registers clobbered by taking exception in debug state */
  260. case ARMV8_ELR_EL1:
  261. retval = dpm->instr_write_data_r0_64(dpm,
  262. ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64);
  263. break;
  264. case ARMV8_ELR_EL2:
  265. retval = dpm->instr_write_data_r0_64(dpm,
  266. ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64);
  267. break;
  268. case ARMV8_ELR_EL3:
  269. retval = dpm->instr_write_data_r0_64(dpm,
  270. ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64);
  271. break;
  272. case ARMV8_ESR_EL1:
  273. value = value_64;
  274. retval = dpm->instr_write_data_r0(dpm,
  275. ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value);
  276. break;
  277. case ARMV8_ESR_EL2:
  278. value = value_64;
  279. retval = dpm->instr_write_data_r0(dpm,
  280. ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value);
  281. break;
  282. case ARMV8_ESR_EL3:
  283. value = value_64;
  284. retval = dpm->instr_write_data_r0(dpm,
  285. ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value);
  286. break;
  287. case ARMV8_SPSR_EL1:
  288. value = value_64;
  289. retval = dpm->instr_write_data_r0(dpm,
  290. ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value);
  291. break;
  292. case ARMV8_SPSR_EL2:
  293. value = value_64;
  294. retval = dpm->instr_write_data_r0(dpm,
  295. ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value);
  296. break;
  297. case ARMV8_SPSR_EL3:
  298. value = value_64;
  299. retval = dpm->instr_write_data_r0(dpm,
  300. ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value);
  301. break;
  302. default:
  303. retval = ERROR_FAIL;
  304. break;
  305. }
  306. return retval;
  307. }
  308. static int armv8_write_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
  309. {
  310. int retval = ERROR_FAIL;
  311. struct arm_dpm *dpm = &armv8->dpm;
  312. switch (regnum) {
  313. case ARMV8_V0 ... ARMV8_V31:
  314. retval = dpm->instr_write_data_r0_64(dpm,
  315. ARMV8_MOV_VFP_GPR((regnum - ARMV8_V0), 0, 1), hvalue);
  316. if (retval != ERROR_OK)
  317. return retval;
  318. retval = dpm->instr_write_data_r0_64(dpm,
  319. ARMV8_MOV_VFP_GPR((regnum - ARMV8_V0), 0, 0), lvalue);
  320. break;
  321. default:
  322. retval = ERROR_FAIL;
  323. break;
  324. }
  325. return retval;
  326. }
  327. static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *regval)
  328. {
  329. struct arm_dpm *dpm = &armv8->dpm;
  330. uint32_t value = 0;
  331. int retval;
  332. switch (regnum) {
  333. case ARMV8_R0 ... ARMV8_R14:
  334. /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
  335. retval = dpm->instr_read_data_dcc(dpm,
  336. ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
  337. &value);
  338. break;
  339. case ARMV8_SP:
  340. retval = dpm->instr_read_data_dcc(dpm,
  341. ARMV4_5_MCR(14, 0, 13, 0, 5, 0),
  342. &value);
  343. break;
  344. case ARMV8_PC:
  345. retval = dpm->instr_read_data_r0(dpm,
  346. ARMV8_MRC_DLR(0),
  347. &value);
  348. break;
  349. case ARMV8_xPSR:
  350. retval = dpm->instr_read_data_r0(dpm,
  351. ARMV8_MRC_DSPSR(0),
  352. &value);
  353. break;
  354. case ARMV8_ELR_EL1: /* mapped to LR_svc */
  355. retval = dpm->instr_read_data_dcc(dpm,
  356. ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
  357. &value);
  358. break;
  359. case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
  360. retval = dpm->instr_read_data_r0(dpm,
  361. ARMV8_MRS_T1(0, 14, 0, 1),
  362. &value);
  363. break;
  364. case ARMV8_ELR_EL3: /* mapped to LR_mon */
  365. retval = dpm->instr_read_data_dcc(dpm,
  366. ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
  367. &value);
  368. break;
  369. case ARMV8_ESR_EL1: /* mapped to DFSR */
  370. retval = dpm->instr_read_data_r0(dpm,
  371. ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
  372. &value);
  373. break;
  374. case ARMV8_ESR_EL2: /* mapped to HSR */
  375. retval = dpm->instr_read_data_r0(dpm,
  376. ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
  377. &value);
  378. break;
  379. case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
  380. retval = ERROR_FAIL;
  381. break;
  382. case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
  383. retval = dpm->instr_read_data_r0(dpm,
  384. ARMV8_MRS_xPSR_T1(1, 0),
  385. &value);
  386. break;
  387. case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
  388. retval = dpm->instr_read_data_r0(dpm,
  389. ARMV8_MRS_xPSR_T1(1, 0),
  390. &value);
  391. break;
  392. case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
  393. retval = dpm->instr_read_data_r0(dpm,
  394. ARMV8_MRS_xPSR_T1(1, 0),
  395. &value);
  396. break;
  397. case ARMV8_FPSR:
  398. /* "VMRS r0, FPSCR"; then return via DCC */
  399. retval = dpm->instr_read_data_r0(dpm,
  400. ARMV4_5_VMRS(0), &value);
  401. break;
  402. default:
  403. retval = ERROR_FAIL;
  404. break;
  405. }
  406. if (retval == ERROR_OK && regval)
  407. *regval = value;
  408. return retval;
  409. }
  410. static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
  411. {
  412. int retval = ERROR_FAIL;
  413. struct arm_dpm *dpm = &armv8->dpm;
  414. struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
  415. uint32_t value_r0 = 0, value_r1 = 0;
  416. unsigned num = (regnum - ARMV8_V0) << 1;
  417. switch (regnum) {
  418. case ARMV8_V0 ... ARMV8_V15:
  419. /* we are going to write R1, mark it dirty */
  420. reg_r1->dirty = true;
  421. /* move from double word register to r0:r1: "vmov r0, r1, vm"
  422. * then read r0 via dcc
  423. */
  424. retval = dpm->instr_read_data_r0(dpm,
  425. ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
  426. &value_r0);
  427. /* read r1 via dcc */
  428. retval = dpm->instr_read_data_dcc(dpm,
  429. ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
  430. &value_r1);
  431. if (retval == ERROR_OK) {
  432. *lvalue = value_r1;
  433. *lvalue = ((*lvalue) << 32) | value_r0;
  434. } else
  435. return retval;
  436. num++;
  437. /* repeat above steps for high 64 bits of V register */
  438. retval = dpm->instr_read_data_r0(dpm,
  439. ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
  440. &value_r0);
  441. retval = dpm->instr_read_data_dcc(dpm,
  442. ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
  443. &value_r1);
  444. if (retval == ERROR_OK) {
  445. *hvalue = value_r1;
  446. *hvalue = ((*hvalue) << 32) | value_r0;
  447. } else
  448. return retval;
  449. break;
  450. default:
  451. retval = ERROR_FAIL;
  452. break;
  453. }
  454. return retval;
  455. }
  456. static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t value)
  457. {
  458. struct arm_dpm *dpm = &armv8->dpm;
  459. int retval;
  460. switch (regnum) {
  461. case ARMV8_R0 ... ARMV8_R14:
  462. /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
  463. retval = dpm->instr_write_data_dcc(dpm,
  464. ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value);
  465. break;
  466. case ARMV8_SP:
  467. retval = dpm->instr_write_data_dcc(dpm,
  468. ARMV4_5_MRC(14, 0, 13, 0, 5, 0), value);
  469. break;
  470. case ARMV8_PC:/* PC
  471. * read r0 from DCC; then "MOV pc, r0" */
  472. retval = dpm->instr_write_data_r0(dpm,
  473. ARMV8_MCR_DLR(0), value);
  474. break;
  475. case ARMV8_xPSR: /* CPSR */
  476. /* read r0 from DCC, then "MCR r0, DSPSR" */
  477. retval = dpm->instr_write_data_r0(dpm,
  478. ARMV8_MCR_DSPSR(0), value);
  479. break;
  480. case ARMV8_ELR_EL1: /* mapped to LR_svc */
  481. retval = dpm->instr_write_data_dcc(dpm,
  482. ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
  483. value);
  484. break;
  485. case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
  486. retval = dpm->instr_write_data_r0(dpm,
  487. ARMV8_MSR_GP_T1(0, 14, 0, 1),
  488. value);
  489. break;
  490. case ARMV8_ELR_EL3: /* mapped to LR_mon */
  491. retval = dpm->instr_write_data_dcc(dpm,
  492. ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
  493. value);
  494. break;
  495. case ARMV8_ESR_EL1: /* mapped to DFSR */
  496. retval = dpm->instr_write_data_r0(dpm,
  497. ARMV4_5_MCR(15, 0, 0, 5, 0, 0),
  498. value);
  499. break;
  500. case ARMV8_ESR_EL2: /* mapped to HSR */
  501. retval = dpm->instr_write_data_r0(dpm,
  502. ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
  503. value);
  504. break;
  505. case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
  506. retval = ERROR_FAIL;
  507. break;
  508. case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
  509. retval = dpm->instr_write_data_r0(dpm,
  510. ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
  511. value);
  512. break;
  513. case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
  514. retval = dpm->instr_write_data_r0(dpm,
  515. ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
  516. value);
  517. break;
  518. case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
  519. retval = dpm->instr_write_data_r0(dpm,
  520. ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
  521. value);
  522. break;
  523. case ARMV8_FPSR:
  524. /* move to r0 from DCC, then "VMSR FPSCR, r0" */
  525. retval = dpm->instr_write_data_r0(dpm,
  526. ARMV4_5_VMSR(0), value);
  527. break;
  528. default:
  529. retval = ERROR_FAIL;
  530. break;
  531. }
  532. return retval;
  533. }
  534. static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
  535. {
  536. int retval = ERROR_FAIL;
  537. struct arm_dpm *dpm = &armv8->dpm;
  538. struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
  539. uint32_t value_r0 = 0, value_r1 = 0;
  540. unsigned num = (regnum - ARMV8_V0) << 1;
  541. switch (regnum) {
  542. case ARMV8_V0 ... ARMV8_V15:
  543. /* we are going to write R1, mark it dirty */
  544. reg_r1->dirty = true;
  545. value_r1 = lvalue >> 32;
  546. value_r0 = lvalue & 0xFFFFFFFF;
  547. /* write value_r1 to r1 via dcc */
  548. retval = dpm->instr_write_data_dcc(dpm,
  549. ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
  550. value_r1);
  551. /* write value_r0 to r0 via dcc then,
  552. * move to double word register from r0:r1: "vmov vm, r0, r1"
  553. */
  554. retval = dpm->instr_write_data_r0(dpm,
  555. ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
  556. value_r0);
  557. num++;
  558. /* repeat above steps for high 64 bits of V register */
  559. value_r1 = hvalue >> 32;
  560. value_r0 = hvalue & 0xFFFFFFFF;
  561. retval = dpm->instr_write_data_dcc(dpm,
  562. ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
  563. value_r1);
  564. retval = dpm->instr_write_data_r0(dpm,
  565. ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
  566. value_r0);
  567. break;
  568. default:
  569. retval = ERROR_FAIL;
  570. break;
  571. }
  572. return retval;
  573. }
  574. void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
  575. {
  576. if (is_aarch64) {
  577. armv8->read_reg_u64 = armv8_read_reg;
  578. armv8->write_reg_u64 = armv8_write_reg;
  579. armv8->read_reg_u128 = armv8_read_reg_simdfp_aarch64;
  580. armv8->write_reg_u128 = armv8_write_reg_simdfp_aarch64;
  581. } else {
  582. armv8->read_reg_u64 = armv8_read_reg32;
  583. armv8->write_reg_u64 = armv8_write_reg32;
  584. armv8->read_reg_u128 = armv8_read_reg_simdfp_aarch32;
  585. armv8->write_reg_u128 = armv8_write_reg_simdfp_aarch32;
  586. }
  587. }
  588. /* retrieve core id cluster id */
  589. int armv8_read_mpidr(struct armv8_common *armv8)
  590. {
  591. int retval = ERROR_FAIL;
  592. struct arm *arm = &armv8->arm;
  593. struct arm_dpm *dpm = armv8->arm.dpm;
  594. uint32_t mpidr;
  595. retval = dpm->prepare(dpm);
  596. if (retval != ERROR_OK)
  597. goto done;
  598. /* check if we're in an unprivileged mode */
  599. if (armv8_curel_from_core_mode(arm->core_mode) < SYSTEM_CUREL_EL1) {
  600. retval = armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
  601. if (retval != ERROR_OK)
  602. return retval;
  603. }
  604. retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
  605. if (retval != ERROR_OK)
  606. goto done;
  607. if (mpidr & 1U<<31) {
  608. armv8->multi_processor_system = (mpidr >> 30) & 1;
  609. armv8->cluster_id = (mpidr >> 8) & 0xf;
  610. armv8->cpu_id = mpidr & 0x3;
  611. LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
  612. armv8->cluster_id,
  613. armv8->cpu_id,
  614. armv8->multi_processor_system == 0 ? "multi core" : "single core");
  615. } else
  616. LOG_ERROR("mpidr not in multiprocessor format");
  617. done:
  618. armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
  619. dpm->finish(dpm);
  620. return retval;
  621. }
  622. /**
  623. * Configures host-side ARM records to reflect the specified CPSR.
  624. * Later, code can use arm_reg_current() to map register numbers
  625. * according to how they are exposed by this mode.
  626. */
  627. void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
  628. {
  629. uint32_t mode = cpsr & 0x1F;
  630. /* NOTE: this may be called very early, before the register
  631. * cache is set up. We can't defend against many errors, in
  632. * particular against CPSRs that aren't valid *here* ...
  633. */
  634. if (arm->cpsr) {
  635. buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
  636. arm->cpsr->valid = true;
  637. arm->cpsr->dirty = false;
  638. }
  639. /* Older ARMs won't have the J bit */
  640. enum arm_state state = 0xFF;
  641. if ((cpsr & 0x10) != 0) {
  642. /* Aarch32 state */
  643. if (cpsr & (1 << 5)) { /* T */
  644. if (cpsr & (1 << 24)) { /* J */
  645. LOG_WARNING("ThumbEE -- incomplete support");
  646. state = ARM_STATE_THUMB_EE;
  647. } else
  648. state = ARM_STATE_THUMB;
  649. } else {
  650. if (cpsr & (1 << 24)) { /* J */
  651. LOG_ERROR("Jazelle state handling is BROKEN!");
  652. state = ARM_STATE_JAZELLE;
  653. } else
  654. state = ARM_STATE_ARM;
  655. }
  656. } else {
  657. /* Aarch64 state */
  658. state = ARM_STATE_AARCH64;
  659. }
  660. arm->core_state = state;
  661. arm->core_mode = mode;
  662. LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
  663. armv8_mode_name(arm->core_mode),
  664. armv8_state_strings[arm->core_state]);
  665. }
  666. static void armv8_show_fault_registers32(struct armv8_common *armv8)
  667. {
  668. uint32_t dfsr, ifsr, dfar, ifar;
  669. struct arm_dpm *dpm = armv8->arm.dpm;
  670. int retval;
  671. retval = dpm->prepare(dpm);
  672. if (retval != ERROR_OK)
  673. return;
  674. /* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
  675. /* c5/c0 - {data, instruction} fault status registers */
  676. retval = dpm->instr_read_data_r0(dpm,
  677. ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
  678. &dfsr);
  679. if (retval != ERROR_OK)
  680. goto done;
  681. retval = dpm->instr_read_data_r0(dpm,
  682. ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
  683. &ifsr);
  684. if (retval != ERROR_OK)
  685. goto done;
  686. /* c6/c0 - {data, instruction} fault address registers */
  687. retval = dpm->instr_read_data_r0(dpm,
  688. ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
  689. &dfar);
  690. if (retval != ERROR_OK)
  691. goto done;
  692. retval = dpm->instr_read_data_r0(dpm,
  693. ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
  694. &ifar);
  695. if (retval != ERROR_OK)
  696. goto done;
  697. LOG_USER("Data fault registers DFSR: %8.8" PRIx32
  698. ", DFAR: %8.8" PRIx32, dfsr, dfar);
  699. LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
  700. ", IFAR: %8.8" PRIx32, ifsr, ifar);
  701. done:
  702. /* (void) */ dpm->finish(dpm);
  703. }
  704. static __attribute__((unused)) void armv8_show_fault_registers(struct target *target)
  705. {
  706. struct armv8_common *armv8 = target_to_armv8(target);
  707. if (armv8->arm.core_state != ARM_STATE_AARCH64)
  708. armv8_show_fault_registers32(armv8);
  709. }
  710. static uint8_t armv8_pa_size(uint32_t ps)
  711. {
  712. uint8_t ret = 0;
  713. switch (ps) {
  714. case 0:
  715. ret = 32;
  716. break;
  717. case 1:
  718. ret = 36;
  719. break;
  720. case 2:
  721. ret = 40;
  722. break;
  723. case 3:
  724. ret = 42;
  725. break;
  726. case 4:
  727. ret = 44;
  728. break;
  729. case 5:
  730. ret = 48;
  731. break;
  732. default:
  733. LOG_INFO("Unknown physical address size");
  734. break;
  735. }
  736. return ret;
  737. }
  738. static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
  739. {
  740. struct armv8_common *armv8 = target_to_armv8(target);
  741. struct arm_dpm *dpm = armv8->arm.dpm;
  742. uint32_t ttbcr, ttbcr_n;
  743. int retval = dpm->prepare(dpm);
  744. if (retval != ERROR_OK)
  745. goto done;
  746. /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
  747. retval = dpm->instr_read_data_r0(dpm,
  748. ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
  749. &ttbcr);
  750. if (retval != ERROR_OK)
  751. goto done;
  752. LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
  753. ttbcr_n = ttbcr & 0x7;
  754. armv8->armv8_mmu.ttbcr = ttbcr;
  755. /*
  756. * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
  757. * document # ARM DDI 0406C
  758. */
  759. armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
  760. armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
  761. armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
  762. armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
  763. LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
  764. (ttbcr_n != 0) ? "used" : "not used",
  765. armv8->armv8_mmu.ttbr_mask[0],
  766. armv8->armv8_mmu.ttbr_mask[1]);
  767. done:
  768. dpm->finish(dpm);
  769. return retval;
  770. }
  771. static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
  772. {
  773. struct armv8_common *armv8 = target_to_armv8(target);
  774. struct arm_dpm *dpm = armv8->arm.dpm;
  775. struct arm *arm = &armv8->arm;
  776. uint32_t ttbcr;
  777. uint64_t ttbcr_64;
  778. int retval = dpm->prepare(dpm);
  779. if (retval != ERROR_OK)
  780. goto done;
  781. /* clear ttrr1_used and ttbr0_mask */
  782. memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
  783. memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
  784. switch (armv8_curel_from_core_mode(arm->core_mode)) {
  785. case SYSTEM_CUREL_EL3:
  786. retval = dpm->instr_read_data_r0(dpm,
  787. ARMV8_MRS(SYSTEM_TCR_EL3, 0),
  788. &ttbcr);
  789. retval += dpm->instr_read_data_r0_64(dpm,
  790. ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
  791. &armv8->ttbr_base);
  792. if (retval != ERROR_OK)
  793. goto done;
  794. armv8->va_size = 64 - (ttbcr & 0x3F);
  795. armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
  796. armv8->page_size = (ttbcr >> 14) & 3;
  797. break;
  798. case SYSTEM_CUREL_EL2:
  799. retval = dpm->instr_read_data_r0(dpm,
  800. ARMV8_MRS(SYSTEM_TCR_EL2, 0),
  801. &ttbcr);
  802. retval += dpm->instr_read_data_r0_64(dpm,
  803. ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
  804. &armv8->ttbr_base);
  805. if (retval != ERROR_OK)
  806. goto done;
  807. armv8->va_size = 64 - (ttbcr & 0x3F);
  808. armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
  809. armv8->page_size = (ttbcr >> 14) & 3;
  810. break;
  811. case SYSTEM_CUREL_EL0:
  812. armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
  813. /* fall through */
  814. case SYSTEM_CUREL_EL1:
  815. retval = dpm->instr_read_data_r0_64(dpm,
  816. ARMV8_MRS(SYSTEM_TCR_EL1, 0),
  817. &ttbcr_64);
  818. armv8->va_size = 64 - (ttbcr_64 & 0x3F);
  819. armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
  820. armv8->page_size = (ttbcr_64 >> 14) & 3;
  821. armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
  822. armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
  823. retval += dpm->instr_read_data_r0_64(dpm,
  824. ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
  825. &armv8->ttbr_base);
  826. if (retval != ERROR_OK)
  827. goto done;
  828. break;
  829. default:
  830. LOG_ERROR("unknown core state");
  831. retval = ERROR_FAIL;
  832. break;
  833. }
  834. if (retval != ERROR_OK)
  835. goto done;
  836. if (armv8->armv8_mmu.ttbr1_used == 1)
  837. LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
  838. done:
  839. armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
  840. dpm->finish(dpm);
  841. return retval;
  842. }
  843. /* method adapted to cortex A : reused arm v4 v5 method*/
  844. int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
  845. {
  846. return ERROR_OK;
  847. }
  848. /* V8 method VA TO PA */
  849. int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
  850. target_addr_t *val, int meminfo)
  851. {
  852. struct armv8_common *armv8 = target_to_armv8(target);
  853. struct arm *arm = target_to_arm(target);
  854. struct arm_dpm *dpm = &armv8->dpm;
  855. enum arm_mode target_mode = ARM_MODE_ANY;
  856. uint32_t retval;
  857. uint32_t instr = 0;
  858. uint64_t par;
  859. static const char * const shared_name[] = {
  860. "Non-", "UNDEFINED ", "Outer ", "Inner "
  861. };
  862. static const char * const secure_name[] = {
  863. "Secure", "Not Secure"
  864. };
  865. if (target->state != TARGET_HALTED) {
  866. LOG_WARNING("target %s not halted", target_name(target));
  867. return ERROR_TARGET_NOT_HALTED;
  868. }
  869. retval = dpm->prepare(dpm);
  870. if (retval != ERROR_OK)
  871. return retval;
  872. switch (armv8_curel_from_core_mode(arm->core_mode)) {
  873. case SYSTEM_CUREL_EL0:
  874. instr = ARMV8_SYS(SYSTEM_ATS12E0R, 0);
  875. /* can only execute instruction at EL2 */
  876. target_mode = ARMV8_64_EL2H;
  877. break;
  878. case SYSTEM_CUREL_EL1:
  879. instr = ARMV8_SYS(SYSTEM_ATS12E1R, 0);
  880. /* can only execute instruction at EL2 */
  881. target_mode = ARMV8_64_EL2H;
  882. break;
  883. case SYSTEM_CUREL_EL2:
  884. instr = ARMV8_SYS(SYSTEM_ATS1E2R, 0);
  885. break;
  886. case SYSTEM_CUREL_EL3:
  887. instr = ARMV8_SYS(SYSTEM_ATS1E3R, 0);
  888. break;
  889. default:
  890. break;
  891. };
  892. if (target_mode != ARM_MODE_ANY)
  893. armv8_dpm_modeswitch(dpm, target_mode);
  894. /* write VA to R0 and execute translation instruction */
  895. retval = dpm->instr_write_data_r0_64(dpm, instr, (uint64_t)va);
  896. /* read result from PAR_EL1 */
  897. if (retval == ERROR_OK)
  898. retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_PAR_EL1, 0), &par);
  899. /* switch back to saved PE mode */
  900. if (target_mode != ARM_MODE_ANY)
  901. armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
  902. dpm->finish(dpm);
  903. if (retval != ERROR_OK)
  904. return retval;
  905. if (par & 1) {
  906. LOG_ERROR("Address translation failed at stage %i, FST=%x, PTW=%i",
  907. ((int)(par >> 9) & 1)+1, (int)(par >> 1) & 0x3f, (int)(par >> 8) & 1);
  908. *val = 0;
  909. retval = ERROR_FAIL;
  910. } else {
  911. *val = (par & 0xFFFFFFFFF000UL) | (va & 0xFFF);
  912. if (meminfo) {
  913. int SH = (par >> 7) & 3;
  914. int NS = (par >> 9) & 1;
  915. int ATTR = (par >> 56) & 0xFF;
  916. char *memtype = (ATTR & 0xF0) == 0 ? "Device Memory" : "Normal Memory";
  917. LOG_USER("%sshareable, %s",
  918. shared_name[SH], secure_name[NS]);
  919. LOG_USER("%s", memtype);
  920. }
  921. }
  922. return retval;
  923. }
  924. COMMAND_HANDLER(armv8_handle_exception_catch_command)
  925. {
  926. struct target *target = get_current_target(CMD_CTX);
  927. struct armv8_common *armv8 = target_to_armv8(target);
  928. uint32_t edeccr = 0;
  929. unsigned int argp = 0;
  930. int retval;
  931. static const struct jim_nvp nvp_ecatch_modes[] = {
  932. { .name = "off", .value = 0 },
  933. { .name = "nsec_el1", .value = (1 << 5) },
  934. { .name = "nsec_el2", .value = (2 << 5) },
  935. { .name = "nsec_el12", .value = (3 << 5) },
  936. { .name = "sec_el1", .value = (1 << 1) },
  937. { .name = "sec_el3", .value = (4 << 1) },
  938. { .name = "sec_el13", .value = (5 << 1) },
  939. { .name = NULL, .value = -1 },
  940. };
  941. const struct jim_nvp *n;
  942. if (CMD_ARGC == 0) {
  943. const char *sec = NULL, *nsec = NULL;
  944. retval = mem_ap_read_atomic_u32(armv8->debug_ap,
  945. armv8->debug_base + CPUV8_DBG_ECCR, &edeccr);
  946. if (retval != ERROR_OK)
  947. return retval;
  948. n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
  949. if (n->name)
  950. sec = n->name;
  951. n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
  952. if (n->name)
  953. nsec = n->name;
  954. if (!sec || !nsec) {
  955. LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
  956. return ERROR_FAIL;
  957. }
  958. command_print(CMD, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
  959. return ERROR_OK;
  960. }
  961. while (CMD_ARGC > argp) {
  962. n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
  963. if (!n->name) {
  964. LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
  965. return ERROR_FAIL;
  966. }
  967. LOG_DEBUG("found: %s", n->name);
  968. edeccr |= n->value;
  969. argp++;
  970. }
  971. retval = mem_ap_write_atomic_u32(armv8->debug_ap,
  972. armv8->debug_base + CPUV8_DBG_ECCR, edeccr);
  973. if (retval != ERROR_OK)
  974. return retval;
  975. return ERROR_OK;
  976. }
  977. int armv8_handle_cache_info_command(struct command_invocation *cmd,
  978. struct armv8_cache_common *armv8_cache)
  979. {
  980. if (armv8_cache->info == -1) {
  981. command_print(cmd, "cache not yet identified");
  982. return ERROR_OK;
  983. }
  984. if (armv8_cache->display_cache_info)
  985. armv8_cache->display_cache_info(cmd, armv8_cache);
  986. return ERROR_OK;
  987. }
  988. static int armv8_setup_semihosting(struct target *target, int enable)
  989. {
  990. return ERROR_OK;
  991. }
  992. int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
  993. {
  994. struct arm *arm = &armv8->arm;
  995. arm->arch_info = armv8;
  996. target->arch_info = &armv8->arm;
  997. arm->setup_semihosting = armv8_setup_semihosting;
  998. /* target is useful in all function arm v4 5 compatible */
  999. armv8->arm.target = target;
  1000. armv8->arm.common_magic = ARM_COMMON_MAGIC;
  1001. armv8->common_magic = ARMV8_COMMON_MAGIC;
  1002. armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
  1003. armv8->armv8_mmu.armv8_cache.info = -1;
  1004. armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
  1005. armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
  1006. return ERROR_OK;
  1007. }
  1008. static int armv8_aarch64_state(struct target *target)
  1009. {
  1010. struct arm *arm = target_to_arm(target);
  1011. if (arm->common_magic != ARM_COMMON_MAGIC) {
  1012. LOG_ERROR("BUG: called for a non-ARM target");
  1013. return ERROR_FAIL;
  1014. }
  1015. LOG_USER("%s halted in %s state due to %s, current mode: %s\n"
  1016. "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
  1017. target_name(target),
  1018. armv8_state_strings[arm->core_state],
  1019. debug_reason_name(target),
  1020. armv8_mode_name(arm->core_mode),
  1021. buf_get_u32(arm->cpsr->value, 0, 32),
  1022. buf_get_u64(arm->pc->value, 0, 64),
  1023. (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "");
  1024. return ERROR_OK;
  1025. }
  1026. int armv8_arch_state(struct target *target)
  1027. {
  1028. static const char * const state[] = {
  1029. "disabled", "enabled"
  1030. };
  1031. struct armv8_common *armv8 = target_to_armv8(target);
  1032. struct arm *arm = &armv8->arm;
  1033. if (armv8->common_magic != ARMV8_COMMON_MAGIC) {
  1034. LOG_ERROR("BUG: called for a non-Armv8 target");
  1035. return ERROR_COMMAND_SYNTAX_ERROR;
  1036. }
  1037. if (arm->core_state == ARM_STATE_AARCH64)
  1038. armv8_aarch64_state(target);
  1039. else
  1040. arm_arch_state(target);
  1041. LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
  1042. state[armv8->armv8_mmu.mmu_enabled],
  1043. state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
  1044. state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
  1045. if (arm->core_mode == ARM_MODE_ABT)
  1046. armv8_show_fault_registers(target);
  1047. if (target->debug_reason == DBG_REASON_WATCHPOINT)
  1048. LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
  1049. return ERROR_OK;
  1050. }
  1051. static struct reg_data_type aarch64_vector_base_types[] = {
  1052. {REG_TYPE_IEEE_DOUBLE, "ieee_double", 0, {NULL} },
  1053. {REG_TYPE_UINT64, "uint64", 0, {NULL} },
  1054. {REG_TYPE_INT64, "int64", 0, {NULL} },
  1055. {REG_TYPE_IEEE_SINGLE, "ieee_single", 0, {NULL} },
  1056. {REG_TYPE_UINT32, "uint32", 0, {NULL} },
  1057. {REG_TYPE_INT32, "int32", 0, {NULL} },
  1058. {REG_TYPE_UINT16, "uint16", 0, {NULL} },
  1059. {REG_TYPE_INT16, "int16", 0, {NULL} },
  1060. {REG_TYPE_UINT8, "uint8", 0, {NULL} },
  1061. {REG_TYPE_INT8, "int8", 0, {NULL} },
  1062. {REG_TYPE_UINT128, "uint128", 0, {NULL} },
  1063. {REG_TYPE_INT128, "int128", 0, {NULL} }
  1064. };
  1065. static struct reg_data_type_vector aarch64_vector_types[] = {
  1066. {aarch64_vector_base_types + 0, 2},
  1067. {aarch64_vector_base_types + 1, 2},
  1068. {aarch64_vector_base_types + 2, 2},
  1069. {aarch64_vector_base_types + 3, 4},
  1070. {aarch64_vector_base_types + 4, 4},
  1071. {aarch64_vector_base_types + 5, 4},
  1072. {aarch64_vector_base_types + 6, 8},
  1073. {aarch64_vector_base_types + 7, 8},
  1074. {aarch64_vector_base_types + 8, 16},
  1075. {aarch64_vector_base_types + 9, 16},
  1076. {aarch64_vector_base_types + 10, 01},
  1077. {aarch64_vector_base_types + 11, 01},
  1078. };
  1079. static struct reg_data_type aarch64_fpu_vector[] = {
  1080. {REG_TYPE_ARCH_DEFINED, "v2d", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 0} },
  1081. {REG_TYPE_ARCH_DEFINED, "v2u", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 1} },
  1082. {REG_TYPE_ARCH_DEFINED, "v2i", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 2} },
  1083. {REG_TYPE_ARCH_DEFINED, "v4f", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 3} },
  1084. {REG_TYPE_ARCH_DEFINED, "v4u", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 4} },
  1085. {REG_TYPE_ARCH_DEFINED, "v4i", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 5} },
  1086. {REG_TYPE_ARCH_DEFINED, "v8u", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 6} },
  1087. {REG_TYPE_ARCH_DEFINED, "v8i", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 7} },
  1088. {REG_TYPE_ARCH_DEFINED, "v16u", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 8} },
  1089. {REG_TYPE_ARCH_DEFINED, "v16i", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 9} },
  1090. {REG_TYPE_ARCH_DEFINED, "v1u", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 10} },
  1091. {REG_TYPE_ARCH_DEFINED, "v1i", REG_TYPE_CLASS_VECTOR, {aarch64_vector_types + 11} },
  1092. };
  1093. static struct reg_data_type_union_field aarch64_union_fields_vnd[] = {
  1094. {"f", aarch64_fpu_vector + 0, aarch64_union_fields_vnd + 1},
  1095. {"u", aarch64_fpu_vector + 1, aarch64_union_fields_vnd + 2},
  1096. {"s", aarch64_fpu_vector + 2, NULL},
  1097. };
  1098. static struct reg_data_type_union_field aarch64_union_fields_vns[] = {
  1099. {"f", aarch64_fpu_vector + 3, aarch64_union_fields_vns + 1},
  1100. {"u", aarch64_fpu_vector + 4, aarch64_union_fields_vns + 2},
  1101. {"s", aarch64_fpu_vector + 5, NULL},
  1102. };
  1103. static struct reg_data_type_union_field aarch64_union_fields_vnh[] = {
  1104. {"u", aarch64_fpu_vector + 6, aarch64_union_fields_vnh + 1},
  1105. {"s", aarch64_fpu_vector + 7, NULL},
  1106. };
  1107. static struct reg_data_type_union_field aarch64_union_fields_vnb[] = {
  1108. {"u", aarch64_fpu_vector + 8, aarch64_union_fields_vnb + 1},
  1109. {"s", aarch64_fpu_vector + 9, NULL},
  1110. };
  1111. static struct reg_data_type_union_field aarch64_union_fields_vnq[] = {
  1112. {"u", aarch64_fpu_vector + 10, aarch64_union_fields_vnq + 1},
  1113. {"s", aarch64_fpu_vector + 11, NULL},
  1114. };
  1115. static struct reg_data_type_union aarch64_union_types[] = {
  1116. {aarch64_union_fields_vnd},
  1117. {aarch64_union_fields_vns},
  1118. {aarch64_union_fields_vnh},
  1119. {aarch64_union_fields_vnb},
  1120. {aarch64_union_fields_vnq},
  1121. };
  1122. static struct reg_data_type aarch64_fpu_union[] = {
  1123. {REG_TYPE_ARCH_DEFINED, "vnd", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 0} },
  1124. {REG_TYPE_ARCH_DEFINED, "vns", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 1} },
  1125. {REG_TYPE_ARCH_DEFINED, "vnh", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 2} },
  1126. {REG_TYPE_ARCH_DEFINED, "vnb", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 3} },
  1127. {REG_TYPE_ARCH_DEFINED, "vnq", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 4} },
  1128. };
  1129. static struct reg_data_type_union_field aarch64v_union_fields[] = {
  1130. {"d", aarch64_fpu_union + 0, aarch64v_union_fields + 1},
  1131. {"s", aarch64_fpu_union + 1, aarch64v_union_fields + 2},
  1132. {"h", aarch64_fpu_union + 2, aarch64v_union_fields + 3},
  1133. {"b", aarch64_fpu_union + 3, aarch64v_union_fields + 4},
  1134. {"q", aarch64_fpu_union + 4, NULL},
  1135. };
  1136. static struct reg_data_type_union aarch64v_union[] = {
  1137. {aarch64v_union_fields}
  1138. };
  1139. static struct reg_data_type aarch64v[] = {
  1140. {REG_TYPE_ARCH_DEFINED, "aarch64v", REG_TYPE_CLASS_UNION,
  1141. {.reg_type_union = aarch64v_union} },
  1142. };
  1143. static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
  1144. { 0, 0, REG_TYPE_UINT8 },
  1145. { 2, 3, REG_TYPE_UINT8 },
  1146. { 4, 4, REG_TYPE_UINT8 },
  1147. { 6, 6, REG_TYPE_BOOL },
  1148. { 7, 7, REG_TYPE_BOOL },
  1149. { 8, 8, REG_TYPE_BOOL },
  1150. { 9, 9, REG_TYPE_BOOL },
  1151. { 20, 20, REG_TYPE_BOOL },
  1152. { 21, 21, REG_TYPE_BOOL },
  1153. { 28, 28, REG_TYPE_BOOL },
  1154. { 29, 29, REG_TYPE_BOOL },
  1155. { 30, 30, REG_TYPE_BOOL },
  1156. { 31, 31, REG_TYPE_BOOL },
  1157. };
  1158. static struct reg_data_type_flags_field aarch64_cpsr_fields[] = {
  1159. { "SP", aarch64_cpsr_bits + 0, aarch64_cpsr_fields + 1 },
  1160. { "EL", aarch64_cpsr_bits + 1, aarch64_cpsr_fields + 2 },
  1161. { "nRW", aarch64_cpsr_bits + 2, aarch64_cpsr_fields + 3 },
  1162. { "F", aarch64_cpsr_bits + 3, aarch64_cpsr_fields + 4 },
  1163. { "I", aarch64_cpsr_bits + 4, aarch64_cpsr_fields + 5 },
  1164. { "A", aarch64_cpsr_bits + 5, aarch64_cpsr_fields + 6 },
  1165. { "D", aarch64_cpsr_bits + 6, aarch64_cpsr_fields + 7 },
  1166. { "IL", aarch64_cpsr_bits + 7, aarch64_cpsr_fields + 8 },
  1167. { "SS", aarch64_cpsr_bits + 8, aarch64_cpsr_fields + 9 },
  1168. { "V", aarch64_cpsr_bits + 9, aarch64_cpsr_fields + 10 },
  1169. { "C", aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
  1170. { "Z", aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
  1171. { "N", aarch64_cpsr_bits + 12, NULL }
  1172. };
  1173. static struct reg_data_type_flags aarch64_cpsr_flags[] = {
  1174. { 4, aarch64_cpsr_fields }
  1175. };
  1176. static struct reg_data_type aarch64_flags_cpsr[] = {
  1177. {REG_TYPE_ARCH_DEFINED, "cpsr_flags", REG_TYPE_CLASS_FLAGS,
  1178. {.reg_type_flags = aarch64_cpsr_flags} },
  1179. };
  1180. static const struct {
  1181. unsigned id;
  1182. const char *name;
  1183. unsigned bits;
  1184. enum arm_mode mode;
  1185. enum reg_type type;
  1186. const char *group;
  1187. const char *feature;
  1188. struct reg_data_type *data_type;
  1189. } armv8_regs[] = {
  1190. { ARMV8_R0, "x0", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1191. { ARMV8_R1, "x1", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1192. { ARMV8_R2, "x2", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1193. { ARMV8_R3, "x3", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1194. { ARMV8_R4, "x4", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1195. { ARMV8_R5, "x5", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1196. { ARMV8_R6, "x6", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1197. { ARMV8_R7, "x7", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1198. { ARMV8_R8, "x8", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1199. { ARMV8_R9, "x9", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1200. { ARMV8_R10, "x10", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1201. { ARMV8_R11, "x11", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1202. { ARMV8_R12, "x12", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1203. { ARMV8_R13, "x13", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1204. { ARMV8_R14, "x14", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1205. { ARMV8_R15, "x15", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1206. { ARMV8_R16, "x16", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1207. { ARMV8_R17, "x17", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1208. { ARMV8_R18, "x18", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1209. { ARMV8_R19, "x19", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1210. { ARMV8_R20, "x20", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1211. { ARMV8_R21, "x21", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1212. { ARMV8_R22, "x22", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1213. { ARMV8_R23, "x23", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1214. { ARMV8_R24, "x24", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1215. { ARMV8_R25, "x25", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1216. { ARMV8_R26, "x26", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1217. { ARMV8_R27, "x27", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1218. { ARMV8_R28, "x28", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1219. { ARMV8_R29, "x29", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1220. { ARMV8_R30, "x30", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
  1221. { ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
  1222. { ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
  1223. { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
  1224. "general", "org.gnu.gdb.aarch64.core", aarch64_flags_cpsr},
  1225. { ARMV8_V0, "v0", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1226. { ARMV8_V1, "v1", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1227. { ARMV8_V2, "v2", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1228. { ARMV8_V3, "v3", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1229. { ARMV8_V4, "v4", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1230. { ARMV8_V5, "v5", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1231. { ARMV8_V6, "v6", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1232. { ARMV8_V7, "v7", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1233. { ARMV8_V8, "v8", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1234. { ARMV8_V9, "v9", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1235. { ARMV8_V10, "v10", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1236. { ARMV8_V11, "v11", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1237. { ARMV8_V12, "v12", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1238. { ARMV8_V13, "v13", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1239. { ARMV8_V14, "v14", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1240. { ARMV8_V15, "v15", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1241. { ARMV8_V16, "v16", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1242. { ARMV8_V17, "v17", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1243. { ARMV8_V18, "v18", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1244. { ARMV8_V19, "v19", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1245. { ARMV8_V20, "v20", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1246. { ARMV8_V21, "v21", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1247. { ARMV8_V22, "v22", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1248. { ARMV8_V23, "v23", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1249. { ARMV8_V24, "v24", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1250. { ARMV8_V25, "v25", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1251. { ARMV8_V26, "v26", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1252. { ARMV8_V27, "v27", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1253. { ARMV8_V28, "v28", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1254. { ARMV8_V29, "v29", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1255. { ARMV8_V30, "v30", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1256. { ARMV8_V31, "v31", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
  1257. { ARMV8_FPSR, "fpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "simdfp", "org.gnu.gdb.aarch64.fpu", NULL},
  1258. { ARMV8_FPCR, "fpcr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "simdfp", "org.gnu.gdb.aarch64.fpu", NULL},
  1259. { ARMV8_ELR_EL1, "ELR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
  1260. NULL},
  1261. { ARMV8_ESR_EL1, "ESR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
  1262. NULL},
  1263. { ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
  1264. NULL},
  1265. { ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
  1266. NULL},
  1267. { ARMV8_ESR_EL2, "ESR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
  1268. NULL},
  1269. { ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
  1270. NULL},
  1271. { ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
  1272. NULL},
  1273. { ARMV8_ESR_EL3, "ESR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
  1274. NULL},
  1275. { ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
  1276. NULL},
  1277. };
  1278. static const struct {
  1279. unsigned id;
  1280. unsigned mapping;
  1281. const char *name;
  1282. unsigned bits;
  1283. enum arm_mode mode;
  1284. enum reg_type type;
  1285. const char *group;
  1286. const char *feature;
  1287. } armv8_regs32[] = {
  1288. { ARMV8_R0, 0, "r0", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1289. { ARMV8_R1, 0, "r1", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1290. { ARMV8_R2, 0, "r2", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1291. { ARMV8_R3, 0, "r3", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1292. { ARMV8_R4, 0, "r4", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1293. { ARMV8_R5, 0, "r5", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1294. { ARMV8_R6, 0, "r6", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1295. { ARMV8_R7, 0, "r7", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1296. { ARMV8_R8, 0, "r8", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1297. { ARMV8_R9, 0, "r9", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1298. { ARMV8_R10, 0, "r10", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1299. { ARMV8_R11, 0, "r11", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1300. { ARMV8_R12, 0, "r12", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1301. { ARMV8_R13, 0, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
  1302. { ARMV8_R14, 0, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
  1303. { ARMV8_PC, 0, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
  1304. { ARMV8_xPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
  1305. { ARMV8_V0, 0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1306. { ARMV8_V0, 8, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1307. { ARMV8_V1, 0, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1308. { ARMV8_V1, 8, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1309. { ARMV8_V2, 0, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1310. { ARMV8_V2, 8, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1311. { ARMV8_V3, 0, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1312. { ARMV8_V3, 8, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1313. { ARMV8_V4, 0, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1314. { ARMV8_V4, 8, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1315. { ARMV8_V5, 0, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1316. { ARMV8_V5, 8, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1317. { ARMV8_V6, 0, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1318. { ARMV8_V6, 8, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1319. { ARMV8_V7, 0, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1320. { ARMV8_V7, 8, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1321. { ARMV8_V8, 0, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1322. { ARMV8_V8, 8, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1323. { ARMV8_V9, 0, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1324. { ARMV8_V9, 8, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1325. { ARMV8_V10, 0, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1326. { ARMV8_V10, 8, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1327. { ARMV8_V11, 0, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1328. { ARMV8_V11, 8, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1329. { ARMV8_V12, 0, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1330. { ARMV8_V12, 8, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1331. { ARMV8_V13, 0, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1332. { ARMV8_V13, 8, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1333. { ARMV8_V14, 0, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1334. { ARMV8_V14, 8, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1335. { ARMV8_V15, 0, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1336. { ARMV8_V15, 8, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
  1337. { ARMV8_FPSR, 0, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "float", "org.gnu.gdb.arm.vfp"},
  1338. };
  1339. #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
  1340. #define ARMV8_NUM_REGS32 ARRAY_SIZE(armv8_regs32)
  1341. static int armv8_get_core_reg(struct reg *reg)
  1342. {
  1343. struct arm_reg *armv8_reg = reg->arch_info;
  1344. struct target *target = armv8_reg->target;
  1345. struct arm *arm = target_to_arm(target);
  1346. if (target->state != TARGET_HALTED)
  1347. return ERROR_TARGET_NOT_HALTED;
  1348. return arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
  1349. }
  1350. static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
  1351. {
  1352. struct arm_reg *armv8_reg = reg->arch_info;
  1353. struct target *target = armv8_reg->target;
  1354. struct arm *arm = target_to_arm(target);
  1355. uint64_t value = buf_get_u64(buf, 0, reg->size);
  1356. if (target->state != TARGET_HALTED)
  1357. return ERROR_TARGET_NOT_HALTED;
  1358. if (reg->size <= 64) {
  1359. if (reg == arm->cpsr)
  1360. armv8_set_cpsr(arm, (uint32_t)value);
  1361. else {
  1362. buf_set_u64(reg->value, 0, reg->size, value);
  1363. reg->valid = true;
  1364. }
  1365. } else if (reg->size <= 128) {
  1366. uint64_t hvalue = buf_get_u64(buf + 8, 0, reg->size - 64);
  1367. buf_set_u64(reg->value, 0, 64, value);
  1368. buf_set_u64(reg->value + 8, 0, reg->size - 64, hvalue);
  1369. reg->valid = true;
  1370. }
  1371. reg->dirty = true;
  1372. return ERROR_OK;
  1373. }
  1374. static const struct reg_arch_type armv8_reg_type = {
  1375. .get = armv8_get_core_reg,
  1376. .set = armv8_set_core_reg,
  1377. };
  1378. static int armv8_get_core_reg32(struct reg *reg)
  1379. {
  1380. struct arm_reg *armv8_reg = reg->arch_info;
  1381. struct target *target = armv8_reg->target;
  1382. struct arm *arm = target_to_arm(target);
  1383. struct reg_cache *cache = arm->core_cache;
  1384. struct reg *reg64;
  1385. int retval;
  1386. if (target->state != TARGET_HALTED)
  1387. return ERROR_TARGET_NOT_HALTED;
  1388. /* get the corresponding Aarch64 register */
  1389. reg64 = cache->reg_list + armv8_reg->num;
  1390. if (reg64->valid) {
  1391. reg->valid = true;
  1392. return ERROR_OK;
  1393. }
  1394. retval = arm->read_core_reg(target, reg64, armv8_reg->num, arm->core_mode);
  1395. if (retval == ERROR_OK)
  1396. reg->valid = reg64->valid;
  1397. return retval;
  1398. }
  1399. static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
  1400. {
  1401. struct arm_reg *armv8_reg = reg->arch_info;
  1402. struct target *target = armv8_reg->target;
  1403. struct arm *arm = target_to_arm(target);
  1404. struct reg_cache *cache = arm->core_cache;
  1405. struct reg *reg64 = cache->reg_list + armv8_reg->num;
  1406. uint32_t value = buf_get_u32(buf, 0, 32);
  1407. if (target->state != TARGET_HALTED)
  1408. return ERROR_TARGET_NOT_HALTED;
  1409. if (reg64 == arm->cpsr) {
  1410. armv8_set_cpsr(arm, value);
  1411. } else {
  1412. if (reg->size <= 32)
  1413. buf_set_u32(reg->value, 0, 32, value);
  1414. else if (reg->size <= 64) {
  1415. uint64_t value64 = buf_get_u64(buf, 0, 64);
  1416. buf_set_u64(reg->value, 0, 64, value64);
  1417. }
  1418. reg->valid = true;
  1419. reg64->valid = true;
  1420. }
  1421. reg64->dirty = true;
  1422. return ERROR_OK;
  1423. }
  1424. static const struct reg_arch_type armv8_reg32_type = {
  1425. .get = armv8_get_core_reg32,
  1426. .set = armv8_set_core_reg32,
  1427. };
  1428. /** Builds cache of architecturally defined registers. */
  1429. struct reg_cache *armv8_build_reg_cache(struct target *target)
  1430. {
  1431. struct armv8_common *armv8 = target_to_armv8(target);
  1432. struct arm *arm = &armv8->arm;
  1433. int num_regs = ARMV8_NUM_REGS;
  1434. int num_regs32 = ARMV8_NUM_REGS32;
  1435. struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
  1436. struct reg_cache *cache = malloc(sizeof(struct reg_cache));
  1437. struct reg_cache *cache32 = malloc(sizeof(struct reg_cache));
  1438. struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
  1439. struct reg *reg_list32 = calloc(num_regs32, sizeof(struct reg));
  1440. struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
  1441. struct reg_feature *feature;
  1442. int i;
  1443. /* Build the process context cache */
  1444. cache->name = "Aarch64 registers";
  1445. cache->next = cache32;
  1446. cache->reg_list = reg_list;
  1447. cache->num_regs = num_regs;
  1448. for (i = 0; i < num_regs; i++) {
  1449. arch_info[i].num = armv8_regs[i].id;
  1450. arch_info[i].mode = armv8_regs[i].mode;
  1451. arch_info[i].target = target;
  1452. arch_info[i].arm = arm;
  1453. reg_list[i].name = armv8_regs[i].name;
  1454. reg_list[i].size = armv8_regs[i].bits;
  1455. reg_list[i].value = &arch_info[i].value[0];
  1456. reg_list[i].type = &armv8_reg_type;
  1457. reg_list[i].arch_info = &arch_info[i];
  1458. reg_list[i].group = armv8_regs[i].group;
  1459. reg_list[i].number = i;
  1460. reg_list[i].exist = true;
  1461. reg_list[i].caller_save = true; /* gdb defaults to true */
  1462. feature = calloc(1, sizeof(struct reg_feature));
  1463. if (feature) {
  1464. feature->name = armv8_regs[i].feature;
  1465. reg_list[i].feature = feature;
  1466. } else
  1467. LOG_ERROR("unable to allocate feature list");
  1468. reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
  1469. if (reg_list[i].reg_data_type) {
  1470. if (!armv8_regs[i].data_type)
  1471. reg_list[i].reg_data_type->type = armv8_regs[i].type;
  1472. else
  1473. *reg_list[i].reg_data_type = *armv8_regs[i].data_type;
  1474. } else
  1475. LOG_ERROR("unable to allocate reg type list");
  1476. }
  1477. arm->cpsr = reg_list + ARMV8_xPSR;
  1478. arm->pc = reg_list + ARMV8_PC;
  1479. arm->core_cache = cache;
  1480. /* shadow cache for ARM mode registers */
  1481. cache32->name = "Aarch32 registers";
  1482. cache32->next = NULL;
  1483. cache32->reg_list = reg_list32;
  1484. cache32->num_regs = num_regs32;
  1485. for (i = 0; i < num_regs32; i++) {
  1486. reg_list32[i].name = armv8_regs32[i].name;
  1487. reg_list32[i].size = armv8_regs32[i].bits;
  1488. reg_list32[i].value = &arch_info[armv8_regs32[i].id].value[armv8_regs32[i].mapping];
  1489. reg_list32[i].type = &armv8_reg32_type;
  1490. reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];
  1491. reg_list32[i].group = armv8_regs32[i].group;
  1492. reg_list32[i].number = i;
  1493. reg_list32[i].exist = true;
  1494. reg_list32[i].caller_save = true;
  1495. feature = calloc(1, sizeof(struct reg_feature));
  1496. if (feature) {
  1497. feature->name = armv8_regs32[i].feature;
  1498. reg_list32[i].feature = feature;
  1499. } else
  1500. LOG_ERROR("unable to allocate feature list");
  1501. reg_list32[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
  1502. if (reg_list32[i].reg_data_type)
  1503. reg_list32[i].reg_data_type->type = armv8_regs32[i].type;
  1504. else
  1505. LOG_ERROR("unable to allocate reg type list");
  1506. }
  1507. (*cache_p) = cache;
  1508. return cache;
  1509. }
  1510. struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
  1511. {
  1512. struct reg *r;
  1513. if (regnum > (ARMV8_LAST_REG - 1))
  1514. return NULL;
  1515. r = arm->core_cache->reg_list + regnum;
  1516. return r;
  1517. }
  1518. static void armv8_free_cache(struct reg_cache *cache, bool regs32)
  1519. {
  1520. struct reg *reg;
  1521. unsigned int i;
  1522. if (!cache)
  1523. return;
  1524. for (i = 0; i < cache->num_regs; i++) {
  1525. reg = &cache->reg_list[i];
  1526. free(reg->feature);
  1527. free(reg->reg_data_type);
  1528. }
  1529. if (!regs32)
  1530. free(cache->reg_list[0].arch_info);
  1531. free(cache->reg_list);
  1532. free(cache);
  1533. }
  1534. void armv8_free_reg_cache(struct target *target)
  1535. {
  1536. struct armv8_common *armv8 = target_to_armv8(target);
  1537. struct arm *arm = &armv8->arm;
  1538. struct reg_cache *cache = NULL, *cache32 = NULL;
  1539. cache = arm->core_cache;
  1540. if (cache)
  1541. cache32 = cache->next;
  1542. armv8_free_cache(cache32, true);
  1543. armv8_free_cache(cache, false);
  1544. arm->core_cache = NULL;
  1545. }
  1546. const struct command_registration armv8_command_handlers[] = {
  1547. {
  1548. .name = "catch_exc",
  1549. .handler = armv8_handle_exception_catch_command,
  1550. .mode = COMMAND_EXEC,
  1551. .help = "configure exception catch",
  1552. .usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]",
  1553. },
  1554. COMMAND_REGISTRATION_DONE
  1555. };
  1556. const char *armv8_get_gdb_arch(struct target *target)
  1557. {
  1558. struct arm *arm = target_to_arm(target);
  1559. return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm";
  1560. }
  1561. int armv8_get_gdb_reg_list(struct target *target,
  1562. struct reg **reg_list[], int *reg_list_size,
  1563. enum target_register_class reg_class)
  1564. {
  1565. struct arm *arm = target_to_arm(target);
  1566. int i;
  1567. if (arm->core_state == ARM_STATE_AARCH64) {
  1568. LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
  1569. switch (reg_class) {
  1570. case REG_CLASS_GENERAL:
  1571. *reg_list_size = ARMV8_V0;
  1572. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  1573. for (i = 0; i < *reg_list_size; i++)
  1574. (*reg_list)[i] = armv8_reg_current(arm, i);
  1575. return ERROR_OK;
  1576. case REG_CLASS_ALL:
  1577. *reg_list_size = ARMV8_LAST_REG;
  1578. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  1579. for (i = 0; i < *reg_list_size; i++)
  1580. (*reg_list)[i] = armv8_reg_current(arm, i);
  1581. return ERROR_OK;
  1582. default:
  1583. LOG_ERROR("not a valid register class type in query.");
  1584. return ERROR_FAIL;
  1585. }
  1586. } else {
  1587. struct reg_cache *cache32 = arm->core_cache->next;
  1588. LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
  1589. switch (reg_class) {
  1590. case REG_CLASS_GENERAL:
  1591. *reg_list_size = ARMV8_R14 + 3;
  1592. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  1593. for (i = 0; i < *reg_list_size; i++)
  1594. (*reg_list)[i] = cache32->reg_list + i;
  1595. return ERROR_OK;
  1596. case REG_CLASS_ALL:
  1597. *reg_list_size = cache32->num_regs;
  1598. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  1599. for (i = 0; i < *reg_list_size; i++)
  1600. (*reg_list)[i] = cache32->reg_list + i;
  1601. return ERROR_OK;
  1602. default:
  1603. LOG_ERROR("not a valid register class type in query.");
  1604. return ERROR_FAIL;
  1605. }
  1606. }
  1607. }
  1608. int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
  1609. {
  1610. uint32_t tmp;
  1611. /* Read register */
  1612. int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
  1613. armv8->debug_base + reg, &tmp);
  1614. if (retval != ERROR_OK)
  1615. return retval;
  1616. /* clear bitfield */
  1617. tmp &= ~mask;
  1618. /* put new value */
  1619. tmp |= value & mask;
  1620. /* write new value */
  1621. retval = mem_ap_write_atomic_u32(armv8->debug_ap,
  1622. armv8->debug_base + reg, tmp);
  1623. return retval;
  1624. }