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  1. /*
  2. * Copyright (C) 2015 by Matthias Welwarsky <matthias.welwarsky@sysgo.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #ifdef HAVE_CONFIG_H
  16. #include "config.h"
  17. #endif
  18. #include <stdint.h>
  19. #include <stdbool.h>
  20. #include "armv8.h"
  21. #include "armv8_opcodes.h"
  22. static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
  23. [READ_REG_CTR] = ARMV8_MRS(SYSTEM_CTR, 0),
  24. [READ_REG_CLIDR] = ARMV8_MRS(SYSTEM_CLIDR, 0),
  25. [READ_REG_CSSELR] = ARMV8_MRS(SYSTEM_CSSELR, 0),
  26. [READ_REG_CCSIDR] = ARMV8_MRS(SYSTEM_CCSIDR, 0),
  27. [WRITE_REG_CSSELR] = ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
  28. [READ_REG_MPIDR] = ARMV8_MRS(SYSTEM_MPIDR, 0),
  29. [READ_REG_DTRRX] = ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
  30. [WRITE_REG_DTRTX] = ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0),
  31. [WRITE_REG_DSPSR] = ARMV8_MSR_DSPSR(0),
  32. [READ_REG_DSPSR] = ARMV8_MRS_DSPSR(0),
  33. [ARMV8_OPC_DSB_SY] = ARMV8_DSB_SY,
  34. [ARMV8_OPC_DCPS] = ARMV8_DCPS(0, 11),
  35. [ARMV8_OPC_DRPS] = ARMV8_DRPS,
  36. [ARMV8_OPC_ISB_SY] = ARMV8_ISB,
  37. [ARMV8_OPC_DCCISW] = ARMV8_SYS(SYSTEM_DCCISW, 0),
  38. [ARMV8_OPC_DCCIVAC] = ARMV8_SYS(SYSTEM_DCCIVAC, 0),
  39. [ARMV8_OPC_ICIVAU] = ARMV8_SYS(SYSTEM_ICIVAU, 0),
  40. [ARMV8_OPC_HLT] = ARMV8_HLT(11),
  41. [ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP(1, 0),
  42. [ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP(1, 0),
  43. [ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP(1, 0),
  44. [ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP(1, 0),
  45. [ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP(1, 0),
  46. [ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP(1, 0),
  47. };
  48. static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
  49. [READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
  50. [READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
  51. [READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
  52. [READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
  53. [WRITE_REG_CSSELR] = ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
  54. [READ_REG_MPIDR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
  55. [READ_REG_DTRRX] = ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
  56. [WRITE_REG_DTRTX] = ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
  57. [WRITE_REG_DSPSR] = ARMV8_MCR_DSPSR(0),
  58. [READ_REG_DSPSR] = ARMV8_MRC_DSPSR(0),
  59. [ARMV8_OPC_DSB_SY] = ARMV8_DSB_SY_T1,
  60. [ARMV8_OPC_DCPS] = ARMV8_DCPS_T1(0),
  61. [ARMV8_OPC_DRPS] = ARMV8_ERET_T1,
  62. [ARMV8_OPC_ISB_SY] = ARMV8_ISB_SY_T1,
  63. [ARMV8_OPC_DCCISW] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
  64. [ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
  65. [ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
  66. [ARMV8_OPC_HLT] = ARMV8_HLT_T1(11),
  67. [ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP_T3(1, 0),
  68. [ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP_T3(1, 0),
  69. [ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP_T3(1, 0),
  70. [ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP_T3(1, 0),
  71. [ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP_T3(1, 0),
  72. [ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP_T3(1, 0),
  73. };
  74. void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
  75. {
  76. if (state_is_aarch64)
  77. armv8->opcodes = &a64_opcodes[0];
  78. else
  79. armv8->opcodes = &t32_opcodes[0];
  80. }
  81. uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode code)
  82. {
  83. if ((int)code >= ARMV8_OPC_NUM)
  84. return -1;
  85. return *(armv8->opcodes + code);
  86. }