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openocd/src/target/mips_m4k.c

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  1. /***************************************************************************

  2.  *   Copyright (C) 2008 by Spencer Oliver                                  *

  3.  *   spen@spen-soft.co.uk                                                  *

  4.  *                                                                         *

  5.  *   Copyright (C) 2008 by David T.L. Wong                                 *

  6.  *                                                                         *

  7.  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *

  8.  *                                                                         *

  9.  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *

  10.  *   drasko.draskovic@gmail.com                                            *

  11.  *                                                                         *

  12.  *   This program is free software; you can redistribute it and/or modify  *

  13.  *   it under the terms of the GNU General Public License as published by  *

  14.  *   the Free Software Foundation; either version 2 of the License, or     *

  15.  *   (at your option) any later version.                                   *

  16.  *                                                                         *

  17.  *   This program is distributed in the hope that it will be useful,       *

  18.  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

  19.  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *

  20.  *   GNU General Public License for more details.                          *

  21.  *                                                                         *

  22.  *   You should have received a copy of the GNU General Public License     *

  23.  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *

  24.  ***************************************************************************/

  25. 

  26. #ifdef HAVE_CONFIG_H

  27. #include "config.h"

  28. #endif

  29. 

  30. #include "breakpoints.h"

  31. #include "mips32.h"

  32. #include "mips_m4k.h"

  33. #include "mips32_dmaacc.h"

  34. #include "target_type.h"

  35. #include "register.h"

  36. #include "smp.h"

  37. 

  38. static void mips_m4k_enable_breakpoints(struct target *target);

  39. static void mips_m4k_enable_watchpoints(struct target *target);

  40. static int mips_m4k_set_breakpoint(struct target *target,

  41. 		struct breakpoint *breakpoint);

  42. static int mips_m4k_unset_breakpoint(struct target *target,

  43. 		struct breakpoint *breakpoint);

  44. static int mips_m4k_internal_restore(struct target *target, int current,

  45. 		target_addr_t address, int handle_breakpoints,

  46. 		int debug_execution);

  47. static int mips_m4k_halt(struct target *target);

  48. static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,

  49. 		uint32_t count, const uint8_t *buffer);

  50. 

  51. static int mips_m4k_examine_debug_reason(struct target *target)

  52. {

  53. 	struct mips32_common *mips32 = target_to_mips32(target);

  54. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  55. 	uint32_t break_status;

  56. 	int retval;

  57. 

  58. 	if ((target->debug_reason != DBG_REASON_DBGRQ)

  59. 			&& (target->debug_reason != DBG_REASON_SINGLESTEP)) {

  60. 		if (ejtag_info->debug_caps & EJTAG_DCR_IB) {

  61. 			/* get info about inst breakpoint support */

  62. 			retval = target_read_u32(target,

  63. 				ejtag_info->ejtag_ibs_addr, &break_status);

  64. 			if (retval != ERROR_OK)

  65. 				return retval;

  66. 			if (break_status & 0x1f) {

  67. 				/* we have halted on a  breakpoint */

  68. 				retval = target_write_u32(target,

  69. 					ejtag_info->ejtag_ibs_addr, 0);

  70. 				if (retval != ERROR_OK)

  71. 					return retval;

  72. 				target->debug_reason = DBG_REASON_BREAKPOINT;

  73. 			}

  74. 		}

  75. 

  76. 		if (ejtag_info->debug_caps & EJTAG_DCR_DB) {

  77. 			/* get info about data breakpoint support */

  78. 			retval = target_read_u32(target,

  79. 				ejtag_info->ejtag_dbs_addr, &break_status);

  80. 			if (retval != ERROR_OK)

  81. 				return retval;

  82. 			if (break_status & 0x1f) {

  83. 				/* we have halted on a  breakpoint */

  84. 				retval = target_write_u32(target,

  85. 					ejtag_info->ejtag_dbs_addr, 0);

  86. 				if (retval != ERROR_OK)

  87. 					return retval;

  88. 				target->debug_reason = DBG_REASON_WATCHPOINT;

  89. 			}

  90. 		}

  91. 	}

  92. 

  93. 	return ERROR_OK;

  94. }

  95. 

  96. static int mips_m4k_debug_entry(struct target *target)

  97. {

  98. 	struct mips32_common *mips32 = target_to_mips32(target);

  99. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  100. 

  101. 	mips32_save_context(target);

  102. 

  103. 	/* make sure stepping disabled, SSt bit in CP0 debug register cleared */

  104. 	mips_ejtag_config_step(ejtag_info, 0);

  105. 

  106. 	/* make sure break unit configured */

  107. 	mips32_configure_break_unit(target);

  108. 

  109. 	/* attempt to find halt reason */

  110. 	mips_m4k_examine_debug_reason(target);

  111. 

  112. 	mips32_read_config_regs(target);

  113. 

  114. 	/* default to mips32 isa, it will be changed below if required */

  115. 	mips32->isa_mode = MIPS32_ISA_MIPS32;

  116. 

  117. 	/* other than mips32 only and isa bit set ? */

  118. 	if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1))

  119. 		mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;

  120. 

  121. 	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",

  122. 			buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),

  123. 			target_state_name(target));

  124. 

  125. 	return ERROR_OK;

  126. }

  127. 

  128. static struct target *get_mips_m4k(struct target *target, int32_t coreid)

  129. {

  130. 	struct target_list *head;

  131. 	struct target *curr;

  132. 

  133. 	head = target->head;

  134. 	while (head != (struct target_list *)NULL) {

  135. 		curr = head->target;

  136. 		if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))

  137. 			return curr;

  138. 		head = head->next;

  139. 	}

  140. 	return target;

  141. }

  142. 

  143. static int mips_m4k_halt_smp(struct target *target)

  144. {

  145. 	int retval = ERROR_OK;

  146. 	struct target_list *head;

  147. 	struct target *curr;

  148. 	head = target->head;

  149. 	while (head != (struct target_list *)NULL) {

  150. 		int ret = ERROR_OK;

  151. 		curr = head->target;

  152. 		if ((curr != target) && (curr->state != TARGET_HALTED))

  153. 			ret = mips_m4k_halt(curr);

  154. 

  155. 		if (ret != ERROR_OK) {

  156. 			LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);

  157. 			retval = ret;

  158. 		}

  159. 		head = head->next;

  160. 	}

  161. 	return retval;

  162. }

  163. 

  164. static int update_halt_gdb(struct target *target)

  165. {

  166. 	int retval = ERROR_OK;

  167. 	if (target->gdb_service->core[0] == -1) {

  168. 		target->gdb_service->target = target;

  169. 		target->gdb_service->core[0] = target->coreid;

  170. 		retval = mips_m4k_halt_smp(target);

  171. 	}

  172. 	return retval;

  173. }

  174. 

  175. static int mips_m4k_poll(struct target *target)

  176. {

  177. 	int retval = ERROR_OK;

  178. 	struct mips32_common *mips32 = target_to_mips32(target);

  179. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  180. 	uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;

  181. 	enum target_state prev_target_state = target->state;

  182. 

  183. 	/*  toggle to another core is done by gdb as follow */

  184. 	/*  maint packet J core_id */

  185. 	/*  continue */

  186. 	/*  the next polling trigger an halt event sent to gdb */

  187. 	if ((target->state == TARGET_HALTED) && (target->smp) &&

  188. 		(target->gdb_service) &&

  189. 		(!target->gdb_service->target)) {

  190. 		target->gdb_service->target =

  191. 			get_mips_m4k(target, target->gdb_service->core[1]);

  192. 		target_call_event_callbacks(target, TARGET_EVENT_HALTED);

  193. 		return retval;

  194. 	}

  195. 

  196. 	/* read ejtag control reg */

  197. 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);

  198. 	retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);

  199. 	if (retval != ERROR_OK)

  200. 		return retval;

  201. 

  202. 	ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;

  203. 

  204. 	/* clear this bit before handling polling

  205. 	 * as after reset registers will read zero */

  206. 	if (ejtag_ctrl & EJTAG_CTRL_ROCC) {

  207. 		/* we have detected a reset, clear flag

  208. 		 * otherwise ejtag will not work */

  209. 		ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;

  210. 

  211. 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);

  212. 		retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);

  213. 		if (retval != ERROR_OK)

  214. 			return retval;

  215. 		LOG_DEBUG("Reset Detected");

  216. 	}

  217. 

  218. 	/* check for processor halted */

  219. 	if (ejtag_ctrl & EJTAG_CTRL_BRKST) {

  220. 		if ((target->state != TARGET_HALTED)

  221. 		    && (target->state != TARGET_DEBUG_RUNNING)) {

  222. 			if (target->state == TARGET_UNKNOWN)

  223. 				LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");

  224. 

  225. 			/* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set

  226. 			 * (maybe put on by HALT-ing the board in the previous session).

  227. 			 *

  228. 			 * Force enable debug entry for this session.

  229. 			 */

  230. 			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);

  231. 			target->state = TARGET_HALTED;

  232. 			retval = mips_m4k_debug_entry(target);

  233. 			if (retval != ERROR_OK)

  234. 				return retval;

  235. 

  236. 			if (target->smp &&

  237. 				((prev_target_state == TARGET_RUNNING)

  238. 			     || (prev_target_state == TARGET_RESET))) {

  239. 				retval = update_halt_gdb(target);

  240. 				if (retval != ERROR_OK)

  241. 					return retval;

  242. 			}

  243. 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);

  244. 		} else if (target->state == TARGET_DEBUG_RUNNING) {

  245. 			target->state = TARGET_HALTED;

  246. 

  247. 			retval = mips_m4k_debug_entry(target);

  248. 			if (retval != ERROR_OK)

  249. 				return retval;

  250. 

  251. 			if (target->smp) {

  252. 				retval = update_halt_gdb(target);

  253. 				if (retval != ERROR_OK)

  254. 					return retval;

  255. 			}

  256. 

  257. 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);

  258. 		}

  259. 	} else

  260. 		target->state = TARGET_RUNNING;

  261. 

  262. /*	LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */

  263. 

  264. 	return ERROR_OK;

  265. }

  266. 

  267. static int mips_m4k_halt(struct target *target)

  268. {

  269. 	struct mips32_common *mips32 = target_to_mips32(target);

  270. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  271. 

  272. 	LOG_DEBUG("target->state: %s", target_state_name(target));

  273. 

  274. 	if (target->state == TARGET_HALTED) {

  275. 		LOG_DEBUG("target was already halted");

  276. 		return ERROR_OK;

  277. 	}

  278. 

  279. 	if (target->state == TARGET_UNKNOWN)

  280. 		LOG_WARNING("target was in unknown state when halt was requested");

  281. 

  282. 	if (target->state == TARGET_RESET) {

  283. 		if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {

  284. 			LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");

  285. 			return ERROR_TARGET_FAILURE;

  286. 		} else {

  287. 			/* we came here in a reset_halt or reset_init sequence

  288. 			 * debug entry was already prepared in mips_m4k_assert_reset()

  289. 			 */

  290. 			target->debug_reason = DBG_REASON_DBGRQ;

  291. 

  292. 			return ERROR_OK;

  293. 		}

  294. 	}

  295. 

  296. 	/* break processor */

  297. 	mips_ejtag_enter_debug(ejtag_info);

  298. 

  299. 	target->debug_reason = DBG_REASON_DBGRQ;

  300. 

  301. 	return ERROR_OK;

  302. }

  303. 

  304. static int mips_m4k_assert_reset(struct target *target)

  305. {

  306. 	struct mips_m4k_common *mips_m4k = target_to_m4k(target);

  307. 	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;

  308. 

  309. 	/* TODO: apply hw reset signal in not examined state */

  310. 	if (!(target_was_examined(target))) {

  311. 		LOG_WARNING("Reset is not asserted because the target is not examined.");

  312. 		LOG_WARNING("Use a reset button or power cycle the target.");

  313. 		return ERROR_TARGET_NOT_EXAMINED;

  314. 	}

  315. 

  316. 	LOG_DEBUG("target->state: %s",

  317. 		target_state_name(target));

  318. 

  319. 	enum reset_types jtag_reset_config = jtag_get_reset_config();

  320. 

  321. 	/* some cores support connecting while srst is asserted

  322. 	 * use that mode is it has been configured */

  323. 

  324. 	bool srst_asserted = false;

  325. 

  326. 	if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&

  327. 			(jtag_reset_config & RESET_SRST_NO_GATING)) {

  328. 		jtag_add_reset(0, 1);

  329. 		srst_asserted = true;

  330. 	}

  331. 

  332. 

  333. 	/* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */

  334. 	if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {

  335. 		if (target->reset_halt) {

  336. 			/* use hardware to catch reset */

  337. 			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);

  338. 		} else

  339. 			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);

  340. 	}

  341. 

  342. 	if (jtag_reset_config & RESET_HAS_SRST) {

  343. 		/* here we should issue a srst only, but we may have to assert trst as well */

  344. 		if (jtag_reset_config & RESET_SRST_PULLS_TRST)

  345. 			jtag_add_reset(1, 1);

  346. 		else if (!srst_asserted)

  347. 			jtag_add_reset(0, 1);

  348. 	} else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {

  349. 		target_handle_event(target, TARGET_EVENT_RESET_ASSERT);

  350. 	} else {

  351. 		if (mips_m4k->is_pic32mx) {

  352. 			LOG_DEBUG("Using MTAP reset to reset processor...");

  353. 

  354. 			/* use microchip specific MTAP reset */

  355. 			mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);

  356. 			mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);

  357. 

  358. 			mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);

  359. 			mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);

  360. 			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);

  361. 		} else {

  362. 			/* use ejtag reset - not supported by all cores */

  363. 			uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;

  364. 			LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");

  365. 			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);

  366. 			mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);

  367. 		}

  368. 	}

  369. 

  370. 	target->state = TARGET_RESET;

  371. 	jtag_add_sleep(50000);

  372. 

  373. 	register_cache_invalidate(mips_m4k->mips32.core_cache);

  374. 

  375. 	if (target->reset_halt) {

  376. 		int retval = target_halt(target);

  377. 		if (retval != ERROR_OK)

  378. 			return retval;

  379. 	}

  380. 

  381. 	return ERROR_OK;

  382. }

  383. 

  384. static int mips_m4k_deassert_reset(struct target *target)

  385. {

  386. 	LOG_DEBUG("target->state: %s", target_state_name(target));

  387. 

  388. 	/* deassert reset lines */

  389. 	jtag_add_reset(0, 0);

  390. 

  391. 	return ERROR_OK;

  392. }

  393. 

  394. static int mips_m4k_single_step_core(struct target *target)

  395. {

  396. 	struct mips32_common *mips32 = target_to_mips32(target);

  397. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  398. 

  399. 	/* configure single step mode */

  400. 	mips_ejtag_config_step(ejtag_info, 1);

  401. 

  402. 	/* disable interrupts while stepping */

  403. 	mips32_enable_interrupts(target, 0);

  404. 

  405. 	/* exit debug mode */

  406. 	mips_ejtag_exit_debug(ejtag_info);

  407. 

  408. 	mips_m4k_debug_entry(target);

  409. 

  410. 	return ERROR_OK;

  411. }

  412. 

  413. static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)

  414. {

  415. 	int retval = ERROR_OK;

  416. 	struct target_list *head;

  417. 	struct target *curr;

  418. 

  419. 	head = target->head;

  420. 	while (head != (struct target_list *)NULL) {

  421. 		int ret = ERROR_OK;

  422. 		curr = head->target;

  423. 		if ((curr != target) && (curr->state != TARGET_RUNNING)) {

  424. 			/*  resume current address , not in step mode */

  425. 			ret = mips_m4k_internal_restore(curr, 1, address,

  426. 						   handle_breakpoints, 0);

  427. 

  428. 			if (ret != ERROR_OK) {

  429. 				LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,

  430. 						  curr->coreid, address);

  431. 				retval = ret;

  432. 			}

  433. 		}

  434. 		head = head->next;

  435. 	}

  436. 	return retval;

  437. }

  438. 

  439. static int mips_m4k_internal_restore(struct target *target, int current,

  440. 		target_addr_t address, int handle_breakpoints, int debug_execution)

  441. {

  442. 	struct mips32_common *mips32 = target_to_mips32(target);

  443. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  444. 	struct breakpoint *breakpoint = NULL;

  445. 	uint32_t resume_pc;

  446. 

  447. 	if (target->state != TARGET_HALTED) {

  448. 		LOG_WARNING("target not halted");

  449. 		return ERROR_TARGET_NOT_HALTED;

  450. 	}

  451. 

  452. 	if (!debug_execution) {

  453. 		target_free_all_working_areas(target);

  454. 		mips_m4k_enable_breakpoints(target);

  455. 		mips_m4k_enable_watchpoints(target);

  456. 	}

  457. 

  458. 	/* current = 1: continue on current pc, otherwise continue at <address> */

  459. 	if (!current) {

  460. 		mips_m4k_isa_filter(mips32->isa_imp, &address);

  461. 		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);

  462. 		mips32->core_cache->reg_list[MIPS32_PC].dirty = true;

  463. 		mips32->core_cache->reg_list[MIPS32_PC].valid = true;

  464. 	}

  465. 

  466. 	if ((mips32->isa_imp > 1) &&  debug_execution)	/* if more than one isa supported */

  467. 		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);

  468. 

  469. 	if (!current)

  470. 		resume_pc = address;

  471. 	else

  472. 		resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);

  473. 

  474. 	mips32_restore_context(target);

  475. 

  476. 	/* the front-end may request us not to handle breakpoints */

  477. 	if (handle_breakpoints) {

  478. 		/* Single step past breakpoint at current address */

  479. 		breakpoint = breakpoint_find(target, resume_pc);

  480. 		if (breakpoint) {

  481. 			LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",

  482. 					  breakpoint->address);

  483. 			mips_m4k_unset_breakpoint(target, breakpoint);

  484. 			mips_m4k_single_step_core(target);

  485. 			mips_m4k_set_breakpoint(target, breakpoint);

  486. 		}

  487. 	}

  488. 

  489. 	/* enable interrupts if we are running */

  490. 	mips32_enable_interrupts(target, !debug_execution);

  491. 

  492. 	/* exit debug mode */

  493. 	mips_ejtag_exit_debug(ejtag_info);

  494. 	target->debug_reason = DBG_REASON_NOTHALTED;

  495. 

  496. 	/* registers are now invalid */

  497. 	register_cache_invalidate(mips32->core_cache);

  498. 

  499. 	if (!debug_execution) {

  500. 		target->state = TARGET_RUNNING;

  501. 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);

  502. 		LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);

  503. 	} else {

  504. 		target->state = TARGET_DEBUG_RUNNING;

  505. 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);

  506. 		LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);

  507. 	}

  508. 

  509. 	return ERROR_OK;

  510. }

  511. 

  512. static int mips_m4k_resume(struct target *target, int current,

  513. 		target_addr_t address, int handle_breakpoints, int debug_execution)

  514. {

  515. 	int retval = ERROR_OK;

  516. 

  517. 	/* dummy resume for smp toggle in order to reduce gdb impact  */

  518. 	if ((target->smp) && (target->gdb_service->core[1] != -1)) {

  519. 		/*   simulate a start and halt of target */

  520. 		target->gdb_service->target = NULL;

  521. 		target->gdb_service->core[0] = target->gdb_service->core[1];

  522. 		/*  fake resume at next poll we play the  target core[1], see poll*/

  523. 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);

  524. 		return retval;

  525. 	}

  526. 

  527. 	retval = mips_m4k_internal_restore(target, current, address,

  528. 				handle_breakpoints,

  529. 				debug_execution);

  530. 

  531. 	if (retval == ERROR_OK && target->smp) {

  532. 		target->gdb_service->core[0] = -1;

  533. 		retval = mips_m4k_restore_smp(target, address, handle_breakpoints);

  534. 	}

  535. 

  536. 	return retval;

  537. }

  538. 

  539. static int mips_m4k_step(struct target *target, int current,

  540. 		target_addr_t address, int handle_breakpoints)

  541. {

  542. 	/* get pointers to arch-specific information */

  543. 	struct mips32_common *mips32 = target_to_mips32(target);

  544. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  545. 	struct breakpoint *breakpoint = NULL;

  546. 

  547. 	if (target->state != TARGET_HALTED) {

  548. 		LOG_WARNING("target not halted");

  549. 		return ERROR_TARGET_NOT_HALTED;

  550. 	}

  551. 

  552. 	/* current = 1: continue on current pc, otherwise continue at <address> */

  553. 	if (!current) {

  554. 		mips_m4k_isa_filter(mips32->isa_imp, &address);

  555. 		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);

  556. 		mips32->core_cache->reg_list[MIPS32_PC].dirty = true;

  557. 		mips32->core_cache->reg_list[MIPS32_PC].valid = true;

  558. 	}

  559. 

  560. 	/* the front-end may request us not to handle breakpoints */

  561. 	if (handle_breakpoints) {

  562. 		breakpoint = breakpoint_find(target,

  563. 				buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));

  564. 		if (breakpoint)

  565. 			mips_m4k_unset_breakpoint(target, breakpoint);

  566. 	}

  567. 

  568. 	/* restore context */

  569. 	mips32_restore_context(target);

  570. 

  571. 	/* configure single step mode */

  572. 	mips_ejtag_config_step(ejtag_info, 1);

  573. 

  574. 	target->debug_reason = DBG_REASON_SINGLESTEP;

  575. 

  576. 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);

  577. 

  578. 	/* disable interrupts while stepping */

  579. 	mips32_enable_interrupts(target, 0);

  580. 

  581. 	/* exit debug mode */

  582. 	mips_ejtag_exit_debug(ejtag_info);

  583. 

  584. 	/* registers are now invalid */

  585. 	register_cache_invalidate(mips32->core_cache);

  586. 

  587. 	LOG_DEBUG("target stepped ");

  588. 	mips_m4k_debug_entry(target);

  589. 

  590. 	if (breakpoint)

  591. 		mips_m4k_set_breakpoint(target, breakpoint);

  592. 

  593. 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);

  594. 

  595. 	return ERROR_OK;

  596. }

  597. 

  598. static void mips_m4k_enable_breakpoints(struct target *target)

  599. {

  600. 	struct breakpoint *breakpoint = target->breakpoints;

  601. 

  602. 	/* set any pending breakpoints */

  603. 	while (breakpoint) {

  604. 		if (breakpoint->set == 0)

  605. 			mips_m4k_set_breakpoint(target, breakpoint);

  606. 		breakpoint = breakpoint->next;

  607. 	}

  608. }

  609. 

  610. static int mips_m4k_set_breakpoint(struct target *target,

  611. 		struct breakpoint *breakpoint)

  612. {

  613. 	struct mips32_common *mips32 = target_to_mips32(target);

  614. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  615. 	struct mips32_comparator *comparator_list = mips32->inst_break_list;

  616. 	int retval;

  617. 

  618. 	if (breakpoint->set) {

  619. 		LOG_WARNING("breakpoint already set");

  620. 		return ERROR_OK;

  621. 	}

  622. 

  623. 	if (breakpoint->type == BKPT_HARD) {

  624. 		int bp_num = 0;

  625. 

  626. 		while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))

  627. 			bp_num++;

  628. 		if (bp_num >= mips32->num_inst_bpoints) {

  629. 			LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",

  630. 					breakpoint->unique_id);

  631. 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  632. 		}

  633. 		breakpoint->set = bp_num + 1;

  634. 		comparator_list[bp_num].used = 1;

  635. 		comparator_list[bp_num].bp_value = breakpoint->address;

  636. 

  637. 		if (breakpoint->length != 4)			/* make sure isa bit set */

  638. 			comparator_list[bp_num].bp_value |= 1;

  639. 		else						/* make sure isa bit cleared */

  640. 			comparator_list[bp_num].bp_value &= ~1;

  641. 

  642. 		/* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.

  643. 		 * Warning: there is no IB ASID registers in 2.0.

  644. 		 * Do not set it! :) */

  645. 		if (ejtag_info->ejtag_version == EJTAG_VERSION_20)

  646. 			comparator_list[bp_num].bp_value &= 0xFFFFFFFC;

  647. 

  648. 		target_write_u32(target, comparator_list[bp_num].reg_address,

  649. 				comparator_list[bp_num].bp_value);

  650. 		target_write_u32(target, comparator_list[bp_num].reg_address +

  651. 				 ejtag_info->ejtag_ibm_offs, 0x00000000);

  652. 		target_write_u32(target, comparator_list[bp_num].reg_address +

  653. 				 ejtag_info->ejtag_ibc_offs, 1);

  654. 		LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",

  655. 				  breakpoint->unique_id,

  656. 				  bp_num, comparator_list[bp_num].bp_value);

  657. 	} else if (breakpoint->type == BKPT_SOFT) {

  658. 		LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);

  659. 

  660. 		uint32_t isa_req = breakpoint->length & 1;	/* micro mips request bit */

  661. 		uint32_t bplength = breakpoint->length & ~1;	/* drop micro mips request bit for length */

  662. 		uint32_t bpaddr = breakpoint->address & ~1;	/* drop isa bit from address, if set */

  663. 

  664. 		if (bplength == 4) {

  665. 			uint32_t verify = 0xffffffff;

  666. 			uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);

  667. 			if (ejtag_info->endianness && isa_req)

  668. 				sdbbp32_instr = SWAP16(sdbbp32_instr);

  669. 

  670. 			if ((breakpoint->address & 3) == 0) {	/* word aligned */

  671. 

  672. 				retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);

  673. 				if (retval != ERROR_OK)

  674. 					return retval;

  675. 

  676. 				retval = target_write_u32(target, bpaddr, sdbbp32_instr);

  677. 				if (retval != ERROR_OK)

  678. 					return retval;

  679. 

  680. 				retval = target_read_u32(target, bpaddr, &verify);

  681. 				if (retval != ERROR_OK)

  682. 					return retval;

  683. 

  684. 				if (verify != sdbbp32_instr)

  685. 					verify = 0;

  686. 

  687. 			} else {	/* 16 bit aligned */

  688. 				retval = target_read_memory(target, bpaddr, 2, 2, breakpoint->orig_instr);

  689. 				if (retval != ERROR_OK)

  690. 					return retval;

  691. 

  692. 				uint8_t sdbbp_buf[4];

  693. 				target_buffer_set_u32(target, sdbbp_buf, sdbbp32_instr);

  694. 

  695. 				retval = target_write_memory(target, bpaddr, 2, 2, sdbbp_buf);

  696. 				if (retval != ERROR_OK)

  697. 					return retval;

  698. 

  699. 				retval = target_read_memory(target, bpaddr, 2, 2, sdbbp_buf);

  700. 				if (retval != ERROR_OK)

  701. 					return retval;

  702. 

  703. 				if (target_buffer_get_u32(target, sdbbp_buf) != sdbbp32_instr)

  704. 					verify = 0;

  705. 			}

  706. 

  707. 			if (verify == 0) {

  708. 				LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR

  709. 					" - check that memory is read/writable", breakpoint->address);

  710. 				return ERROR_OK;

  711. 			}

  712. 

  713. 		} else {

  714. 			uint16_t verify = 0xffff;

  715. 

  716. 			retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);

  717. 			if (retval != ERROR_OK)

  718. 				return retval;

  719. 

  720. 			retval = target_write_u16(target, bpaddr, MIPS16_SDBBP(isa_req));

  721. 			if (retval != ERROR_OK)

  722. 				return retval;

  723. 

  724. 			retval = target_read_u16(target, bpaddr, &verify);

  725. 			if (retval != ERROR_OK)

  726. 				return retval;

  727. 

  728. 			if (verify != MIPS16_SDBBP(isa_req)) {

  729. 				LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR

  730. 						" - check that memory is read/writable", breakpoint->address);

  731. 				return ERROR_OK;

  732. 			}

  733. 		}

  734. 

  735. 		breakpoint->set = 20; /* Any nice value but 0 */

  736. 	}

  737. 

  738. 	return ERROR_OK;

  739. }

  740. 

  741. static int mips_m4k_unset_breakpoint(struct target *target,

  742. 		struct breakpoint *breakpoint)

  743. {

  744. 	/* get pointers to arch-specific information */

  745. 	struct mips32_common *mips32 = target_to_mips32(target);

  746. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  747. 	struct mips32_comparator *comparator_list = mips32->inst_break_list;

  748. 	int retval;

  749. 

  750. 	if (!breakpoint->set) {

  751. 		LOG_WARNING("breakpoint not set");

  752. 		return ERROR_OK;

  753. 	}

  754. 

  755. 	if (breakpoint->type == BKPT_HARD) {

  756. 		int bp_num = breakpoint->set - 1;

  757. 		if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {

  758. 			LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",

  759. 					  breakpoint->unique_id);

  760. 			return ERROR_OK;

  761. 		}

  762. 		LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",

  763. 				breakpoint->unique_id,

  764. 				bp_num);

  765. 		comparator_list[bp_num].used = 0;

  766. 		comparator_list[bp_num].bp_value = 0;

  767. 		target_write_u32(target, comparator_list[bp_num].reg_address +

  768. 				 ejtag_info->ejtag_ibc_offs, 0);

  769. 

  770. 	} else {

  771. 		/* restore original instruction (kept in target endianness) */

  772. 		uint32_t isa_req = breakpoint->length & 1;

  773. 		uint32_t bplength = breakpoint->length & ~1;

  774. 		uint8_t current_instr[4];

  775. 		LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);

  776. 		if (bplength == 4) {

  777. 			uint32_t sdbbp32_instr =  MIPS32_SDBBP(isa_req);

  778. 			if (ejtag_info->endianness && isa_req)

  779. 				sdbbp32_instr = SWAP16(sdbbp32_instr);

  780. 

  781. 			if ((breakpoint->address & 3) == 0) {		/* 32bit aligned */

  782. 				/* check that user program has not modified breakpoint instruction */

  783. 				retval = target_read_memory(target, breakpoint->address, 4, 1, current_instr);

  784. 				if (retval != ERROR_OK)

  785. 					return retval;

  786. 				/**

  787. 				* target_read_memory() gets us data in _target_ endianness.

  788. 				* If we want to use this data on the host for comparisons with some macros

  789. 				* we must first transform it to _host_ endianness using target_buffer_get_u16().

  790. 				*/

  791. 				if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {

  792. 					retval = target_write_memory(target, breakpoint->address, 4, 1,

  793. 										breakpoint->orig_instr);

  794. 					if (retval != ERROR_OK)

  795. 						return retval;

  796. 				}

  797. 			} else {	/* 16bit aligned */

  798. 				retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);

  799. 				if (retval != ERROR_OK)

  800. 					return retval;

  801. 

  802. 				if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {

  803. 					retval = target_write_memory(target, breakpoint->address, 2, 2,

  804. 										breakpoint->orig_instr);

  805. 					if (retval != ERROR_OK)

  806. 						return retval;

  807. 				}

  808. 			}

  809. 		} else {

  810. 			/* check that user program has not modified breakpoint instruction */

  811. 			retval = target_read_memory(target, breakpoint->address, 2, 1, current_instr);

  812. 			if (retval != ERROR_OK)

  813. 				return retval;

  814. 

  815. 			if (target_buffer_get_u16(target, current_instr) == MIPS16_SDBBP(isa_req)) {

  816. 				retval = target_write_memory(target, breakpoint->address, 2, 1,

  817. 									breakpoint->orig_instr);

  818. 				if (retval != ERROR_OK)

  819. 					return retval;

  820. 			}

  821. 		}

  822. 	}

  823. 

  824. 	breakpoint->set = 0;

  825. 

  826. 	return ERROR_OK;

  827. }

  828. 

  829. static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)

  830. {

  831. 	struct mips32_common *mips32 = target_to_mips32(target);

  832. 

  833. 	if ((breakpoint->length > 5 || breakpoint->length < 2) ||		/* out of range */

  834. 		(breakpoint->length == 4 && (breakpoint->address & 2)) ||	/* mips32 unaligned */

  835. 		(mips32->isa_imp == MIPS32_ONLY && breakpoint->length != 4) ||	/* misp32 specific */

  836. 		((mips32->isa_imp & 1) != (breakpoint->length & 1)))		/* isa not implemented */

  837. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  838. 

  839. 	if (breakpoint->type == BKPT_HARD) {

  840. 		if (mips32->num_inst_bpoints_avail < 1) {

  841. 			LOG_INFO("no hardware breakpoint available");

  842. 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  843. 		}

  844. 

  845. 		mips32->num_inst_bpoints_avail--;

  846. 	}

  847. 

  848. 	return mips_m4k_set_breakpoint(target, breakpoint);

  849. }

  850. 

  851. static int mips_m4k_remove_breakpoint(struct target *target,

  852. 		struct breakpoint *breakpoint)

  853. {

  854. 	/* get pointers to arch-specific information */

  855. 	struct mips32_common *mips32 = target_to_mips32(target);

  856. 

  857. 	if (target->state != TARGET_HALTED) {

  858. 		LOG_WARNING("target not halted");

  859. 		return ERROR_TARGET_NOT_HALTED;

  860. 	}

  861. 

  862. 	if (breakpoint->set)

  863. 		mips_m4k_unset_breakpoint(target, breakpoint);

  864. 

  865. 	if (breakpoint->type == BKPT_HARD)

  866. 		mips32->num_inst_bpoints_avail++;

  867. 

  868. 	return ERROR_OK;

  869. }

  870. 

  871. static int mips_m4k_set_watchpoint(struct target *target,

  872. 		struct watchpoint *watchpoint)

  873. {

  874. 	struct mips32_common *mips32 = target_to_mips32(target);

  875. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  876. 	struct mips32_comparator *comparator_list = mips32->data_break_list;

  877. 	int wp_num = 0;

  878. 	/*

  879. 	 * watchpoint enabled, ignore all byte lanes in value register

  880. 	 * and exclude both load and store accesses from  watchpoint

  881. 	 * condition evaluation

  882. 	*/

  883. 	int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |

  884. 			(0xff << EJTAG_DBCN_BLM_SHIFT);

  885. 

  886. 	if (watchpoint->set) {

  887. 		LOG_WARNING("watchpoint already set");

  888. 		return ERROR_OK;

  889. 	}

  890. 

  891. 	while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))

  892. 		wp_num++;

  893. 	if (wp_num >= mips32->num_data_bpoints) {

  894. 		LOG_ERROR("Can not find free FP Comparator");

  895. 		return ERROR_FAIL;

  896. 	}

  897. 

  898. 	if (watchpoint->length != 4) {

  899. 		LOG_ERROR("Only watchpoints of length 4 are supported");

  900. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  901. 	}

  902. 

  903. 	if (watchpoint->address % 4) {

  904. 		LOG_ERROR("Watchpoints address should be word aligned");

  905. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  906. 	}

  907. 

  908. 	switch (watchpoint->rw) {

  909. 		case WPT_READ:

  910. 			enable &= ~EJTAG_DBCN_NOLB;

  911. 			break;

  912. 		case WPT_WRITE:

  913. 			enable &= ~EJTAG_DBCN_NOSB;

  914. 			break;

  915. 		case WPT_ACCESS:

  916. 			enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);

  917. 			break;

  918. 		default:

  919. 			LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");

  920. 	}

  921. 

  922. 	watchpoint->set = wp_num + 1;

  923. 	comparator_list[wp_num].used = 1;

  924. 	comparator_list[wp_num].bp_value = watchpoint->address;

  925. 

  926. 	/* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.

  927. 	 * There is as well no ASID register support. */

  928. 	if (ejtag_info->ejtag_version == EJTAG_VERSION_20)

  929. 		comparator_list[wp_num].bp_value &= 0xFFFFFFF8;

  930. 	else

  931. 		target_write_u32(target, comparator_list[wp_num].reg_address +

  932. 			 ejtag_info->ejtag_dbasid_offs, 0x00000000);

  933. 

  934. 	target_write_u32(target, comparator_list[wp_num].reg_address,

  935. 			 comparator_list[wp_num].bp_value);

  936. 	target_write_u32(target, comparator_list[wp_num].reg_address +

  937. 			 ejtag_info->ejtag_dbm_offs, 0x00000000);

  938. 

  939. 	target_write_u32(target, comparator_list[wp_num].reg_address +

  940. 			 ejtag_info->ejtag_dbc_offs, enable);

  941. 	/* TODO: probably this value is ignored on 2.0 */

  942. 	target_write_u32(target, comparator_list[wp_num].reg_address +

  943. 			 ejtag_info->ejtag_dbv_offs, 0);

  944. 	LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);

  945. 

  946. 	return ERROR_OK;

  947. }

  948. 

  949. static int mips_m4k_unset_watchpoint(struct target *target,

  950. 		struct watchpoint *watchpoint)

  951. {

  952. 	/* get pointers to arch-specific information */

  953. 	struct mips32_common *mips32 = target_to_mips32(target);

  954. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  955. 	struct mips32_comparator *comparator_list = mips32->data_break_list;

  956. 

  957. 	if (!watchpoint->set) {

  958. 		LOG_WARNING("watchpoint not set");

  959. 		return ERROR_OK;

  960. 	}

  961. 

  962. 	int wp_num = watchpoint->set - 1;

  963. 	if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {

  964. 		LOG_DEBUG("Invalid FP Comparator number in watchpoint");

  965. 		return ERROR_OK;

  966. 	}

  967. 	comparator_list[wp_num].used = 0;

  968. 	comparator_list[wp_num].bp_value = 0;

  969. 	target_write_u32(target, comparator_list[wp_num].reg_address +

  970. 			 ejtag_info->ejtag_dbc_offs, 0);

  971. 	watchpoint->set = 0;

  972. 

  973. 	return ERROR_OK;

  974. }

  975. 

  976. static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)

  977. {

  978. 	struct mips32_common *mips32 = target_to_mips32(target);

  979. 

  980. 	if (mips32->num_data_bpoints_avail < 1) {

  981. 		LOG_INFO("no hardware watchpoints available");

  982. 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;

  983. 	}

  984. 

  985. 	mips32->num_data_bpoints_avail--;

  986. 

  987. 	mips_m4k_set_watchpoint(target, watchpoint);

  988. 	return ERROR_OK;

  989. }

  990. 

  991. static int mips_m4k_remove_watchpoint(struct target *target,

  992. 		struct watchpoint *watchpoint)

  993. {

  994. 	/* get pointers to arch-specific information */

  995. 	struct mips32_common *mips32 = target_to_mips32(target);

  996. 

  997. 	if (target->state != TARGET_HALTED) {

  998. 		LOG_WARNING("target not halted");

  999. 		return ERROR_TARGET_NOT_HALTED;

  1000. 	}

  1001. 

  1002. 	if (watchpoint->set)

  1003. 		mips_m4k_unset_watchpoint(target, watchpoint);

  1004. 

  1005. 	mips32->num_data_bpoints_avail++;

  1006. 

  1007. 	return ERROR_OK;

  1008. }

  1009. 

  1010. static void mips_m4k_enable_watchpoints(struct target *target)

  1011. {

  1012. 	struct watchpoint *watchpoint = target->watchpoints;

  1013. 

  1014. 	/* set any pending watchpoints */

  1015. 	while (watchpoint) {

  1016. 		if (watchpoint->set == 0)

  1017. 			mips_m4k_set_watchpoint(target, watchpoint);

  1018. 		watchpoint = watchpoint->next;

  1019. 	}

  1020. }

  1021. 

  1022. static int mips_m4k_read_memory(struct target *target, target_addr_t address,

  1023. 		uint32_t size, uint32_t count, uint8_t *buffer)

  1024. {

  1025. 	struct mips32_common *mips32 = target_to_mips32(target);

  1026. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  1027. 

  1028. 	LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",

  1029. 			address, size, count);

  1030. 

  1031. 	if (target->state != TARGET_HALTED) {

  1032. 		LOG_WARNING("target not halted");

  1033. 		return ERROR_TARGET_NOT_HALTED;

  1034. 	}

  1035. 

  1036. 	/* sanitize arguments */

  1037. 	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))

  1038. 		return ERROR_COMMAND_SYNTAX_ERROR;

  1039. 

  1040. 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))

  1041. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  1042. 

  1043. 	/* since we don't know if buffer is aligned, we allocate new mem that is always aligned */

  1044. 	void *t = NULL;

  1045. 

  1046. 	if (size > 1) {

  1047. 		t = malloc(count * size * sizeof(uint8_t));

  1048. 		if (!t) {

  1049. 			LOG_ERROR("Out of memory");

  1050. 			return ERROR_FAIL;

  1051. 		}

  1052. 	} else

  1053. 		t = buffer;

  1054. 

  1055. 	/* if noDMA off, use DMAACC mode for memory read */

  1056. 	int retval;

  1057. 	if (ejtag_info->impcode & EJTAG_IMP_NODMA)

  1058. 		retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);

  1059. 	else

  1060. 		retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);

  1061. 

  1062. 	/* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */

  1063. 	/* endianness, but byte array should represent target endianness       */

  1064. 	if (retval == ERROR_OK) {

  1065. 		switch (size) {

  1066. 		case 4:

  1067. 			target_buffer_set_u32_array(target, buffer, count, t);

  1068. 			break;

  1069. 		case 2:

  1070. 			target_buffer_set_u16_array(target, buffer, count, t);

  1071. 			break;

  1072. 		}

  1073. 	}

  1074. 

  1075. 	if (size > 1)

  1076. 		free(t);

  1077. 

  1078. 	return retval;

  1079. }

  1080. 

  1081. static int mips_m4k_write_memory(struct target *target, target_addr_t address,

  1082. 		uint32_t size, uint32_t count, const uint8_t *buffer)

  1083. {

  1084. 	struct mips32_common *mips32 = target_to_mips32(target);

  1085. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  1086. 

  1087. 	LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",

  1088. 			address, size, count);

  1089. 

  1090. 	if (target->state != TARGET_HALTED) {

  1091. 		LOG_WARNING("target not halted");

  1092. 		return ERROR_TARGET_NOT_HALTED;

  1093. 	}

  1094. 

  1095. 	if (size == 4 && count > 32) {

  1096. 		int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);

  1097. 		if (retval == ERROR_OK)

  1098. 			return ERROR_OK;

  1099. 		LOG_WARNING("Falling back to non-bulk write");

  1100. 	}

  1101. 

  1102. 	/* sanitize arguments */

  1103. 	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))

  1104. 		return ERROR_COMMAND_SYNTAX_ERROR;

  1105. 

  1106. 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))

  1107. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  1108. 

  1109. 	/** correct endianness if we have word or hword access */

  1110. 	void *t = NULL;

  1111. 	if (size > 1) {

  1112. 		/* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */

  1113. 		/* endianness, but byte array represents target endianness               */

  1114. 		t = malloc(count * size * sizeof(uint8_t));

  1115. 		if (!t) {

  1116. 			LOG_ERROR("Out of memory");

  1117. 			return ERROR_FAIL;

  1118. 		}

  1119. 

  1120. 		switch (size) {

  1121. 		case 4:

  1122. 			target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);

  1123. 			break;

  1124. 		case 2:

  1125. 			target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);

  1126. 			break;

  1127. 		}

  1128. 		buffer = t;

  1129. 	}

  1130. 

  1131. 	/* if noDMA off, use DMAACC mode for memory write */

  1132. 	int retval;

  1133. 	if (ejtag_info->impcode & EJTAG_IMP_NODMA)

  1134. 		retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);

  1135. 	else

  1136. 		retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);

  1137. 

  1138. 	free(t);

  1139. 

  1140. 	if (retval != ERROR_OK)

  1141. 		return retval;

  1142. 

  1143. 	return ERROR_OK;

  1144. }

  1145. 

  1146. static int mips_m4k_init_target(struct command_context *cmd_ctx,

  1147. 		struct target *target)

  1148. {

  1149. 	mips32_build_reg_cache(target);

  1150. 

  1151. 	return ERROR_OK;

  1152. }

  1153. 

  1154. static int mips_m4k_init_arch_info(struct target *target,

  1155. 		struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)

  1156. {

  1157. 	struct mips32_common *mips32 = &mips_m4k->mips32;

  1158. 

  1159. 	mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;

  1160. 

  1161. 	/* initialize mips4k specific info */

  1162. 	mips32_init_arch_info(target, mips32, tap);

  1163. 	mips32->arch_info = mips_m4k;

  1164. 

  1165. 	return ERROR_OK;

  1166. }

  1167. 

  1168. static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)

  1169. {

  1170. 	struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));

  1171. 

  1172. 	mips_m4k_init_arch_info(target, mips_m4k, target->tap);

  1173. 

  1174. 	return ERROR_OK;

  1175. }

  1176. 

  1177. static int mips_m4k_examine(struct target *target)

  1178. {

  1179. 	struct mips_m4k_common *mips_m4k = target_to_m4k(target);

  1180. 	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;

  1181. 

  1182. 	if (!target_was_examined(target)) {

  1183. 		int retval = mips_ejtag_get_idcode(ejtag_info);

  1184. 		if (retval != ERROR_OK) {

  1185. 			LOG_ERROR("idcode read failed");

  1186. 			return retval;

  1187. 		}

  1188. 		if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {

  1189. 			/* we are using a pic32mx so select ejtag port

  1190. 			 * as it is not selected by default */

  1191. 			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);

  1192. 			LOG_DEBUG("PIC32 Detected - using EJTAG Interface");

  1193. 			mips_m4k->is_pic32mx = true;

  1194. 		}

  1195. 	}

  1196. 

  1197. 	/* init rest of ejtag interface */

  1198. 	int retval = mips_ejtag_init(ejtag_info);

  1199. 	if (retval != ERROR_OK)

  1200. 		return retval;

  1201. 

  1202. 	return mips32_examine(target);

  1203. }

  1204. 

  1205. static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,

  1206. 		uint32_t count, const uint8_t *buffer)

  1207. {

  1208. 	struct mips32_common *mips32 = target_to_mips32(target);

  1209. 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;

  1210. 	struct working_area *fast_data_area;

  1211. 	int retval;

  1212. 	int write_t = 1;

  1213. 

  1214. 	LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",

  1215. 			  address, count);

  1216. 

  1217. 	/* check alignment */

  1218. 	if (address & 0x3u)

  1219. 		return ERROR_TARGET_UNALIGNED_ACCESS;

  1220. 

  1221. 	if (!mips32->fast_data_area) {

  1222. 		/* Get memory for block write handler

  1223. 		 * we preserve this area between calls and gain a speed increase

  1224. 		 * of about 3kb/sec when writing flash

  1225. 		 * this will be released/nulled by the system when the target is resumed or reset */

  1226. 		retval = target_alloc_working_area(target,

  1227. 				MIPS32_FASTDATA_HANDLER_SIZE,

  1228. 				&mips32->fast_data_area);

  1229. 		if (retval != ERROR_OK) {

  1230. 			LOG_ERROR("No working area available");

  1231. 			return retval;

  1232. 		}

  1233. 

  1234. 		/* reset fastadata state so the algo get reloaded */

  1235. 		ejtag_info->fast_access_save = -1;

  1236. 	}

  1237. 

  1238. 	fast_data_area = mips32->fast_data_area;

  1239. 

  1240. 	if (address <= fast_data_area->address + fast_data_area->size &&

  1241. 			fast_data_area->address <= address + count) {

  1242. 		LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "

  1243. 			  "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",

  1244. 			  fast_data_area->address, address, address + count);

  1245. 		LOG_ERROR("Change work-area-phys or load_image address!");

  1246. 		return ERROR_FAIL;

  1247. 	}

  1248. 

  1249. 	/* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */

  1250. 	/* but byte array represents target endianness                      */

  1251. 	uint32_t *t = NULL;

  1252. 	t = malloc(count * sizeof(uint32_t));

  1253. 	if (!t) {

  1254. 		LOG_ERROR("Out of memory");

  1255. 		return ERROR_FAIL;

  1256. 	}

  1257. 

  1258. 	target_buffer_get_u32_array(target, buffer, count, t);

  1259. 

  1260. 	retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,

  1261. 			count, t);

  1262. 

  1263. 	free(t);

  1264. 

  1265. 	if (retval != ERROR_OK)

  1266. 		LOG_ERROR("Fastdata access Failed");

  1267. 

  1268. 	return retval;

  1269. }

  1270. 

  1271. static int mips_m4k_verify_pointer(struct command_invocation *cmd,

  1272. 		struct mips_m4k_common *mips_m4k)

  1273. {

  1274. 	if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {

  1275. 		command_print(cmd, "target is not an MIPS_M4K");

  1276. 		return ERROR_TARGET_INVALID;

  1277. 	}

  1278. 	return ERROR_OK;

  1279. }

  1280. 

  1281. COMMAND_HANDLER(mips_m4k_handle_cp0_command)

  1282. {

  1283. 	int retval;

  1284. 	struct target *target = get_current_target(CMD_CTX);

  1285. 	struct mips_m4k_common *mips_m4k = target_to_m4k(target);

  1286. 	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;

  1287. 

  1288. 	retval = mips_m4k_verify_pointer(CMD, mips_m4k);

  1289. 	if (retval != ERROR_OK)

  1290. 		return retval;

  1291. 

  1292. 	if (target->state != TARGET_HALTED) {

  1293. 		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);

  1294. 		return ERROR_OK;

  1295. 	}

  1296. 

  1297. 	/* two or more argument, access a single register/select (write if third argument is given) */

  1298. 	if (CMD_ARGC < 2)

  1299. 		return ERROR_COMMAND_SYNTAX_ERROR;

  1300. 	else {

  1301. 		uint32_t cp0_reg, cp0_sel;

  1302. 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);

  1303. 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);

  1304. 

  1305. 		if (CMD_ARGC == 2) {

  1306. 			uint32_t value;

  1307. 			retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);

  1308. 			if (retval != ERROR_OK) {

  1309. 				command_print(CMD,

  1310. 						"couldn't access reg %" PRIu32,

  1311. 						cp0_reg);

  1312. 				return ERROR_OK;

  1313. 			}

  1314. 			command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,

  1315. 					cp0_reg, cp0_sel, value);

  1316. 

  1317. 		} else if (CMD_ARGC == 3) {

  1318. 			uint32_t value;

  1319. 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);

  1320. 			retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);

  1321. 			if (retval != ERROR_OK) {

  1322. 				command_print(CMD,

  1323. 						"couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,

  1324. 						cp0_reg,  cp0_sel);

  1325. 				return ERROR_OK;

  1326. 			}

  1327. 			command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,

  1328. 					cp0_reg, cp0_sel, value);

  1329. 		}

  1330. 	}

  1331. 

  1332. 	return ERROR_OK;

  1333. }

  1334. 

  1335. COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)

  1336. {

  1337. 	struct target *target = get_current_target(CMD_CTX);

  1338. 	struct mips_m4k_common *mips_m4k = target_to_m4k(target);

  1339. 	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;

  1340. 

  1341. 	if (CMD_ARGC == 1)

  1342. 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);

  1343. 	else if (CMD_ARGC > 1)

  1344. 			return ERROR_COMMAND_SYNTAX_ERROR;

  1345. 

  1346. 	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);

  1347. 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {

  1348. 		ejtag_info->mode = 0;

  1349. 		command_print(CMD, "running in legacy mode");

  1350. 	} else {

  1351. 		ejtag_info->mode = 1;

  1352. 		command_print(CMD, "running in fast queued mode");

  1353. 	}

  1354. 

  1355. 	return ERROR_OK;

  1356. }

  1357. 

  1358. static const struct command_registration mips_m4k_exec_command_handlers[] = {

  1359. 	{

  1360. 		.name = "cp0",

  1361. 		.handler = mips_m4k_handle_cp0_command,

  1362. 		.mode = COMMAND_EXEC,

  1363. 		.usage = "regnum [value]",

  1364. 		.help = "display/modify cp0 register",

  1365. 	},

  1366. 	{

  1367. 		.name = "scan_delay",

  1368. 		.handler = mips_m4k_handle_scan_delay_command,

  1369. 		.mode = COMMAND_ANY,

  1370. 		.help = "display/set scan delay in nano seconds",

  1371. 		.usage = "[value]",

  1372. 	},

  1373. 	{

  1374. 		.chain = smp_command_handlers,

  1375. 	},

  1376. 	COMMAND_REGISTRATION_DONE

  1377. };

  1378. 

  1379. const struct command_registration mips_m4k_command_handlers[] = {

  1380. 	{

  1381. 		.chain = mips32_command_handlers,

  1382. 	},

  1383. 	{

  1384. 		.name = "mips_m4k",

  1385. 		.mode = COMMAND_ANY,

  1386. 		.help = "mips_m4k command group",

  1387. 		.usage = "",

  1388. 		.chain = mips_m4k_exec_command_handlers,

  1389. 	},

  1390. 	COMMAND_REGISTRATION_DONE

  1391. };

  1392. 

  1393. struct target_type mips_m4k_target = {

  1394. 	.name = "mips_m4k",

  1395. 

  1396. 	.poll = mips_m4k_poll,

  1397. 	.arch_state = mips32_arch_state,

  1398. 

  1399. 	.halt = mips_m4k_halt,

  1400. 	.resume = mips_m4k_resume,

  1401. 	.step = mips_m4k_step,

  1402. 

  1403. 	.assert_reset = mips_m4k_assert_reset,

  1404. 	.deassert_reset = mips_m4k_deassert_reset,

  1405. 

  1406. 	.get_gdb_reg_list = mips32_get_gdb_reg_list,

  1407. 

  1408. 	.read_memory = mips_m4k_read_memory,

  1409. 	.write_memory = mips_m4k_write_memory,

  1410. 	.checksum_memory = mips32_checksum_memory,

  1411. 	.blank_check_memory = mips32_blank_check_memory,

  1412. 

  1413. 	.run_algorithm = mips32_run_algorithm,

  1414. 

  1415. 	.add_breakpoint = mips_m4k_add_breakpoint,

  1416. 	.remove_breakpoint = mips_m4k_remove_breakpoint,

  1417. 	.add_watchpoint = mips_m4k_add_watchpoint,

  1418. 	.remove_watchpoint = mips_m4k_remove_watchpoint,

  1419. 

  1420. 	.commands = mips_m4k_command_handlers,

  1421. 	.target_create = mips_m4k_target_create,

  1422. 	.init_target = mips_m4k_init_target,

  1423. 	.examine = mips_m4k_examine,

  1424. };