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openocd/src/target/armv4_5.h

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  1. /***************************************************************************

  2.  *   Copyright (C) 2005 by Dominic Rath                                    *

  3.  *   Dominic.Rath@gmx.de                                                   *

  4.  *                                                                         *

  5.  *   This program is free software; you can redistribute it and/or modify  *

  6.  *   it under the terms of the GNU General Public License as published by  *

  7.  *   the Free Software Foundation; either version 2 of the License, or     *

  8.  *   (at your option) any later version.                                   *

  9.  *                                                                         *

  10.  *   This program is distributed in the hope that it will be useful,       *

  11.  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

  12.  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *

  13.  *   GNU General Public License for more details.                          *

  14.  *                                                                         *

  15.  *   You should have received a copy of the GNU General Public License     *

  16.  *   along with this program; if not, write to the                         *

  17.  *   Free Software Foundation, Inc.,                                       *

  18.  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *

  19.  ***************************************************************************/

  20. #ifndef ARMV4_5_H

  21. #define ARMV4_5_H

  22. 

  23. #include "register.h"

  24. #include "target.h"

  25. 

  26. enum armv4_5_mode

  27. {

  28. 	ARMV4_5_MODE_USR = 16, 

  29. 	ARMV4_5_MODE_FIQ = 17, 

  30. 	ARMV4_5_MODE_IRQ = 18, 

  31. 	ARMV4_5_MODE_SVC = 19, 

  32. 	ARMV4_5_MODE_ABT = 23,

  33. 	ARMV4_5_MODE_UND = 27,

  34. 	ARMV4_5_MODE_SYS = 31,

  35. 	ARMV4_5_MODE_ANY = -1

  36. };

  37. 

  38. extern char* armv4_5_mode_strings[];

  39. 

  40. enum armv4_5_state

  41. {

  42. 	ARMV4_5_STATE_ARM,

  43. 	ARMV4_5_STATE_THUMB,

  44. 	ARMV4_5_STATE_JAZELLE,

  45. };

  46. 

  47. extern char* armv4_5_state_strings[];

  48. 

  49. extern int armv4_5_core_reg_map[7][17];

  50. 

  51. #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \

  52. 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]

  53. #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \

  54. 		cache->reg_list[armv4_5_core_reg_map[mode][num]]

  55. 

  56. /* offsets into armv4_5 core register cache */

  57. enum 

  58. {

  59. 	ARMV4_5_CPSR = 31,

  60. 	ARMV4_5_SPSR_FIQ = 32,

  61. 	ARMV4_5_SPSR_IRQ = 33,

  62. 	ARMV4_5_SPSR_SVC = 34,

  63. 	ARMV4_5_SPSR_ABT = 35,

  64. 	ARMV4_5_SPSR_UND = 36

  65. };

  66. 

  67. #define ARMV4_5_COMMON_MAGIC 0x0A450A45

  68. 

  69. typedef struct armv4_5_common_s

  70. {

  71. 	int common_magic;

  72. 	reg_cache_t *core_cache;

  73. 	enum armv4_5_mode core_mode;

  74. 	enum armv4_5_state core_state;

  75. 	int (*full_context)(struct target_s *target);

  76. 	int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);

  77. 	int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);

  78. 	void *arch_info;

  79. } armv4_5_common_t;

  80. 

  81. typedef struct armv4_5_algorithm_s

  82. {

  83. 	int common_magic;

  84. 		

  85. 	enum armv4_5_mode core_mode;

  86. 	enum armv4_5_state core_state;

  87. } armv4_5_algorithm_t;

  88. 

  89. typedef struct armv4_5_core_reg_s

  90. {

  91. 	int num;

  92. 	enum armv4_5_mode mode;

  93. 	target_t *target;

  94. 	armv4_5_common_t *armv4_5_common;

  95. } armv4_5_core_reg_t;

  96. 

  97. extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);

  98. extern enum armv4_5_mode armv4_5_number_to_mode(int number);

  99. extern int armv4_5_mode_to_number(enum armv4_5_mode mode);

  100. 

  101. extern int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size);

  102. extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);

  103. extern int armv4_5_invalidate_core_regs(target_t *target);

  104. 

  105. extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);

  106. extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);

  107. 

  108. extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);

  109. 

  110. extern int armv4_5_invalidate_core_regs(target_t *target);

  111. 

  112. /* ARM mode instructions

  113.  */

  114.  

  115. /* Store multiple increment after

  116.  * Rn: base register

  117.  * List: for each bit in list: store register

  118.  * S: in priviledged mode: store user-mode registers

  119.  * W=1: update the base register. W=0: leave the base register untouched

  120.  */

  121. #define ARMV4_5_STMIA(Rn, List, S, W)	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))

  122. 

  123. /* Load multiple increment after

  124.  * Rn: base register

  125.  * List: for each bit in list: store register

  126.  * S: in priviledged mode: store user-mode registers

  127.  * W=1: update the base register. W=0: leave the base register untouched

  128.  */

  129. #define ARMV4_5_LDMIA(Rn, List, S, W)	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))

  130. 

  131. /* MOV r8, r8 */

  132. #define ARMV4_5_NOP					(0xe1a08008)

  133. 

  134. /* Move PSR to general purpose register

  135.  * R=1: SPSR R=0: CPSR

  136.  * Rn: target register

  137.  */

  138. #define ARMV4_5_MRS(Rn, R)			(0xe10f0000 | ((R) << 22) | ((Rn) << 12))

  139. 

  140. /* Store register

  141.  * Rd: register to store

  142.  * Rn: base register

  143.  */

  144. #define ARMV4_5_STR(Rd, Rn)			(0xe5800000 | ((Rd) << 12) | ((Rn) << 16))

  145. 

  146. /* Load register

  147.  * Rd: register to load

  148.  * Rn: base register

  149.  */

  150. #define ARMV4_5_LDR(Rd, Rn)			(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))

  151. 

  152. /* Move general purpose register to PSR

  153.  * R=1: SPSR R=0: CPSR

  154.  * Field: Field mask

  155.  * 1: control field 2: extension field 4: status field 8: flags field

  156.  * Rm: source register

  157.  */

  158. #define ARMV4_5_MSR_GP(Rm, Field, R)	(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))

  159. #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))

  160. 

  161. /* Load Register Halfword Immediate Post-Index

  162.  * Rd: register to load

  163.  * Rn: base register

  164.  */

  165. #define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))

  166. 

  167. /* Load Register Byte Immediate Post-Index

  168.  * Rd: register to load

  169.  * Rn: base register

  170.  */

  171. #define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))

  172. 

  173. /* Store register Halfword Immediate Post-Index

  174.  * Rd: register to store

  175.  * Rn: base register

  176.  */

  177. #define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))

  178. 

  179. /* Store register Byte Immediate Post-Index

  180.  * Rd: register to store

  181.  * Rn: base register

  182.  */

  183. #define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))

  184. 

  185. /* Branch (and Link)

  186.  * Im: Branch target (left-shifted by 2 bits, added to PC)

  187.  * L: 1: branch and link 0: branch only

  188.  */

  189. #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))

  190. 

  191. /* Branch and exchange (ARM state)

  192.  * Rm: register holding branch target address

  193.  */

  194. #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))

  195. 

  196. /* Move to ARM register from coprocessor

  197.  * CP: Coprocessor number

  198.  * op1: Coprocessor opcode

  199.  * Rd: destination register

  200.  * CRn: first coprocessor operand

  201.  * CRm: second coprocessor operand

  202.  * op2: Second coprocessor opcode

  203.  */

  204. #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 

  205. 

  206. /* Move to coprocessor from ARM register

  207.  * CP: Coprocessor number

  208.  * op1: Coprocessor opcode

  209.  * Rd: destination register

  210.  * CRn: first coprocessor operand

  211.  * CRm: second coprocessor operand

  212.  * op2: Second coprocessor opcode

  213.  */

  214. #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 

  215. 

  216. /* Breakpoint instruction (ARMv5)

  217.  * Im: 16-bit immediate

  218.  */

  219. #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))

  220. 

  221. 

  222. /* Thumb mode instructions

  223.  */

  224.  

  225. /* Store register (Thumb mode)

  226.  * Rd: source register

  227.  * Rn: base register

  228.  */

  229. #define ARMV4_5_T_STR(Rd, Rn)	((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))

  230. 

  231. /* Load register (Thumb state)

  232.  * Rd: destination register

  233.  * Rn: base register

  234.  */

  235. #define ARMV4_5_T_LDR(Rd, Rn)	((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))

  236. 

  237. /* Load multiple (Thumb state)

  238.  * Rn: base register

  239.  * List: for each bit in list: store register

  240.  */

  241. #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))

  242.  

  243. /* Load register with PC relative addressing

  244.  * Rd: register to load

  245.  */

  246. #define ARMV4_5_T_LDR_PCREL(Rd)	((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) 

  247.  

  248. /* Move hi register (Thumb mode)

  249.  * Rd: destination register

  250.  * Rm: source register

  251.  */

  252. #define ARMV4_5_T_MOV(Rd, Rm)	((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))

  253. 

  254. /* No operation (Thumb mode)

  255.  */

  256. #define ARMV4_5_T_NOP	(0x46c0 | (0x46c0 << 16))

  257. 

  258. /* Move immediate to register (Thumb state)

  259.  * Rd: destination register

  260.  * Im: 8-bit immediate value

  261.  */

  262. #define ARMV4_5_T_MOV_IM(Rd, Im)	((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))

  263. 

  264. /* Branch and Exchange

  265.  * Rm: register containing branch target

  266.  */

  267. #define ARMV4_5_T_BX(Rm)		((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))

  268. 

  269. /* Branch (Thumb state)

  270.  * Imm: Branch target

  271.  */

  272. #define ARMV4_5_T_B(Imm)	((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))

  273. 

  274. /* Breakpoint instruction (ARMv5) (Thumb state)

  275.  * Im: 8-bit immediate

  276.  */

  277. #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))

  278. 

  279. #endif /* ARMV4_5_H */