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72 lines
1.4 KiB

  1. # The Cogent CSB732 board has a single i.MX35 chip
  2. source [find target/imx35.cfg]
  3. # Determined by trial and error
  4. reset_config trst_and_srst combined
  5. jtag_nsrst_delay 200
  6. jtag_ntrst_delay 200
  7. $_TARGETNAME configure -event gdb-attach { reset init }
  8. $_TARGETNAME configure -event reset-init { csb732_init }
  9. # Bare-bones initialization of core clocks and SDRAM
  10. proc csb732_init { } {
  11. # Disable fast writing only for init
  12. memwrite burst disable
  13. # All delay loops are omitted.
  14. # We assume the interpreter latency is enough.
  15. # Allow access to all coprocessors
  16. arm11 mcr imx35.cpu 15 0 15 1 0 0x2001
  17. # Disable MMU, caches, write buffer
  18. arm11 mcr imx35.cpu 15 0 1 0 0 0x78
  19. # Grant manager access to all domains
  20. arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF
  21. # Set ARM clock to 532 MHz, AHB to 133 MHz
  22. mww 0x53F80004 0x1000
  23. # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
  24. mww 0x53F8001C 0xB2C01
  25. set ESDMISC 0xB8001010
  26. set ESDCFG0 0xB8001004
  27. set ESDCTL0 0xB8001000
  28. # Enable DDR
  29. mww $ESDMISC 0x4
  30. # Timing
  31. mww $ESDCFG0 0x007fff3f
  32. # CS0
  33. mww $ESDCTL0 0x92120080
  34. # Precharge all dummy write
  35. mww 0x80000400 0
  36. # Enable CS) auto-refresh
  37. mww $ESDCTL0 0xA2120080
  38. # Refresh twice (dummy writes)
  39. mww 0x80000000 0
  40. mww 0x80000000 0
  41. # Enable CS0 load mode register
  42. mww $ESDCTL0 0xB2120080
  43. # Dummy writes
  44. mwb 0x80000033 0x01
  45. mwb 0x81000000 0x01
  46. mww $ESDCTL0 0x82226080
  47. mww 0x80000000 0
  48. # Re-enable fast writing
  49. memwrite burst enable
  50. }