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99 lines
2.3 KiB

  1. # A PXA255 test board with SST 39LF400A flash
  2. #
  3. # At reset the memory map is as follows. Note that
  4. # the memory map changes later on as the application
  5. # starts...
  6. #
  7. # RAM at 0x4000000
  8. # Flash at 0x00000000
  9. #
  10. source [find target/pxa255.cfg]
  11. # Target name is set by above
  12. $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
  13. # flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
  14. flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
  15. proc pxa255_sst_init {} {
  16. xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
  17. #
  18. # setup GPIO
  19. #
  20. mww 0x40E00018 0x00008000 #CPSR0
  21. sleep 20
  22. mww 0x40E0001C 0x00000002 #GPSR1
  23. sleep 20
  24. mww 0x40E00020 0x00000008 #GPSR2
  25. sleep 20
  26. mww 0x40E0000C 0x00008000 #GPDR0
  27. sleep 20
  28. mww 0x40E00054 0x80000000 #GAFR0_L
  29. sleep 20
  30. mww 0x40E00058 0x00188010 #GAFR0_H
  31. sleep 20
  32. mww 0x40E0005C 0x60908018 #GAFR1_L
  33. sleep 20
  34. mww 0x40E0000C 0x0280E000 #GPDR0
  35. sleep 20
  36. mww 0x40E00010 0x821C88B2 #GPDR1
  37. sleep 20
  38. mww 0x40E00014 0x000F03DB #GPDR2
  39. sleep 20
  40. mww 0x40E00000 0x000F03DB #GPLR0
  41. sleep 20
  42. mww 0x40F00004 0x00000020 #PSSR
  43. sleep 20
  44. #
  45. # setup memory controller
  46. #
  47. mww 0x48000008 0x01111998 #MSC0
  48. sleep 20
  49. mww 0x48000010 0x00047ff0 #MSC2
  50. sleep 20
  51. mww 0x48000014 0x00000000 #MECR
  52. sleep 20
  53. mww 0x48000028 0x00010504 #MCMEM0
  54. sleep 20
  55. mww 0x4800002C 0x00010504 #MCMEM1
  56. sleep 20
  57. mww 0x48000030 0x00010504 #MCATT0
  58. sleep 20
  59. mww 0x48000034 0x00010504 #MCATT1
  60. sleep 20
  61. mww 0x48000038 0x00004715 #MCIO0
  62. sleep 20
  63. mww 0x4800003C 0x00004715 #MCIO1
  64. sleep 20
  65. #
  66. mww 0x48000004 0x03CA4018 #MDREF
  67. sleep 20
  68. mww 0x48000004 0x004B4018 #MDREF
  69. sleep 20
  70. mww 0x48000004 0x000B4018 #MDREF
  71. sleep 20
  72. mww 0x48000004 0x000BC018 #MDREF
  73. sleep 20
  74. mww 0x48000000 0x00001AC8 #MDCNFG
  75. sleep 20
  76. sleep 20
  77. mww 0x48000000 0x00001AC9 #MDCNFG
  78. sleep 20
  79. mww 0x48000040 0x00000000 #MDMRS
  80. sleep 20
  81. }
  82. $_TARGETNAME configure -event reset-init {pxa255_sst_init}
  83. reset_config trst_and_srst
  84. jtag_nsrst_delay 200
  85. jtag_ntrst_delay 200
  86. #xscale debug_handler 0 0xFFFF0800 # debug handler base address