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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifndef ARM_DISASSEMBLER_H
  21. #define ARM_DISASSEMBLER_H
  22. enum arm_instruction_type {
  23. ARM_UNKNOWN_INSTUCTION,
  24. /* Branch instructions */
  25. ARM_B,
  26. ARM_BL,
  27. ARM_BX,
  28. ARM_BLX,
  29. /* Data processing instructions */
  30. ARM_AND,
  31. ARM_EOR,
  32. ARM_SUB,
  33. ARM_RSB,
  34. ARM_ADD,
  35. ARM_ADC,
  36. ARM_SBC,
  37. ARM_RSC,
  38. ARM_TST,
  39. ARM_TEQ,
  40. ARM_CMP,
  41. ARM_CMN,
  42. ARM_ORR,
  43. ARM_MOV,
  44. ARM_BIC,
  45. ARM_MVN,
  46. /* Load/store instructions */
  47. ARM_LDR,
  48. ARM_LDRB,
  49. ARM_LDRT,
  50. ARM_LDRBT,
  51. ARM_LDRH,
  52. ARM_LDRSB,
  53. ARM_LDRSH,
  54. ARM_LDM,
  55. ARM_STR,
  56. ARM_STRB,
  57. ARM_STRT,
  58. ARM_STRBT,
  59. ARM_STRH,
  60. ARM_STM,
  61. /* Status register access instructions */
  62. ARM_MRS,
  63. ARM_MSR,
  64. /* Multiply instructions */
  65. ARM_MUL,
  66. ARM_MLA,
  67. ARM_SMULL,
  68. ARM_SMLAL,
  69. ARM_UMULL,
  70. ARM_UMLAL,
  71. /* Miscellaneous instructions */
  72. ARM_CLZ,
  73. /* Exception generating instructions */
  74. ARM_BKPT,
  75. ARM_SWI,
  76. /* Coprocessor instructions */
  77. ARM_CDP,
  78. ARM_LDC,
  79. ARM_STC,
  80. ARM_MCR,
  81. ARM_MRC,
  82. /* Semaphore instructions */
  83. ARM_SWP,
  84. ARM_SWPB,
  85. /* Enhanced DSP extensions */
  86. ARM_MCRR,
  87. ARM_MRRC,
  88. ARM_PLD,
  89. ARM_QADD,
  90. ARM_QDADD,
  91. ARM_QSUB,
  92. ARM_QDSUB,
  93. ARM_SMLAxy,
  94. ARM_SMLALxy,
  95. ARM_SMLAWy,
  96. ARM_SMULxy,
  97. ARM_SMULWy,
  98. ARM_LDRD,
  99. ARM_STRD,
  100. ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
  101. };
  102. struct arm_b_bl_bx_blx_instr {
  103. int reg_operand;
  104. uint32_t target_address;
  105. };
  106. union arm_shifter_operand {
  107. struct {
  108. uint32_t immediate;
  109. } immediate;
  110. struct {
  111. uint8_t Rm;
  112. uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
  113. uint8_t shift_imm;
  114. } immediate_shift;
  115. struct {
  116. uint8_t Rm;
  117. uint8_t shift;
  118. uint8_t Rs;
  119. } register_shift;
  120. };
  121. struct arm_data_proc_instr {
  122. int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
  123. uint8_t S;
  124. uint8_t Rn;
  125. uint8_t Rd;
  126. union arm_shifter_operand shifter_operand;
  127. };
  128. struct arm_load_store_instr {
  129. uint8_t Rd;
  130. uint8_t Rn;
  131. uint8_t U;
  132. int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
  133. int offset_mode; /* 0: immediate, 1: (scaled) register */
  134. union {
  135. uint32_t offset;
  136. struct {
  137. uint8_t Rm;
  138. uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
  139. uint8_t shift_imm;
  140. } reg;
  141. } offset;
  142. };
  143. struct arm_load_store_multiple_instr {
  144. uint8_t Rn;
  145. uint32_t register_list;
  146. uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
  147. uint8_t S;
  148. uint8_t W;
  149. };
  150. struct arm_instruction {
  151. enum arm_instruction_type type;
  152. char text[128];
  153. uint32_t opcode;
  154. /* return value ... Thumb-2 sizes vary */
  155. unsigned instruction_size;
  156. union {
  157. struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
  158. struct arm_data_proc_instr data_proc;
  159. struct arm_load_store_instr load_store;
  160. struct arm_load_store_multiple_instr load_store_multiple;
  161. } info;
  162. };
  163. int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
  164. struct arm_instruction *instruction);
  165. int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
  166. struct arm_instruction *instruction);
  167. int thumb2_opcode(struct target *target, uint32_t address,
  168. struct arm_instruction *instruction);
  169. int arm_access_size(struct arm_instruction *instruction);
  170. #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
  171. #endif /* ARM_DISASSEMBLER_H */