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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * Copyright (C) 2007,2008 Øyvind Harboe *
  12. * oyvind.harboe@zylin.com *
  13. * *
  14. * This program is free software; you can redistribute it and/or modify *
  15. * it under the terms of the GNU General Public License as published by *
  16. * the Free Software Foundation; either version 2 of the License, or *
  17. * (at your option) any later version. *
  18. * *
  19. * This program is distributed in the hope that it will be useful, *
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  22. * GNU General Public License for more details. *
  23. * *
  24. * You should have received a copy of the GNU General Public License *
  25. * along with this program; if not, write to the *
  26. * Free Software Foundation, Inc., *
  27. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  28. * *
  29. * ARMv7-M Architecture, Application Level Reference Manual *
  30. * ARM DDI 0405C (September 2008) *
  31. * *
  32. ***************************************************************************/
  33. #ifdef HAVE_CONFIG_H
  34. #include "config.h"
  35. #endif
  36. #include "armv7m.h"
  37. #if 0
  38. #define _DEBUG_INSTRUCTION_EXECUTION_
  39. #endif
  40. char* armv7m_mode_strings[] =
  41. {
  42. "Thread", "Thread (User)", "Handler",
  43. };
  44. char* armv7m_exception_strings[] =
  45. {
  46. "", "Reset", "NMI", "HardFault",
  47. "MemManage", "BusFault", "UsageFault", "RESERVED",
  48. "RESERVED", "RESERVED", "RESERVED", "SVCall",
  49. "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  50. };
  51. char* armv7m_core_reg_list[] =
  52. {
  53. /* Registers accessed through core debug */
  54. "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  55. "sp", "lr", "pc",
  56. "xPSR", "msp", "psp",
  57. /* reg 20 has 4 bytes: CONTROL, FAULTMASK, BASEPRI, PRIMASK */
  58. "spec20",
  59. };
  60. uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  61. reg_t armv7m_gdb_dummy_fp_reg =
  62. {
  63. "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  64. };
  65. uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  66. reg_t armv7m_gdb_dummy_fps_reg =
  67. {
  68. "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  69. };
  70. #ifdef ARMV7_GDB_HACKS
  71. uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  72. reg_t armv7m_gdb_dummy_cpsr_reg =
  73. {
  74. "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
  75. };
  76. #endif
  77. armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  78. {
  79. /* CORE_GP are accesible using the core debug registers */
  80. {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  81. {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  82. {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  83. {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  84. {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  85. {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  86. {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  87. {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  88. {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  89. {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  90. {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  91. {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  92. {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  93. {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94. {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95. {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96. {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
  97. {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
  98. {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
  99. /* FIXME the register numbers here are core-specific.
  100. * Numbers 0..18 above work for all Cortex-M3 revisions.
  101. * Number 20 below works for CM3 r2p0 and later.
  102. */
  103. {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL},
  104. };
  105. int armv7m_core_reg_arch_type = -1;
  106. int armv7m_dummy_core_reg_arch_type = -1;
  107. int armv7m_restore_context(target_t *target)
  108. {
  109. int i;
  110. /* get pointers to arch-specific information */
  111. armv7m_common_t *armv7m = target->arch_info;
  112. LOG_DEBUG(" ");
  113. if (armv7m->pre_restore_context)
  114. armv7m->pre_restore_context(target);
  115. for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
  116. {
  117. if (armv7m->core_cache->reg_list[i].dirty)
  118. {
  119. armv7m->write_core_reg(target, i);
  120. }
  121. }
  122. if (armv7m->post_restore_context)
  123. armv7m->post_restore_context(target);
  124. return ERROR_OK;
  125. }
  126. /* Core state functions */
  127. char *armv7m_exception_string(int number)
  128. {
  129. static char enamebuf[32];
  130. if ((number < 0) | (number > 511))
  131. return "Invalid exception";
  132. if (number < 16)
  133. return armv7m_exception_strings[number];
  134. sprintf(enamebuf, "External Interrupt(%i)", number - 16);
  135. return enamebuf;
  136. }
  137. int armv7m_get_core_reg(reg_t *reg)
  138. {
  139. int retval;
  140. armv7m_core_reg_t *armv7m_reg = reg->arch_info;
  141. target_t *target = armv7m_reg->target;
  142. armv7m_common_t *armv7m_target = target->arch_info;
  143. if (target->state != TARGET_HALTED)
  144. {
  145. return ERROR_TARGET_NOT_HALTED;
  146. }
  147. retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
  148. return retval;
  149. }
  150. int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
  151. {
  152. armv7m_core_reg_t *armv7m_reg = reg->arch_info;
  153. target_t *target = armv7m_reg->target;
  154. uint32_t value = buf_get_u32(buf, 0, 32);
  155. if (target->state != TARGET_HALTED)
  156. {
  157. return ERROR_TARGET_NOT_HALTED;
  158. }
  159. buf_set_u32(reg->value, 0, 32, value);
  160. reg->dirty = 1;
  161. reg->valid = 1;
  162. return ERROR_OK;
  163. }
  164. int armv7m_read_core_reg(struct target_s *target, int num)
  165. {
  166. uint32_t reg_value;
  167. int retval;
  168. armv7m_core_reg_t * armv7m_core_reg;
  169. /* get pointers to arch-specific information */
  170. armv7m_common_t *armv7m = target->arch_info;
  171. if ((num < 0) || (num >= ARMV7NUMCOREREGS))
  172. return ERROR_INVALID_ARGUMENTS;
  173. armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
  174. retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
  175. buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
  176. armv7m->core_cache->reg_list[num].valid = 1;
  177. armv7m->core_cache->reg_list[num].dirty = 0;
  178. return retval;
  179. }
  180. int armv7m_write_core_reg(struct target_s *target, int num)
  181. {
  182. int retval;
  183. uint32_t reg_value;
  184. armv7m_core_reg_t *armv7m_core_reg;
  185. /* get pointers to arch-specific information */
  186. armv7m_common_t *armv7m = target->arch_info;
  187. if ((num < 0) || (num >= ARMV7NUMCOREREGS))
  188. return ERROR_INVALID_ARGUMENTS;
  189. reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
  190. armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
  191. retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
  192. if (retval != ERROR_OK)
  193. {
  194. LOG_ERROR("JTAG failure");
  195. armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
  196. return ERROR_JTAG_DEVICE_ERROR;
  197. }
  198. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
  199. armv7m->core_cache->reg_list[num].valid = 1;
  200. armv7m->core_cache->reg_list[num].dirty = 0;
  201. return ERROR_OK;
  202. }
  203. int armv7m_invalidate_core_regs(target_t *target)
  204. {
  205. /* get pointers to arch-specific information */
  206. armv7m_common_t *armv7m = target->arch_info;
  207. int i;
  208. for (i = 0; i < armv7m->core_cache->num_regs; i++)
  209. {
  210. armv7m->core_cache->reg_list[i].valid = 0;
  211. armv7m->core_cache->reg_list[i].dirty = 0;
  212. }
  213. return ERROR_OK;
  214. }
  215. int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
  216. {
  217. /* get pointers to arch-specific information */
  218. armv7m_common_t *armv7m = target->arch_info;
  219. int i;
  220. *reg_list_size = 26;
  221. *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
  222. for (i = 0; i < 16; i++)
  223. {
  224. (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
  225. }
  226. for (i = 16; i < 24; i++)
  227. {
  228. (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
  229. }
  230. (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
  231. #ifdef ARMV7_GDB_HACKS
  232. /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
  233. (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
  234. /* ARMV7M is always in thumb mode, try to make GDB understand this
  235. * if it does not support this arch */
  236. *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
  237. #else
  238. (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
  239. #endif
  240. return ERROR_OK;
  241. }
  242. /* run to exit point. return error if exit point was not reached. */
  243. static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
  244. {
  245. uint32_t pc;
  246. int retval;
  247. /* This code relies on the target specific resume() and poll()->debug_entry()
  248. * sequence to write register values to the processor and the read them back */
  249. if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
  250. {
  251. return retval;
  252. }
  253. retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
  254. /* If the target fails to halt due to the breakpoint, force a halt */
  255. if (retval != ERROR_OK || target->state != TARGET_HALTED)
  256. {
  257. if ((retval = target_halt(target)) != ERROR_OK)
  258. return retval;
  259. if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
  260. {
  261. return retval;
  262. }
  263. return ERROR_TARGET_TIMEOUT;
  264. }
  265. armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
  266. if (pc != exit_point)
  267. {
  268. LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
  269. return ERROR_TARGET_TIMEOUT;
  270. }
  271. return ERROR_OK;
  272. }
  273. int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
  274. {
  275. /* get pointers to arch-specific information */
  276. armv7m_common_t *armv7m = target->arch_info;
  277. armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
  278. enum armv7m_mode core_mode = armv7m->core_mode;
  279. int retval = ERROR_OK;
  280. int i;
  281. uint32_t context[ARMV7NUMCOREREGS];
  282. if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
  283. {
  284. LOG_ERROR("current target isn't an ARMV7M target");
  285. return ERROR_TARGET_INVALID;
  286. }
  287. if (target->state != TARGET_HALTED)
  288. {
  289. LOG_WARNING("target not halted");
  290. return ERROR_TARGET_NOT_HALTED;
  291. }
  292. /* refresh core register cache */
  293. /* Not needed if core register cache is always consistent with target process state */
  294. for (i = 0; i < ARMV7NUMCOREREGS; i++)
  295. {
  296. if (!armv7m->core_cache->reg_list[i].valid)
  297. armv7m->read_core_reg(target, i);
  298. context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
  299. }
  300. for (i = 0; i < num_mem_params; i++)
  301. {
  302. if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
  303. return retval;
  304. }
  305. for (i = 0; i < num_reg_params; i++)
  306. {
  307. reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
  308. // uint32_t regvalue;
  309. if (!reg)
  310. {
  311. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  312. exit(-1);
  313. }
  314. if (reg->size != reg_params[i].size)
  315. {
  316. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
  317. exit(-1);
  318. }
  319. // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
  320. armv7m_set_core_reg(reg, reg_params[i].value);
  321. }
  322. /* NOTE: CONTROL is bits 31:24 of SPEC20 register, if it's present;
  323. * holding a two-bit field.
  324. *
  325. * FIXME need a solution using ARMV7M_T_MSR(). Use it at least for
  326. * earlier cores.
  327. */
  328. if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY
  329. && armv7m->has_spec20)
  330. {
  331. LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
  332. buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20].value,
  333. 24, 2, armv7m_algorithm_info->core_mode);
  334. armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1;
  335. armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1;
  336. }
  337. /* ARMV7M always runs in Thumb state */
  338. if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
  339. {
  340. LOG_ERROR("can't add breakpoint to finish algorithm execution");
  341. return ERROR_TARGET_FAILURE;
  342. }
  343. retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
  344. breakpoint_remove(target, exit_point);
  345. if (retval != ERROR_OK)
  346. {
  347. return retval;
  348. }
  349. /* Read memory values to mem_params[] */
  350. for (i = 0; i < num_mem_params; i++)
  351. {
  352. if (mem_params[i].direction != PARAM_OUT)
  353. if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
  354. {
  355. return retval;
  356. }
  357. }
  358. /* Copy core register values to reg_params[] */
  359. for (i = 0; i < num_reg_params; i++)
  360. {
  361. if (reg_params[i].direction != PARAM_OUT)
  362. {
  363. reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
  364. if (!reg)
  365. {
  366. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  367. exit(-1);
  368. }
  369. if (reg->size != reg_params[i].size)
  370. {
  371. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
  372. exit(-1);
  373. }
  374. buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
  375. }
  376. }
  377. for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
  378. {
  379. uint32_t regvalue;
  380. regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
  381. if (regvalue != context[i])
  382. {
  383. LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
  384. buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
  385. armv7m->core_cache->reg_list[i].valid = 1;
  386. armv7m->core_cache->reg_list[i].dirty = 1;
  387. }
  388. }
  389. armv7m->core_mode = core_mode;
  390. return retval;
  391. }
  392. int armv7m_arch_state(struct target_s *target)
  393. {
  394. /* get pointers to arch-specific information */
  395. armv7m_common_t *armv7m = target->arch_info;
  396. LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
  397. Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
  398. armv7m_mode_strings[armv7m->core_mode],
  399. armv7m_exception_string(armv7m->exception_number),
  400. buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
  401. buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
  402. return ERROR_OK;
  403. }
  404. reg_cache_t *armv7m_build_reg_cache(target_t *target)
  405. {
  406. /* get pointers to arch-specific information */
  407. armv7m_common_t *armv7m = target->arch_info;
  408. int num_regs = ARMV7NUMCOREREGS;
  409. reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
  410. reg_cache_t *cache = malloc(sizeof(reg_cache_t));
  411. reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
  412. armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
  413. int i;
  414. if (armv7m_core_reg_arch_type == -1)
  415. {
  416. armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
  417. }
  418. register_init_dummy(&armv7m_gdb_dummy_fps_reg);
  419. #ifdef ARMV7_GDB_HACKS
  420. register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
  421. #endif
  422. register_init_dummy(&armv7m_gdb_dummy_fp_reg);
  423. /* Build the process context cache */
  424. cache->name = "arm v7m registers";
  425. cache->next = NULL;
  426. cache->reg_list = reg_list;
  427. cache->num_regs = num_regs;
  428. (*cache_p) = cache;
  429. armv7m->core_cache = cache;
  430. for (i = 0; i < num_regs; i++)
  431. {
  432. arch_info[i] = armv7m_core_reg_list_arch_info[i];
  433. arch_info[i].target = target;
  434. arch_info[i].armv7m_common = armv7m;
  435. reg_list[i].name = armv7m_core_reg_list[i];
  436. reg_list[i].size = 32;
  437. reg_list[i].value = calloc(1, 4);
  438. reg_list[i].dirty = 0;
  439. reg_list[i].valid = 0;
  440. reg_list[i].bitfield_desc = NULL;
  441. reg_list[i].num_bitfields = 0;
  442. reg_list[i].arch_type = armv7m_core_reg_arch_type;
  443. reg_list[i].arch_info = &arch_info[i];
  444. }
  445. return cache;
  446. }
  447. int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  448. {
  449. armv7m_build_reg_cache(target);
  450. return ERROR_OK;
  451. }
  452. int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
  453. {
  454. /* register arch-specific functions */
  455. target->arch_info = armv7m;
  456. armv7m->read_core_reg = armv7m_read_core_reg;
  457. armv7m->write_core_reg = armv7m_write_core_reg;
  458. return ERROR_OK;
  459. }
  460. int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
  461. {
  462. working_area_t *crc_algorithm;
  463. armv7m_algorithm_t armv7m_info;
  464. reg_param_t reg_params[2];
  465. int retval;
  466. uint16_t cortex_m3_crc_code[] = {
  467. 0x4602, /* mov r2, r0 */
  468. 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
  469. 0x460B, /* mov r3, r1 */
  470. 0xF04F, 0x0400, /* mov r4, #0 */
  471. 0xE013, /* b ncomp */
  472. /* nbyte: */
  473. 0x5D11, /* ldrb r1, [r2, r4] */
  474. 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
  475. 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
  476. 0xF04F, 0x0500, /* mov r5, #0 */
  477. /* loop: */
  478. 0x2800, /* cmp r0, #0 */
  479. 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
  480. 0xF105, 0x0501, /* add r5, r5, #1 */
  481. 0x4630, /* mov r0, r6 */
  482. 0xBFB8, /* it lt */
  483. 0xEA86, 0x0007, /* eor r0, r6, r7 */
  484. 0x2D08, /* cmp r5, #8 */
  485. 0xD1F4, /* bne loop */
  486. 0xF104, 0x0401, /* add r4, r4, #1 */
  487. /* ncomp: */
  488. 0x429C, /* cmp r4, r3 */
  489. 0xD1E9, /* bne nbyte */
  490. /* end: */
  491. 0xE7FE, /* b end */
  492. 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
  493. };
  494. uint32_t i;
  495. if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
  496. {
  497. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  498. }
  499. /* convert flash writing code into a buffer in target endianness */
  500. for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
  501. if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
  502. {
  503. return retval;
  504. }
  505. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  506. armv7m_info.core_mode = ARMV7M_MODE_ANY;
  507. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
  508. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  509. buf_set_u32(reg_params[0].value, 0, 32, address);
  510. buf_set_u32(reg_params[1].value, 0, 32, count);
  511. if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
  512. crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
  513. {
  514. LOG_ERROR("error executing cortex_m3 crc algorithm");
  515. destroy_reg_param(&reg_params[0]);
  516. destroy_reg_param(&reg_params[1]);
  517. target_free_working_area(target, crc_algorithm);
  518. return retval;
  519. }
  520. *checksum = buf_get_u32(reg_params[0].value, 0, 32);
  521. destroy_reg_param(&reg_params[0]);
  522. destroy_reg_param(&reg_params[1]);
  523. target_free_working_area(target, crc_algorithm);
  524. return ERROR_OK;
  525. }
  526. int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
  527. {
  528. working_area_t *erase_check_algorithm;
  529. reg_param_t reg_params[3];
  530. armv7m_algorithm_t armv7m_info;
  531. int retval;
  532. uint32_t i;
  533. uint16_t erase_check_code[] =
  534. {
  535. /* loop: */
  536. 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
  537. 0xEA02, 0x0203, /* and r2, r2, r3 */
  538. 0x3901, /* subs r1, r1, #1 */
  539. 0xD1F9, /* bne loop */
  540. /* end: */
  541. 0xE7FE, /* b end */
  542. };
  543. /* make sure we have a working area */
  544. if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
  545. {
  546. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  547. }
  548. /* convert flash writing code into a buffer in target endianness */
  549. for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
  550. target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
  551. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  552. armv7m_info.core_mode = ARMV7M_MODE_ANY;
  553. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  554. buf_set_u32(reg_params[0].value, 0, 32, address);
  555. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  556. buf_set_u32(reg_params[1].value, 0, 32, count);
  557. init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
  558. buf_set_u32(reg_params[2].value, 0, 32, 0xff);
  559. if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
  560. erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
  561. {
  562. destroy_reg_param(&reg_params[0]);
  563. destroy_reg_param(&reg_params[1]);
  564. destroy_reg_param(&reg_params[2]);
  565. target_free_working_area(target, erase_check_algorithm);
  566. return 0;
  567. }
  568. *blank = buf_get_u32(reg_params[2].value, 0, 32);
  569. destroy_reg_param(&reg_params[0]);
  570. destroy_reg_param(&reg_params[1]);
  571. destroy_reg_param(&reg_params[2]);
  572. target_free_working_area(target, erase_check_algorithm);
  573. return ERROR_OK;
  574. }
  575. /*
  576. * Return the debug ap baseaddress in hexadecimal;
  577. * no extra output to simplify script processing
  578. */
  579. static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
  580. char *cmd, char **args, int argc)
  581. {
  582. target_t *target = get_current_target(cmd_ctx);
  583. armv7m_common_t *armv7m = target->arch_info;
  584. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  585. uint32_t apsel, apselsave, baseaddr;
  586. int retval;
  587. apsel = swjdp->apsel;
  588. apselsave = swjdp->apsel;
  589. if (argc > 0)
  590. {
  591. apsel = strtoul(args[0], NULL, 0);
  592. }
  593. if (apselsave != apsel)
  594. {
  595. dap_ap_select(swjdp, apsel);
  596. }
  597. dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
  598. retval = swjdp_transaction_endcheck(swjdp);
  599. command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
  600. if (apselsave != apsel)
  601. {
  602. dap_ap_select(swjdp, apselsave);
  603. }
  604. return retval;
  605. }
  606. /*
  607. * Return the debug ap id in hexadecimal;
  608. * no extra output to simplify script processing
  609. */
  610. extern int handle_dap_apid_command(struct command_context_s *cmd_ctx,
  611. char *cmd, char **args, int argc)
  612. {
  613. target_t *target = get_current_target(cmd_ctx);
  614. armv7m_common_t *armv7m = target->arch_info;
  615. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  616. return dap_apid_command(cmd_ctx, swjdp, args, argc);
  617. }
  618. static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
  619. char *cmd, char **args, int argc)
  620. {
  621. target_t *target = get_current_target(cmd_ctx);
  622. armv7m_common_t *armv7m = target->arch_info;
  623. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  624. return dap_apsel_command(cmd_ctx, swjdp, args, argc);
  625. }
  626. static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
  627. char *cmd, char **args, int argc)
  628. {
  629. target_t *target = get_current_target(cmd_ctx);
  630. armv7m_common_t *armv7m = target->arch_info;
  631. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  632. return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
  633. }
  634. static int handle_dap_info_command(struct command_context_s *cmd_ctx,
  635. char *cmd, char **args, int argc)
  636. {
  637. target_t *target = get_current_target(cmd_ctx);
  638. armv7m_common_t *armv7m = target->arch_info;
  639. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  640. uint32_t apsel;
  641. apsel = swjdp->apsel;
  642. if (argc > 0)
  643. apsel = strtoul(args[0], NULL, 0);
  644. return dap_info_command(cmd_ctx, swjdp, apsel);
  645. }
  646. int armv7m_register_commands(struct command_context_s *cmd_ctx)
  647. {
  648. command_t *arm_adi_v5_dap_cmd;
  649. arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
  650. NULL, COMMAND_ANY,
  651. "cortex dap specific commands");
  652. register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
  653. handle_dap_info_command, COMMAND_EXEC,
  654. "Displays dap info for ap [num],"
  655. "default currently selected AP");
  656. register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
  657. handle_dap_apsel_command, COMMAND_EXEC,
  658. "Select a different AP [num] (default 0)");
  659. register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
  660. handle_dap_apid_command, COMMAND_EXEC,
  661. "Displays id reg from AP [num], "
  662. "default currently selected AP");
  663. register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
  664. handle_dap_baseaddr_command, COMMAND_EXEC,
  665. "Displays debug base address from AP [num],"
  666. "default currently selected AP");
  667. register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
  668. handle_dap_memaccess_command, COMMAND_EXEC,
  669. "set/get number of extra tck for mem-ap "
  670. "memory bus access [0-255]");
  671. return ERROR_OK;
  672. }