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- # Copyright (C) 2014-2015,2020 Synopsys, Inc.
- # Anton Kolesov <anton.kolesov@synopsys.com>
- # Didin Evgeniy <didin@synopsys.com>
- #
- # SPDX-License-Identifier: GPL-2.0-or-later
-
- #
- # Xilinx Spartan-6 XC6SLX45 FPGA on EM Starter Kit v1.
- # Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
- #
-
- source [find cpu/arc/em.tcl]
-
- set _CHIPNAME arc-em
- set _TARGETNAME $_CHIPNAME.cpu
-
- # EM SK IDENTITY is 0x200444b1
- # EM SK v2 IDENTITY is 0x200044b1
- jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
- -expected-id 0x200044b1
-
- set _coreid 0
- set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
-
- target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
- -coreid 0 -dbgbase $_dbgbase -endian little
-
- # There is no SRST, so do a software reset
- $_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
-
- arc_em_init_regs
-
- # vim:ft=tcl
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