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  1. /***************************************************************************
  2. * Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com> *
  3. * Based on mips_m4k code: *
  4. * Copyright (C) 2008 by Spencer Oliver <spen@spen-soft.co.uk> *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  21. ***************************************************************************/
  22. #ifdef HAVE_CONFIG_H
  23. #include "config.h"
  24. #endif
  25. #include "jtag/jtag.h"
  26. #include "register.h"
  27. #include "algorithm.h"
  28. #include "target.h"
  29. #include "breakpoints.h"
  30. #include "target_type.h"
  31. #include "avr32_jtag.h"
  32. #include "avr32_mem.h"
  33. #include "avr32_regs.h"
  34. #include "avr32_ap7k.h"
  35. static char *avr32_core_reg_list[] = {
  36. "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
  37. "r9", "r10", "r11", "r12", "sp", "lr", "pc", "sr"
  38. };
  39. static struct avr32_core_reg
  40. avr32_core_reg_list_arch_info[AVR32NUMCOREREGS] = {
  41. {0, NULL, NULL},
  42. {1, NULL, NULL},
  43. {2, NULL, NULL},
  44. {3, NULL, NULL},
  45. {4, NULL, NULL},
  46. {5, NULL, NULL},
  47. {6, NULL, NULL},
  48. {7, NULL, NULL},
  49. {8, NULL, NULL},
  50. {9, NULL, NULL},
  51. {10, NULL, NULL},
  52. {11, NULL, NULL},
  53. {12, NULL, NULL},
  54. {13, NULL, NULL},
  55. {14, NULL, NULL},
  56. {15, NULL, NULL},
  57. {16, NULL, NULL},
  58. };
  59. static int avr32_read_core_reg(struct target *target, int num);
  60. static int avr32_write_core_reg(struct target *target, int num);
  61. int avr32_ap7k_save_context(struct target *target)
  62. {
  63. int retval, i;
  64. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  65. retval = avr32_jtag_read_regs(&ap7k->jtag, ap7k->core_regs);
  66. if (retval != ERROR_OK)
  67. return retval;
  68. for (i = 0; i < AVR32NUMCOREREGS; i++) {
  69. if (!ap7k->core_cache->reg_list[i].valid)
  70. avr32_read_core_reg(target, i);
  71. }
  72. return ERROR_OK;
  73. }
  74. int avr32_ap7k_restore_context(struct target *target)
  75. {
  76. int i;
  77. /* get pointers to arch-specific information */
  78. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  79. for (i = 0; i < AVR32NUMCOREREGS; i++) {
  80. if (ap7k->core_cache->reg_list[i].dirty)
  81. avr32_write_core_reg(target, i);
  82. }
  83. /* write core regs */
  84. avr32_jtag_write_regs(&ap7k->jtag, ap7k->core_regs);
  85. return ERROR_OK;
  86. }
  87. static int avr32_read_core_reg(struct target *target, int num)
  88. {
  89. uint32_t reg_value;
  90. /* get pointers to arch-specific information */
  91. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  92. if ((num < 0) || (num >= AVR32NUMCOREREGS))
  93. return ERROR_COMMAND_SYNTAX_ERROR;
  94. reg_value = ap7k->core_regs[num];
  95. buf_set_u32(ap7k->core_cache->reg_list[num].value, 0, 32, reg_value);
  96. ap7k->core_cache->reg_list[num].valid = 1;
  97. ap7k->core_cache->reg_list[num].dirty = 0;
  98. return ERROR_OK;
  99. }
  100. static int avr32_write_core_reg(struct target *target, int num)
  101. {
  102. uint32_t reg_value;
  103. /* get pointers to arch-specific information */
  104. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  105. if ((num < 0) || (num >= AVR32NUMCOREREGS))
  106. return ERROR_COMMAND_SYNTAX_ERROR;
  107. reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32);
  108. ap7k->core_regs[num] = reg_value;
  109. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
  110. ap7k->core_cache->reg_list[num].valid = 1;
  111. ap7k->core_cache->reg_list[num].dirty = 0;
  112. return ERROR_OK;
  113. }
  114. static int avr32_get_core_reg(struct reg *reg)
  115. {
  116. int retval;
  117. struct avr32_core_reg *avr32_reg = reg->arch_info;
  118. struct target *target = avr32_reg->target;
  119. if (target->state != TARGET_HALTED)
  120. return ERROR_TARGET_NOT_HALTED;
  121. retval = avr32_read_core_reg(target, avr32_reg->num);
  122. return retval;
  123. }
  124. static int avr32_set_core_reg(struct reg *reg, uint8_t *buf)
  125. {
  126. struct avr32_core_reg *avr32_reg = reg->arch_info;
  127. struct target *target = avr32_reg->target;
  128. uint32_t value = buf_get_u32(buf, 0, 32);
  129. if (target->state != TARGET_HALTED)
  130. return ERROR_TARGET_NOT_HALTED;
  131. buf_set_u32(reg->value, 0, 32, value);
  132. reg->dirty = 1;
  133. reg->valid = 1;
  134. return ERROR_OK;
  135. }
  136. static const struct reg_arch_type avr32_reg_type = {
  137. .get = avr32_get_core_reg,
  138. .set = avr32_set_core_reg,
  139. };
  140. static struct reg_cache *avr32_build_reg_cache(struct target *target)
  141. {
  142. int num_regs = AVR32NUMCOREREGS;
  143. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  144. struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
  145. struct reg_cache *cache = malloc(sizeof(struct reg_cache));
  146. struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
  147. struct avr32_core_reg *arch_info =
  148. malloc(sizeof(struct avr32_core_reg) * num_regs);
  149. int i;
  150. /* Build the process context cache */
  151. cache->name = "avr32 registers";
  152. cache->next = NULL;
  153. cache->reg_list = reg_list;
  154. cache->num_regs = num_regs;
  155. (*cache_p) = cache;
  156. ap7k->core_cache = cache;
  157. for (i = 0; i < num_regs; i++) {
  158. arch_info[i] = avr32_core_reg_list_arch_info[i];
  159. arch_info[i].target = target;
  160. arch_info[i].avr32_common = ap7k;
  161. reg_list[i].name = avr32_core_reg_list[i];
  162. reg_list[i].size = 32;
  163. reg_list[i].value = calloc(1, 4);
  164. reg_list[i].dirty = 0;
  165. reg_list[i].valid = 0;
  166. reg_list[i].type = &avr32_reg_type;
  167. reg_list[i].arch_info = &arch_info[i];
  168. }
  169. return cache;
  170. }
  171. static int avr32_ap7k_debug_entry(struct target *target)
  172. {
  173. uint32_t dpc, dinst;
  174. int retval;
  175. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  176. retval = avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DPC, &dpc);
  177. if (retval != ERROR_OK)
  178. return retval;
  179. retval = avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DINST, &dinst);
  180. if (retval != ERROR_OK)
  181. return retval;
  182. ap7k->jtag.dpc = dpc;
  183. avr32_ap7k_save_context(target);
  184. return ERROR_OK;
  185. }
  186. static int avr32_ap7k_poll(struct target *target)
  187. {
  188. uint32_t ds;
  189. int retval;
  190. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  191. retval = avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DS, &ds);
  192. if (retval != ERROR_OK)
  193. return retval;
  194. /* check for processor halted */
  195. if (ds & OCDREG_DS_DBA) {
  196. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
  197. target->state = TARGET_HALTED;
  198. retval = avr32_ap7k_debug_entry(target);
  199. if (retval != ERROR_OK)
  200. return retval;
  201. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  202. } else if (target->state == TARGET_DEBUG_RUNNING) {
  203. target->state = TARGET_HALTED;
  204. retval = avr32_ap7k_debug_entry(target);
  205. if (retval != ERROR_OK)
  206. return retval;
  207. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  208. }
  209. } else
  210. target->state = TARGET_RUNNING;
  211. return ERROR_OK;
  212. }
  213. static int avr32_ap7k_halt(struct target *target)
  214. {
  215. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  216. LOG_DEBUG("target->state: %s",
  217. target_state_name(target));
  218. if (target->state == TARGET_HALTED) {
  219. LOG_DEBUG("target was already halted");
  220. return ERROR_OK;
  221. }
  222. if (target->state == TARGET_UNKNOWN)
  223. LOG_WARNING("target was in unknown state when halt was requested");
  224. if (target->state == TARGET_RESET) {
  225. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
  226. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  227. return ERROR_TARGET_FAILURE;
  228. } else {
  229. target->debug_reason = DBG_REASON_DBGRQ;
  230. return ERROR_OK;
  231. }
  232. }
  233. avr32_ocd_setbits(&ap7k->jtag, AVR32_OCDREG_DC, OCDREG_DC_DBR);
  234. target->debug_reason = DBG_REASON_DBGRQ;
  235. return ERROR_OK;
  236. }
  237. static int avr32_ap7k_assert_reset(struct target *target)
  238. {
  239. LOG_ERROR("%s: implement me", __func__);
  240. return ERROR_OK;
  241. }
  242. static int avr32_ap7k_deassert_reset(struct target *target)
  243. {
  244. LOG_ERROR("%s: implement me", __func__);
  245. return ERROR_OK;
  246. }
  247. static int avr32_ap7k_soft_reset_halt(struct target *target)
  248. {
  249. LOG_ERROR("%s: implement me", __func__);
  250. return ERROR_OK;
  251. }
  252. static int avr32_ap7k_resume(struct target *target, int current,
  253. uint32_t address, int handle_breakpoints, int debug_execution)
  254. {
  255. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  256. struct breakpoint *breakpoint = NULL;
  257. uint32_t resume_pc;
  258. int retval;
  259. if (target->state != TARGET_HALTED) {
  260. LOG_WARNING("target not halted");
  261. return ERROR_TARGET_NOT_HALTED;
  262. }
  263. if (!debug_execution) {
  264. target_free_all_working_areas(target);
  265. /*
  266. avr32_ap7k_enable_breakpoints(target);
  267. avr32_ap7k_enable_watchpoints(target);
  268. */
  269. }
  270. /* current = 1: continue on current pc, otherwise continue at <address> */
  271. if (!current) {
  272. #if 0
  273. if (retval != ERROR_OK)
  274. return retval;
  275. #endif
  276. }
  277. resume_pc = buf_get_u32(ap7k->core_cache->reg_list[AVR32_REG_PC].value, 0, 32);
  278. avr32_ap7k_restore_context(target);
  279. /* the front-end may request us not to handle breakpoints */
  280. if (handle_breakpoints) {
  281. /* Single step past breakpoint at current address */
  282. breakpoint = breakpoint_find(target, resume_pc);
  283. if (breakpoint) {
  284. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  285. #if 0
  286. avr32_ap7k_unset_breakpoint(target, breakpoint);
  287. avr32_ap7k_single_step_core(target);
  288. avr32_ap7k_set_breakpoint(target, breakpoint);
  289. #endif
  290. }
  291. }
  292. #if 0
  293. /* enable interrupts if we are running */
  294. avr32_ap7k_enable_interrupts(target, !debug_execution);
  295. /* exit debug mode */
  296. mips_ejtag_exit_debug(ejtag_info);
  297. #endif
  298. retval = avr32_ocd_clearbits(&ap7k->jtag, AVR32_OCDREG_DC,
  299. OCDREG_DC_DBR);
  300. if (retval != ERROR_OK)
  301. return retval;
  302. retval = avr32_jtag_exec(&ap7k->jtag, RETD);
  303. if (retval != ERROR_OK)
  304. return retval;
  305. target->debug_reason = DBG_REASON_NOTHALTED;
  306. /* registers are now invalid */
  307. register_cache_invalidate(ap7k->core_cache);
  308. if (!debug_execution) {
  309. target->state = TARGET_RUNNING;
  310. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  311. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  312. } else {
  313. target->state = TARGET_DEBUG_RUNNING;
  314. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  315. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  316. }
  317. return ERROR_OK;
  318. }
  319. static int avr32_ap7k_step(struct target *target, int current,
  320. uint32_t address, int handle_breakpoints)
  321. {
  322. LOG_ERROR("%s: implement me", __func__);
  323. return ERROR_OK;
  324. }
  325. static int avr32_ap7k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  326. {
  327. LOG_ERROR("%s: implement me", __func__);
  328. return ERROR_OK;
  329. }
  330. static int avr32_ap7k_remove_breakpoint(struct target *target,
  331. struct breakpoint *breakpoint)
  332. {
  333. LOG_ERROR("%s: implement me", __func__);
  334. return ERROR_OK;
  335. }
  336. static int avr32_ap7k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  337. {
  338. LOG_ERROR("%s: implement me", __func__);
  339. return ERROR_OK;
  340. }
  341. static int avr32_ap7k_remove_watchpoint(struct target *target,
  342. struct watchpoint *watchpoint)
  343. {
  344. LOG_ERROR("%s: implement me", __func__);
  345. return ERROR_OK;
  346. }
  347. static int avr32_ap7k_read_memory(struct target *target, uint32_t address,
  348. uint32_t size, uint32_t count, uint8_t *buffer)
  349. {
  350. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  351. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
  352. address,
  353. size,
  354. count);
  355. if (target->state != TARGET_HALTED) {
  356. LOG_WARNING("target not halted");
  357. return ERROR_TARGET_NOT_HALTED;
  358. }
  359. /* sanitize arguments */
  360. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  361. return ERROR_COMMAND_SYNTAX_ERROR;
  362. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  363. return ERROR_TARGET_UNALIGNED_ACCESS;
  364. switch (size) {
  365. case 4:
  366. return avr32_jtag_read_memory32(&ap7k->jtag, address, count,
  367. (uint32_t *)(void *)buffer);
  368. break;
  369. case 2:
  370. return avr32_jtag_read_memory16(&ap7k->jtag, address, count,
  371. (uint16_t *)(void *)buffer);
  372. break;
  373. case 1:
  374. return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer);
  375. break;
  376. default:
  377. break;
  378. }
  379. return ERROR_OK;
  380. }
  381. static int avr32_ap7k_write_memory(struct target *target, uint32_t address,
  382. uint32_t size, uint32_t count, const uint8_t *buffer)
  383. {
  384. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  385. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
  386. address,
  387. size,
  388. count);
  389. if (target->state != TARGET_HALTED) {
  390. LOG_WARNING("target not halted");
  391. return ERROR_TARGET_NOT_HALTED;
  392. }
  393. /* sanitize arguments */
  394. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  395. return ERROR_COMMAND_SYNTAX_ERROR;
  396. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  397. return ERROR_TARGET_UNALIGNED_ACCESS;
  398. switch (size) {
  399. case 4:
  400. return avr32_jtag_write_memory32(&ap7k->jtag, address, count,
  401. (uint32_t *)(void *)buffer);
  402. break;
  403. case 2:
  404. return avr32_jtag_write_memory16(&ap7k->jtag, address, count,
  405. (uint16_t *)(void *)buffer);
  406. break;
  407. case 1:
  408. return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer);
  409. break;
  410. default:
  411. break;
  412. }
  413. return ERROR_OK;
  414. }
  415. static int avr32_ap7k_init_target(struct command_context *cmd_ctx,
  416. struct target *target)
  417. {
  418. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  419. ap7k->jtag.tap = target->tap;
  420. avr32_build_reg_cache(target);
  421. return ERROR_OK;
  422. }
  423. static int avr32_ap7k_target_create(struct target *target, Jim_Interp *interp)
  424. {
  425. struct avr32_ap7k_common *ap7k = calloc(1, sizeof(struct
  426. avr32_ap7k_common));
  427. ap7k->common_magic = AP7k_COMMON_MAGIC;
  428. target->arch_info = ap7k;
  429. return ERROR_OK;
  430. }
  431. static int avr32_ap7k_examine(struct target *target)
  432. {
  433. uint32_t devid, ds;
  434. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  435. if (!target_was_examined(target)) {
  436. target_set_examined(target);
  437. avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DID, &devid);
  438. LOG_INFO("device id: %08x", devid);
  439. avr32_ocd_setbits(&ap7k->jtag, AVR32_OCDREG_DC, OCDREG_DC_DBE);
  440. avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DS, &ds);
  441. /* check for processor halted */
  442. if (ds & OCDREG_DS_DBA) {
  443. LOG_INFO("target is halted");
  444. target->state = TARGET_HALTED;
  445. } else
  446. target->state = TARGET_RUNNING;
  447. }
  448. return ERROR_OK;
  449. }
  450. int avr32_ap7k_arch_state(struct target *target)
  451. {
  452. struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
  453. LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
  454. debug_reason_name(target), ap7k->jtag.dpc);
  455. return ERROR_OK;
  456. }
  457. int avr32_ap7k_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
  458. {
  459. #if 0
  460. /* get pointers to arch-specific information */
  461. int i;
  462. /* include floating point registers */
  463. *reg_list_size = AVR32NUMCOREREGS + AVR32NUMFPREGS;
  464. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  465. for (i = 0; i < AVR32NUMCOREREGS; i++)
  466. (*reg_list)[i] = &mips32->core_cache->reg_list[i];
  467. /* add dummy floating points regs */
  468. for (i = AVR32NUMCOREREGS; i < (AVR32NUMCOREREGS + AVR32NUMFPREGS); i++)
  469. (*reg_list)[i] = &avr32_ap7k_gdb_dummy_fp_reg;
  470. #endif
  471. LOG_ERROR("%s: implement me", __func__);
  472. return ERROR_FAIL;
  473. }
  474. struct target_type avr32_ap7k_target = {
  475. .name = "avr32_ap7k",
  476. .poll = avr32_ap7k_poll,
  477. .arch_state = avr32_ap7k_arch_state,
  478. .target_request_data = NULL,
  479. .halt = avr32_ap7k_halt,
  480. .resume = avr32_ap7k_resume,
  481. .step = avr32_ap7k_step,
  482. .assert_reset = avr32_ap7k_assert_reset,
  483. .deassert_reset = avr32_ap7k_deassert_reset,
  484. .soft_reset_halt = avr32_ap7k_soft_reset_halt,
  485. .get_gdb_reg_list = avr32_ap7k_get_gdb_reg_list,
  486. .read_memory = avr32_ap7k_read_memory,
  487. .write_memory = avr32_ap7k_write_memory,
  488. /* .checksum_memory = avr32_ap7k_checksum_memory, */
  489. /* .blank_check_memory = avr32_ap7k_blank_check_memory, */
  490. /* .run_algorithm = avr32_ap7k_run_algorithm, */
  491. .add_breakpoint = avr32_ap7k_add_breakpoint,
  492. .remove_breakpoint = avr32_ap7k_remove_breakpoint,
  493. .add_watchpoint = avr32_ap7k_add_watchpoint,
  494. .remove_watchpoint = avr32_ap7k_remove_watchpoint,
  495. .target_create = avr32_ap7k_target_create,
  496. .init_target = avr32_ap7k_init_target,
  497. .examine = avr32_ap7k_examine,
  498. };