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openocd/src/target/board/imx31pdk.cfg

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  1. # The IMX31PDK eval board has a single IMX31 chip

  2. source [find target/imx31.cfg]

  3. $_TARGETNAME configure -event gdb-attach { reset init }

  4. $_TARGETNAME configure -event reset-init { imx31pdk_init }

  5. 

  6. proc imx31pdk_init { } {

  7. 	# This setup puts RAM at 0x80000000

  8. 

  9. 	# reset the board correctly

  10. 	reset run

  11. 	reset halt

  12. 

  13. 	# ========================================

  14. 	# Init CCM

  15. 	# ========================================

  16. 	mww 0x53FC0000 0x040

  17. 	mww 0x53F80000 0x074B0B7D

  18. 

  19. 	sleep 100

  20. 

  21. 	# ========================================

  22. 	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40

  23. 	# ========================================

  24. 	mww 0x53F80004 0xFF871D50

  25. 	mww 0x53F80010 0x00271C1B

  26. 

  27. 	# ========================================

  28. 	# Configure CPLD on CS5 

  29. 	# ========================================

  30. 	mww 0xb8002050 0x0000DCF6

  31. 	mww 0xb8002054 0x444A4541

  32. 	mww 0xb8002058 0x44443302

  33. 

  34. 	# ========================================

  35. 	# SDCLK

  36. 	# ========================================

  37. 	mww 0x43FAC26C 0

  38. 

  39. 	# ========================================

  40. 	# CAS

  41. 	# ========================================

  42. 	mww 0x43FAC270 0

  43. 

  44. 	# ========================================

  45. 	# RAS

  46. 	# ========================================

  47. 	mww 0x43FAC274 0

  48. 

  49. 	# ========================================

  50. 	# CS2 (CSD0)

  51. 	# ========================================

  52. 	mww 0x43FAC27C 0x1000

  53. 

  54. 	# ========================================

  55. 	# DQM3

  56. 	# ========================================

  57. 	mww 0x43FAC284 0

  58. 

  59. 	# ========================================

  60. 	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)

  61. 	# ========================================

  62. 	mww 0x43FAC288 0

  63. 	mww 0x43FAC28C 0

  64. 	mww 0x43FAC290 0

  65. 	mww 0x43FAC294 0

  66. 	mww 0x43FAC298 0

  67. 	mww 0x43FAC29C 0

  68. 	mww 0x43FAC2A0 0

  69. 	mww 0x43FAC2A4 0

  70. 	mww 0x43FAC2A8 0

  71. 	mww 0x43FAC2AC 0

  72. 	mww 0x43FAC2B0 0

  73. 	mww 0x43FAC2B4 0

  74. 	mww 0x43FAC2B8 0

  75. 	mww 0x43FAC2BC 0

  76. 	mww 0x43FAC2C0 0

  77. 	mww 0x43FAC2C4 0

  78. 	mww 0x43FAC2C8 0

  79. 	mww 0x43FAC2CC 0

  80. 	mww 0x43FAC2D0 0

  81. 	mww 0x43FAC2D4 0

  82. 	mww 0x43FAC2D8 0

  83. 	mww 0x43FAC2DC 0

  84. 

  85. 	# ========================================

  86. 	# Initialization script for 32 bit DDR on MX31 PDK

  87. 	# ========================================

  88. 	mww 0xB8001010 0x00000004

  89. 	mww 0xB8001004 0x006ac73a

  90. 	mww 0xB8001000 0x92100000

  91. 	mww 0x80000f00 0x12344321

  92. 	mww 0xB8001000 0xa2100000

  93. 	mww 0x80000000 0x12344321

  94. 	mww 0x80000000 0x12344321

  95. 	mww 0xB8001000 0xb2100000

  96. 	mwb 0x80000033 0xda

  97. 	mwb 0x81000000 0xff

  98. 	mww 0xB8001000 0x82226080

  99. 	mww 0x80000000 0xDEADBEEF

  100. 	mww 0xB8001010 0x0000000c

  101. }