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  1. #
  2. # Utility code for DaVinci-family chips
  3. #
  4. # davinci_pinmux: assigns PINMUX$reg <== $value
  5. proc davinci_pinmux {soc reg value} {
  6. mww [expr [dict get $soc sysbase] + 4 * $reg] $value
  7. }
  8. # mrw: "memory read word", returns value of $reg
  9. proc mrw {reg} {
  10. set value ""
  11. ocd_mem2array value 32 $reg 1
  12. return $value(0)
  13. }
  14. # mmw: "memory modify word", updates value of $reg
  15. # $reg <== ((value & ~$clearbits) | $setbits)
  16. proc mmw {reg setbits clearbits} {
  17. set old [mrw $reg]
  18. set new [expr ($old & ~$clearbits) | $setbits]
  19. mww $reg $new
  20. }
  21. #
  22. # pll_setup: initialize PLL
  23. # - pll_addr ... physical addr of controller
  24. # - mult ... pll multiplier
  25. # - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
  26. #
  27. # For PLLs that don't have a given register (e.g. plldiv8), or where a
  28. # given divider is non-programmable, caller provides *NO* config mapping.
  29. #
  30. # PLL version 0x02: tested on dm355
  31. # REVISIT: On dm6446/dm357 the PLLRST polarity is different.
  32. proc pll_v02_setup {pll_addr mult config} {
  33. set pll_ctrl_addr [expr $pll_addr + 0x100]
  34. set pll_ctrl [mrw $pll_ctrl_addr]
  35. # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
  36. # NOTE: this assumes we should clear that bit
  37. set pll_ctrl [expr $pll_ctrl & ~0x0100]
  38. mww $pll_ctrl_addr $pll_ctrl
  39. # 2 - clear PLLENSRC (bit 5)
  40. set pll_ctrl [expr $pll_ctrl & ~0x0020]
  41. mww $pll_ctrl_addr $pll_ctrl
  42. # 3 - clear PLLEN (bit 0) ... enter bypass mode
  43. set pll_ctrl [expr $pll_ctrl & ~0x0001]
  44. mww $pll_ctrl_addr $pll_ctrl
  45. # 4 - wait at least 4 refclk cycles
  46. sleep 1
  47. # 5 - set PLLRST (bit 3)
  48. set pll_ctrl [expr $pll_ctrl | 0x0008]
  49. mww $pll_ctrl_addr $pll_ctrl
  50. # 6 - set PLLDIS (bit 4)
  51. set pll_ctrl [expr $pll_ctrl | 0x0010]
  52. mww $pll_ctrl_addr $pll_ctrl
  53. # 7 - clear PLLPWRDN (bit 1)
  54. set pll_ctrl [expr $pll_ctrl & ~0x0002]
  55. mww $pll_ctrl_addr $pll_ctrl
  56. # 8 - clear PLLDIS (bit 4)
  57. set pll_ctrl [expr $pll_ctrl & ~0x0010]
  58. mww $pll_ctrl_addr $pll_ctrl
  59. # 9 - optional: write prediv, postdiv, and pllm
  60. # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
  61. mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
  62. if { [dict exists $config prediv] } {
  63. set div [dict get $config prediv]
  64. set div [expr 0x8000 | ($div - 1)]
  65. mww [expr $pll_addr + 0x0114] $div
  66. }
  67. if { [dict exists $config postdiv] } {
  68. set div [dict get $config postdiv]
  69. set div [expr 0x8000 | ($div - 1)]
  70. mww [expr $pll_addr + 0x0128] $div
  71. }
  72. # 10 - optional: set plldiv1, plldiv2, ...
  73. # NOTE: this assumes some registers have their just-reset values:
  74. # - PLLSTAT.GOSTAT is clear when we enter
  75. # - ALNCTL has everything set
  76. set go 0
  77. if { [dict exists $config div1] } {
  78. set div [dict get $config div1]
  79. set div [expr 0x8000 | ($div - 1)]
  80. mww [expr $pll_addr + 0x0118] $div
  81. set go 1
  82. }
  83. if { [dict exists $config div2] } {
  84. set div [dict get $config div2]
  85. set div [expr 0x8000 | ($div - 1)]
  86. mww [expr $pll_addr + 0x011c] $div
  87. set go 1
  88. }
  89. if { [dict exists $config div3] } {
  90. set div [dict get $config div3]
  91. set div [expr 0x8000 | ($div - 1)]
  92. mww [expr $pll_addr + 0x0120] $div
  93. set go 1
  94. }
  95. if { [dict exists $config div4] } {
  96. set div [dict get $config div4]
  97. set div [expr 0x8000 | ($div - 1)]
  98. mww [expr $pll_addr + 0x0160] $div
  99. set go 1
  100. }
  101. if { [dict exists $config div5] } {
  102. set div [dict get $config div5]
  103. set div [expr 0x8000 | ($div - 1)]
  104. mww [expr $pll_addr + 0x0164] $div
  105. set go 1
  106. }
  107. if {$go != 0} {
  108. # write pllcmd.GO; poll pllstat.GO
  109. mww [expr $pll_addr + 0x0138] 0x01
  110. set pllstat [expr $pll_addr + 0x013c]
  111. while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
  112. }
  113. mww [expr $pll_addr + 0x0138] 0x00
  114. # 11 - wait at least 5 usec for reset to finish
  115. # (assume covered by overheads including JTAG messaging)
  116. # 12 - clear PLLRST (bit 3)
  117. set pll_ctrl [expr $pll_ctrl & ~0x0008]
  118. mww $pll_ctrl_addr $pll_ctrl
  119. # 13 - wait at least 8000 refclk cycles for PLL to lock
  120. # if we assume 24 MHz (slowest osc), that's 1/3 msec
  121. sleep 3
  122. # 14 - set PLLEN (bit 0) ... leave bypass mode
  123. set pll_ctrl [expr $pll_ctrl | 0x0001]
  124. mww $pll_ctrl_addr $pll_ctrl
  125. }
  126. # NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
  127. # modules can be enabled.
  128. # prepare a non-DSP module to be enabled; finish with psc_go
  129. proc psc_enable {module} {
  130. set psc_addr 0x01c41000
  131. # write MDCTL
  132. mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
  133. }
  134. # prepare a non-DSP module to be reset; finish with psc_go
  135. proc psc_reset {module} {
  136. set psc_addr 0x01c41000
  137. # write MDCTL
  138. mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
  139. }
  140. # execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
  141. proc psc_go {} {
  142. set psc_addr 0x01c41000
  143. set ptstat_addr [expr $psc_addr + 0x0128]
  144. # just in case PTSTAT.go isn't clear
  145. while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
  146. # write PTCMD.go ... ignoring any DSP power domain
  147. mww [expr $psc_addr + 0x0120] 1
  148. # wait for PTSTAT.go to clear (again ignoring DSP power domain)
  149. while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
  150. }
  151. #
  152. # A reset using only SRST is a "Warm Reset", resetting everything in the
  153. # chip except ARM emulation (and everything _outside_ the chip that hooks
  154. # up to SRST). But many boards don't expose SRST via their JTAG connectors
  155. # (it's not present on TI-14 headers).
  156. #
  157. # From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
  158. # without any board-wide side effects, since it's triggered using JTAG using
  159. # either (a) ARM watchdog timer, or (b) ICEpick.
  160. #
  161. proc davinci_wdog_reset {} {
  162. set timer2_phys 0x01c21c00
  163. # NOTE -- on entry
  164. # - JTAG communication with the ARM *must* be working OK; this
  165. # may imply using adaptive clocking or disabling WFI-in-idle
  166. # - current target must be the DaVinci ARM
  167. # - that ARM core must be halted
  168. # - timer2 clock is still enabled (PSC 29 on most chips)
  169. #
  170. # Part I -- run regardless of being halted via JTAG
  171. #
  172. # NOTE: for now, we assume there's no DSP that could control the
  173. # watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
  174. # suspend signal is controlled via ARM emulation suspend.
  175. #
  176. # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
  177. mww phys [expr $timer2_phys + 0x28] 0x00004000
  178. #
  179. # Part II -- in case watchdog hasn't been set up
  180. #
  181. # TCR: disable, force internal clock source
  182. mww phys [expr $timer2_phys + 0x20] 0
  183. # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
  184. mww phys [expr $timer2_phys + 0x24] 0
  185. mww phys [expr $timer2_phys + 0x24] 0x110b
  186. # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
  187. # so watchdog triggers ASAP
  188. mww phys [expr $timer2_phys + 0x10] 0
  189. mww phys [expr $timer2_phys + 0x14] 0
  190. mww phys [expr $timer2_phys + 0x18] 0
  191. mww phys [expr $timer2_phys + 0x1c] 0
  192. # WDTCR: put into pre-active state, then active
  193. mww phys [expr $timer2_phys + 0x28] 0xa5c64000
  194. mww phys [expr $timer2_phys + 0x28] 0xda7e4000
  195. #
  196. # Part III -- it's ready to rumble
  197. #
  198. # WDTCR: write invalid WDKEY to trigger reset
  199. mww phys [expr $timer2_phys + 0x28] 0x00004000
  200. }