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- #
- # Utility code for DaVinci-family chips
- #
-
- # davinci_pinmux: assigns PINMUX$reg <== $value
- proc davinci_pinmux {soc reg value} {
- mww [expr [dict get $soc sysbase] + 4 * $reg] $value
- }
-
- # mrw: "memory read word", returns value of $reg
- proc mrw {reg} {
- set value ""
- ocd_mem2array value 32 $reg 1
- return $value(0)
- }
-
- # mmw: "memory modify word", updates value of $reg
- # $reg <== ((value & ~$clearbits) | $setbits)
- proc mmw {reg setbits clearbits} {
- set old [mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww $reg $new
- }
-
- #
- # pll_setup: initialize PLL
- # - pll_addr ... physical addr of controller
- # - mult ... pll multiplier
- # - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
- #
- # For PLLs that don't have a given register (e.g. plldiv8), or where a
- # given divider is non-programmable, caller provides *NO* config mapping.
- #
-
- # PLL version 0x02: tested on dm355
- # REVISIT: On dm6446/dm357 the PLLRST polarity is different.
- proc pll_v02_setup {pll_addr mult config} {
- set pll_ctrl_addr [expr $pll_addr + 0x100]
- set pll_ctrl [mrw $pll_ctrl_addr]
-
- # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
- # NOTE: this assumes we should clear that bit
- set pll_ctrl [expr $pll_ctrl & ~0x0100]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 2 - clear PLLENSRC (bit 5)
- set pll_ctrl [expr $pll_ctrl & ~0x0020]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 3 - clear PLLEN (bit 0) ... enter bypass mode
- set pll_ctrl [expr $pll_ctrl & ~0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 4 - wait at least 4 refclk cycles
- sleep 1
-
- # 5 - set PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl | 0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 6 - set PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl | 0x0010]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 7 - clear PLLPWRDN (bit 1)
- set pll_ctrl [expr $pll_ctrl & ~0x0002]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 8 - clear PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl & ~0x0010]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 9 - optional: write prediv, postdiv, and pllm
- # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
- mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
- if { [dict exists $config prediv] } {
- set div [dict get $config prediv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0114] $div
- }
- if { [dict exists $config postdiv] } {
- set div [dict get $config postdiv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0128] $div
- }
-
- # 10 - optional: set plldiv1, plldiv2, ...
- # NOTE: this assumes some registers have their just-reset values:
- # - PLLSTAT.GOSTAT is clear when we enter
- # - ALNCTL has everything set
- set go 0
- if { [dict exists $config div1] } {
- set div [dict get $config div1]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0118] $div
- set go 1
- }
- if { [dict exists $config div2] } {
- set div [dict get $config div2]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x011c] $div
- set go 1
- }
- if { [dict exists $config div3] } {
- set div [dict get $config div3]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0120] $div
- set go 1
- }
- if { [dict exists $config div4] } {
- set div [dict get $config div4]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0160] $div
- set go 1
- }
- if { [dict exists $config div5] } {
- set div [dict get $config div5]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0164] $div
- set go 1
- }
- if {$go != 0} {
- # write pllcmd.GO; poll pllstat.GO
- mww [expr $pll_addr + 0x0138] 0x01
- set pllstat [expr $pll_addr + 0x013c]
- while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
- }
- mww [expr $pll_addr + 0x0138] 0x00
-
- # 11 - wait at least 5 usec for reset to finish
- # (assume covered by overheads including JTAG messaging)
-
- # 12 - clear PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl & ~0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 13 - wait at least 8000 refclk cycles for PLL to lock
- # if we assume 24 MHz (slowest osc), that's 1/3 msec
- sleep 3
-
- # 14 - set PLLEN (bit 0) ... leave bypass mode
- set pll_ctrl [expr $pll_ctrl | 0x0001]
- mww $pll_ctrl_addr $pll_ctrl
- }
-
- # NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
- # modules can be enabled.
-
- # prepare a non-DSP module to be enabled; finish with psc_go
- proc psc_enable {module} {
- set psc_addr 0x01c41000
- # write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
- }
-
- # prepare a non-DSP module to be reset; finish with psc_go
- proc psc_reset {module} {
- set psc_addr 0x01c41000
- # write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
- }
-
- # execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
- proc psc_go {} {
- set psc_addr 0x01c41000
- set ptstat_addr [expr $psc_addr + 0x0128]
-
- # just in case PTSTAT.go isn't clear
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
-
- # write PTCMD.go ... ignoring any DSP power domain
- mww [expr $psc_addr + 0x0120] 1
-
- # wait for PTSTAT.go to clear (again ignoring DSP power domain)
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
- }
-
- #
- # A reset using only SRST is a "Warm Reset", resetting everything in the
- # chip except ARM emulation (and everything _outside_ the chip that hooks
- # up to SRST). But many boards don't expose SRST via their JTAG connectors
- # (it's not present on TI-14 headers).
- #
- # From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
- # without any board-wide side effects, since it's triggered using JTAG using
- # either (a) ARM watchdog timer, or (b) ICEpick.
- #
- proc davinci_wdog_reset {} {
- set timer2_phys 0x01c21c00
-
- # NOTE -- on entry
- # - JTAG communication with the ARM *must* be working OK; this
- # may imply using adaptive clocking or disabling WFI-in-idle
- # - current target must be the DaVinci ARM
- # - that ARM core must be halted
- # - timer2 clock is still enabled (PSC 29 on most chips)
-
- #
- # Part I -- run regardless of being halted via JTAG
- #
- # NOTE: for now, we assume there's no DSP that could control the
- # watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
- # suspend signal is controlled via ARM emulation suspend.
- #
-
- # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
- mww phys [expr $timer2_phys + 0x28] 0x00004000
-
- #
- # Part II -- in case watchdog hasn't been set up
- #
-
- # TCR: disable, force internal clock source
- mww phys [expr $timer2_phys + 0x20] 0
-
- # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
- mww phys [expr $timer2_phys + 0x24] 0
- mww phys [expr $timer2_phys + 0x24] 0x110b
-
- # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
- # so watchdog triggers ASAP
- mww phys [expr $timer2_phys + 0x10] 0
- mww phys [expr $timer2_phys + 0x14] 0
- mww phys [expr $timer2_phys + 0x18] 0
- mww phys [expr $timer2_phys + 0x1c] 0
-
- # WDTCR: put into pre-active state, then active
- mww phys [expr $timer2_phys + 0x28] 0xa5c64000
- mww phys [expr $timer2_phys + 0x28] 0xda7e4000
-
- #
- # Part III -- it's ready to rumble
- #
-
- # WDTCR: write invalid WDKEY to trigger reset
- mww phys [expr $timer2_phys + 0x28] 0x00004000
- }
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