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  1. /*
  2. * Copyright (C) 2005 by Dominic Rath
  3. * Dominic.Rath@gmx.de
  4. *
  5. * Copyright (C) 2008 by Spencer Oliver
  6. * spen@spen-soft.co.uk
  7. *
  8. * Copyright (C) 2009 by Øyvind Harboe
  9. * oyvind.harboe@zylin.com
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the
  23. * Free Software Foundation, Inc.,
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  25. */
  26. #ifndef ARM_H
  27. #define ARM_H
  28. #include <helper/command.h>
  29. #include "target.h"
  30. /**
  31. * @file
  32. * Holds the interface to ARM cores.
  33. *
  34. * At this writing, only "classic ARM" cores built on the ARMv4 register
  35. * and mode model are supported. The Thumb2-only microcontroller profile
  36. * support has not yet been integrated, affecting Cortex-M parts.
  37. */
  38. /**
  39. * Represent state of an ARM core.
  40. *
  41. * Most numbers match the five low bits of the *PSR registers on
  42. * "classic ARM" processors, which build on the ARMv4 processor
  43. * modes and register set.
  44. *
  45. * ARM_MODE_ANY is a magic value, often used as a wildcard.
  46. *
  47. * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  48. * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
  49. * they support.
  50. */
  51. enum arm_mode {
  52. ARM_MODE_USR = 16,
  53. ARM_MODE_FIQ = 17,
  54. ARM_MODE_IRQ = 18,
  55. ARM_MODE_SVC = 19,
  56. ARM_MODE_ABT = 23,
  57. ARM_MODE_MON = 26,
  58. ARM_MODE_UND = 27,
  59. ARM_MODE_SYS = 31,
  60. ARM_MODE_THREAD,
  61. ARM_MODE_USER_THREAD,
  62. ARM_MODE_HANDLER,
  63. ARM_MODE_ANY = -1
  64. };
  65. const char *arm_mode_name(unsigned psr_mode);
  66. bool is_arm_mode(unsigned psr_mode);
  67. /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  68. enum arm_state {
  69. ARM_STATE_ARM,
  70. ARM_STATE_THUMB,
  71. ARM_STATE_JAZELLE,
  72. ARM_STATE_THUMB_EE,
  73. };
  74. #define ARM_COMMON_MAGIC 0x0A450A45
  75. /**
  76. * Represents a generic ARM core, with standard application registers.
  77. *
  78. * There are sixteen application registers (including PC, SP, LR) and a PSR.
  79. * Cortex-M series cores do not support as many core states or shadowed
  80. * registers as traditional ARM cores, and only support Thumb2 instructions.
  81. */
  82. struct arm {
  83. int common_magic;
  84. struct reg_cache *core_cache;
  85. /** Handle to the PC; valid in all core modes. */
  86. struct reg *pc;
  87. /** Handle to the CPSR; valid in all core modes. */
  88. struct reg *cpsr;
  89. /** Handle to the SPSR; valid only in core modes with an SPSR. */
  90. struct reg *spsr;
  91. /** Support for arm_reg_current() */
  92. const int *map;
  93. /**
  94. * Indicates what registers are in the ARM state core register set.
  95. * ARM_MODE_ANY indicates the standard set of 37 registers,
  96. * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
  97. * more registers are shadowed, for "Secure Monitor" mode.
  98. * ARM_MODE_THREAD indicates a microcontroller profile core,
  99. * which only shadows SP.
  100. */
  101. enum arm_mode core_type;
  102. /** Record the current core mode: SVC, USR, or some other mode. */
  103. enum arm_mode core_mode;
  104. /** Record the current core state: ARM, Thumb, or otherwise. */
  105. enum arm_state core_state;
  106. /** Flag reporting unavailability of the BKPT instruction. */
  107. bool is_armv4;
  108. /** Flag reporting armv6m based core. */
  109. bool is_armv6m;
  110. /** Flag reporting whether semihosting is active. */
  111. bool is_semihosting;
  112. /** Value to be returned by semihosting SYS_ERRNO request. */
  113. int semihosting_errno;
  114. int (*setup_semihosting)(struct target *target, int enable);
  115. /** Backpointer to the target. */
  116. struct target *target;
  117. /** Handle for the debug module, if one is present. */
  118. struct arm_dpm *dpm;
  119. /** Handle for the Embedded Trace Module, if one is present. */
  120. struct etm_context *etm;
  121. /* FIXME all these methods should take "struct arm *" not target */
  122. /** Retrieve all core registers, for display. */
  123. int (*full_context)(struct target *target);
  124. /** Retrieve a single core register. */
  125. int (*read_core_reg)(struct target *target, struct reg *reg,
  126. int num, enum arm_mode mode);
  127. int (*write_core_reg)(struct target *target, struct reg *reg,
  128. int num, enum arm_mode mode, uint32_t value);
  129. /** Read coprocessor register. */
  130. int (*mrc)(struct target *target, int cpnum,
  131. uint32_t op1, uint32_t op2,
  132. uint32_t CRn, uint32_t CRm,
  133. uint32_t *value);
  134. /** Write coprocessor register. */
  135. int (*mcr)(struct target *target, int cpnum,
  136. uint32_t op1, uint32_t op2,
  137. uint32_t CRn, uint32_t CRm,
  138. uint32_t value);
  139. void *arch_info;
  140. /** For targets conforming to ARM Debug Interface v5,
  141. * this handle references the Debug Access Port (DAP)
  142. * used to make requests to the target.
  143. */
  144. struct adiv5_dap *dap;
  145. };
  146. /** Convert target handle to generic ARM target state handle. */
  147. static inline struct arm *target_to_arm(struct target *target)
  148. {
  149. assert(target != NULL);
  150. return target->arch_info;
  151. }
  152. static inline bool is_arm(struct arm *arm)
  153. {
  154. assert(arm != NULL);
  155. return arm->common_magic == ARM_COMMON_MAGIC;
  156. }
  157. struct arm_algorithm {
  158. int common_magic;
  159. enum arm_mode core_mode;
  160. enum arm_state core_state;
  161. };
  162. struct arm_reg {
  163. int num;
  164. enum arm_mode mode;
  165. struct target *target;
  166. struct arm *arm;
  167. uint32_t value;
  168. };
  169. struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
  170. extern const struct command_registration arm_command_handlers[];
  171. int arm_arch_state(struct target *target);
  172. int arm_get_gdb_reg_list(struct target *target,
  173. struct reg **reg_list[], int *reg_list_size);
  174. int arm_init_arch_info(struct target *target, struct arm *arm);
  175. /* REVISIT rename this once it's usable by ARMv7-M */
  176. int armv4_5_run_algorithm(struct target *target,
  177. int num_mem_params, struct mem_param *mem_params,
  178. int num_reg_params, struct reg_param *reg_params,
  179. uint32_t entry_point, uint32_t exit_point,
  180. int timeout_ms, void *arch_info);
  181. int armv4_5_run_algorithm_inner(struct target *target,
  182. int num_mem_params, struct mem_param *mem_params,
  183. int num_reg_params, struct reg_param *reg_params,
  184. uint32_t entry_point, uint32_t exit_point,
  185. int timeout_ms, void *arch_info,
  186. int (*run_it)(struct target *target, uint32_t exit_point,
  187. int timeout_ms, void *arch_info));
  188. int arm_checksum_memory(struct target *target,
  189. uint32_t address, uint32_t count, uint32_t *checksum);
  190. int arm_blank_check_memory(struct target *target,
  191. uint32_t address, uint32_t count, uint32_t *blank);
  192. void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
  193. struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
  194. void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
  195. extern struct reg arm_gdb_dummy_fp_reg;
  196. extern struct reg arm_gdb_dummy_fps_reg;
  197. #endif /* ARM_H */