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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developers
  53. * JTAG Hardware Dongles:: JTAG Hardware Dongles
  54. * About JIM-Tcl:: About JIM-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Interface - Dongle Configuration:: Interface - Dongle Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * NAND Flash Commands:: NAND Flash Commands
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * TFTP:: TFTP
  71. * GDB and OpenOCD:: Using GDB and OpenOCD
  72. * Tcl Scripting API:: Tcl Scripting API
  73. * FAQ:: Frequently Asked Questions
  74. * Tcl Crash Course:: Tcl Crash Course
  75. * License:: GNU Free Documentation License
  76. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  77. @comment case issue with ``Index.html'' and ``index.html''
  78. @comment Occurs when creating ``--html --no-split'' output
  79. @comment This fix is based on:
  80. * OpenOCD Concept Index:: Concept Index
  81. * Command and Driver Index:: Command and Driver Index
  82. @end menu
  83. @node About
  84. @unnumbered About
  85. @cindex about
  86. OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
  87. University of Applied Sciences Augsburg (@uref{}).
  88. Since that time, the project has grown into an active open-source project,
  89. supported by a diverse community of software and hardware developers from
  90. around the world.
  91. @section What is OpenOCD?
  92. @cindex TAP
  93. @cindex JTAG
  94. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  95. in-system programming and boundary-scan testing for embedded target
  96. devices.
  97. @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
  98. with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
  99. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  100. special instructions and data. TAPs are daisy-chained within and
  101. between chips and boards.
  102. @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
  103. based, parallel port based, and other standalone boxes that run
  104. OpenOCD internally. @xref{JTAG Hardware Dongles}.
  105. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  106. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
  107. Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
  108. debugged via the GDB protocol.
  109. @b{Flash Programing:} Flash writing is supported for external CFI
  110. compatible NOR flashes (Intel and AMD/Spansion command set) and several
  111. internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
  112. STM32x). Preliminary support for various NAND flash controllers
  113. (LPC3180, Orion, S3C24xx, more) controller is included.
  114. @section OpenOCD Web Site
  115. The OpenOCD web site provides the latest public news from the community:
  116. @uref{}
  117. @section Latest User's Guide:
  118. The user's guide you are now reading may not be the latest one
  119. available. A version for more recent code may be available.
  120. Its HTML form is published irregularly at:
  121. @uref{}
  122. PDF form is likewise published at:
  123. @uref{}
  124. @section OpenOCD User's Forum
  125. There is an OpenOCD forum (phpBB) hosted by SparkFun:
  126. @uref{}
  127. @node Developers
  128. @chapter OpenOCD Developer Resources
  129. @cindex developers
  130. If you are interested in improving the state of OpenOCD's debugging and
  131. testing support, new contributions will be welcome. Motivated developers
  132. can produce new target, flash or interface drivers, improve the
  133. documentation, as well as more conventional bug fixes and enhancements.
  134. The resources in this chapter are available for developers wishing to explore
  135. or expand the OpenOCD source code.
  136. @section OpenOCD GIT Repository
  137. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  138. a GIT repository hosted at SourceForge. The repository URL is:
  139. @uref{git://}
  140. You may prefer to use a mirror and the HTTP protocol:
  141. @uref{}
  142. With standard GIT tools, use @command{git clone} to initialize
  143. a local repository, and @command{git pull} to update it.
  144. There are also gitweb pages letting you browse the repository
  145. with a web browser, or download arbitrary snapshots without
  146. needing a GIT client:
  147. @uref{}
  148. @uref{}
  149. The @file{README} file contains the instructions for building the project
  150. from the repository or a snapshot.
  151. Developers that want to contribute patches to the OpenOCD system are
  152. @b{strongly} encouraged to work against mainline.
  153. Patches created against older versions may require additional
  154. work from their submitter in order to be updated for newer releases.
  155. @section Doxygen Developer Manual
  156. During the 0.2.x release cycle, the OpenOCD project began
  157. providing a Doxygen reference manual. This document contains more
  158. technical information about the software internals, development
  159. processes, and similar documentation:
  160. @uref{}
  161. This document is a work-in-progress, but contributions would be welcome
  162. to fill in the gaps. All of the source files are provided in-tree,
  163. listed in the Doxyfile configuration in the top of the source tree.
  164. @section OpenOCD Developer Mailing List
  165. The OpenOCD Developer Mailing List provides the primary means of
  166. communication between developers:
  167. @uref{}
  168. Discuss and submit patches to this list.
  169. The @file{PATCHES} file contains basic information about how
  170. to prepare patches.
  171. @node JTAG Hardware Dongles
  172. @chapter JTAG Hardware Dongles
  173. @cindex dongles
  174. @cindex FTDI
  175. @cindex wiggler
  176. @cindex zy1000
  177. @cindex printer port
  178. @cindex USB Adapter
  179. @cindex RTCK
  180. Defined: @b{dongle}: A small device that plugins into a computer and serves as
  181. an adapter .... [snip]
  182. In the OpenOCD case, this generally refers to @b{a small adapater} one
  183. attaches to your computer via USB or the Parallel Printer Port. The
  184. execption being the Zylin ZY1000 which is a small box you attach via
  185. an ethernet cable. The Zylin ZY1000 has the advantage that it does not
  186. require any drivers to be installed on the developer PC. It also has
  187. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  188. and has a built in relay to power cycle targets remotely.
  189. @section Choosing a Dongle
  190. There are several things you should keep in mind when choosing a dongle.
  191. @enumerate
  192. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  193. Does your dongle support it? You might need a level converter.
  194. @item @b{Pinout} What pinout does your target board use?
  195. Does your dongle support it? You may be able to use jumper
  196. wires, or an "octopus" connector, to convert pinouts.
  197. @item @b{Connection} Does your computer have the USB, printer, or
  198. Ethernet port needed?
  199. @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
  200. @end enumerate
  201. @section Stand alone Systems
  202. @b{ZY1000} See: @url{} Technically, not a
  203. dongle, but a standalone box. The ZY1000 has the advantage that it does
  204. not require any drivers installed on the developer PC. It also has
  205. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  206. and has a built in relay to power cycle targets remotely.
  207. @section USB FT2232 Based
  208. There are many USB JTAG dongles on the market, many of them are based
  209. on a chip from ``Future Technology Devices International'' (FTDI)
  210. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  211. See: @url{} for more information.
  212. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  213. chips are starting to become available in JTAG adapters.
  214. @itemize @bullet
  215. @item @b{usbjtag}
  216. @* Link @url{}
  217. @item @b{jtagkey}
  218. @* See: @url{}
  219. @item @b{jtagkey2}
  220. @* See: @url{}
  221. @item @b{oocdlink}
  222. @* See: @url{} By Joern Kaipf
  223. @item @b{signalyzer}
  224. @* See: @url{}
  225. @item @b{evb_lm3s811}
  226. @* See: @url{} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
  227. @item @b{luminary_icdi}
  228. @* See: @url{} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
  229. @item @b{olimex-jtag}
  230. @* See: @url{}
  231. @item @b{flyswatter}
  232. @* See: @url{}
  233. @item @b{turtelizer2}
  234. @* See:
  235. @uref{, Turtelizer 2}, or
  236. @url{}
  237. @item @b{comstick}
  238. @* Link: @url{}
  239. @item @b{stm32stick}
  240. @* Link @url{}
  241. @item @b{axm0432_jtag}
  242. @* Axiom AXM-0432 Link @url{}
  243. @item @b{cortino}
  244. @* Link @url{}
  245. @end itemize
  246. @section USB JLINK based
  247. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  248. an example of a micro controller based JTAG adapter, it uses an
  249. AT91SAM764 internally.
  250. @itemize @bullet
  251. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  252. @* Link: @url{}
  253. @item @b{SEGGER JLINK}
  254. @* Link: @url{}
  255. @item @b{IAR J-Link}
  256. @* Link: @url{}
  257. @end itemize
  258. @section USB RLINK based
  259. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
  260. @itemize @bullet
  261. @item @b{Raisonance RLink}
  262. @* Link: @url{}
  263. @item @b{STM32 Primer}
  264. @* Link: @url{}
  265. @item @b{STM32 Primer2}
  266. @* Link: @url{}
  267. @end itemize
  268. @section USB Other
  269. @itemize @bullet
  270. @item @b{USBprog}
  271. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  272. @item @b{USB - Presto}
  273. @* Link: @url{}
  274. @item @b{Versaloon-Link}
  275. @* Link: @url{}
  276. @item @b{ARM-JTAG-EW}
  277. @* Link: @url{}
  278. @end itemize
  279. @section IBM PC Parallel Printer Port Based
  280. The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
  281. and the MacGraigor Wiggler. There are many clones and variations of
  282. these on the market.
  283. Note that parallel ports are becoming much less common, so if you
  284. have the choice you should probably avoid these adapters in favor
  285. of USB-based ones.
  286. @itemize @bullet
  287. @item @b{Wiggler} - There are many clones of this.
  288. @* Link: @url{}
  289. @item @b{DLC5} - From XILINX - There are many clones of this
  290. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  291. produced, PDF schematics are easily found and it is easy to make.
  292. @item @b{Amontec - JTAG Accelerator}
  293. @* Link: @url{}
  294. @item @b{GW16402}
  295. @* Link: @url{}
  296. @item @b{Wiggler2}
  297. @*@uref{,
  298. Improved parallel-port wiggler-style JTAG adapter}
  299. @item @b{Wiggler_ntrst_inverted}
  300. @* Yet another variation - See the source code, src/jtag/parport.c
  301. @item @b{old_amt_wiggler}
  302. @* Unknown - probably not on the market today
  303. @item @b{arm-jtag}
  304. @* Link: Most likely @url{} [another wiggler clone]
  305. @item @b{chameleon}
  306. @* Link: @url{}
  307. @item @b{Triton}
  308. @* Unknown.
  309. @item @b{Lattice}
  310. @* ispDownload from Lattice Semiconductor
  311. @url{}
  312. @item @b{flashlink}
  313. @* From ST Microsystems;
  314. @uref{,
  315. FlashLINK JTAG programing cable for PSD and uPSD}
  316. @end itemize
  317. @section Other...
  318. @itemize @bullet
  319. @item @b{ep93xx}
  320. @* An EP93xx based Linux machine using the GPIO pins directly.
  321. @item @b{at91rm9200}
  322. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  323. @end itemize
  324. @node About JIM-Tcl
  325. @chapter About JIM-Tcl
  326. @cindex JIM Tcl
  327. @cindex tcl
  328. OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
  329. This programming language provides a simple and extensible
  330. command interpreter.
  331. All commands presented in this Guide are extensions to JIM-Tcl.
  332. You can use them as simple commands, without needing to learn
  333. much of anything about Tcl.
  334. Alternatively, can write Tcl programs with them.
  335. You can learn more about JIM at its website, @url{}.
  336. @itemize @bullet
  337. @item @b{JIM vs. Tcl}
  338. @* JIM-TCL is a stripped down version of the well known Tcl language,
  339. which can be found here: @url{}. JIM-Tcl has far
  340. fewer features. JIM-Tcl is a single .C file and a single .H file and
  341. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  342. 4.2 MB .zip file containing 1540 files.
  343. @item @b{Missing Features}
  344. @* Our practice has been: Add/clone the real Tcl feature if/when
  345. needed. We welcome JIM Tcl improvements, not bloat.
  346. @item @b{Scripts}
  347. @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
  348. command interpreter today is a mixture of (newer)
  349. JIM-Tcl commands, and (older) the orginal command interpreter.
  350. @item @b{Commands}
  351. @* At the OpenOCD telnet command line (or via the GDB mon command) one
  352. can type a Tcl for() loop, set variables, etc.
  353. Some of the commands documented in this guide are implemented
  354. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  355. @item @b{Historical Note}
  356. @* JIM-Tcl was introduced to OpenOCD in spring 2008.
  357. @item @b{Need a crash course in Tcl?}
  358. @*@xref{Tcl Crash Course}.
  359. @end itemize
  360. @node Running
  361. @chapter Running
  362. @cindex command line options
  363. @cindex logfile
  364. @cindex directory search
  365. The @option{--help} option shows:
  366. @verbatim
  367. bash$ openocd --help
  368. --help | -h display this help
  369. --version | -v display OpenOCD version
  370. --file | -f use configuration file <name>
  371. --search | -s dir to search for config files and scripts
  372. --debug | -d set debug level <0-3>
  373. --log_output | -l redirect log output to file <name>
  374. --command | -c run <command>
  375. --pipe | -p use pipes when talking to gdb
  376. @end verbatim
  377. By default OpenOCD reads the configuration file @file{openocd.cfg}.
  378. To specify a different (or multiple)
  379. configuration file, you can use the @option{-f} option. For example:
  380. @example
  381. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  382. @end example
  383. Configuration files and scripts are searched for in
  384. @enumerate
  385. @item the current directory,
  386. @item any search dir specified on the command line using the @option{-s} option,
  387. @item @file{$HOME/.openocd} (not on Windows),
  388. @item the site wide script library @file{$pkgdatadir/site} and
  389. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  390. @end enumerate
  391. The first found file with a matching file name will be used.
  392. @section Simple setup, no customization
  393. In the best case, you can use two scripts from one of the script
  394. libraries, hook up your JTAG adapter, and start the server ... and
  395. your JTAG setup will just work "out of the box". Always try to
  396. start by reusing those scripts, but assume you'll need more
  397. customization even if this works. @xref{OpenOCD Project Setup}.
  398. If you find a script for your JTAG adapter, and for your board or
  399. target, you may be able to hook up your JTAG adapter then start
  400. the server like:
  401. @example
  402. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  403. @end example
  404. You might also need to configure which reset signals are present,
  405. using @option{-c 'reset_config trst_and_srst'} or something similar.
  406. If all goes well you'll see output something like
  407. @example
  408. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  409. For bug reports, read
  411. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  412. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  413. @end example
  414. Seeing that "tap/device found" message, and no warnings, means
  415. the JTAG communication is working. That's a key milestone, but
  416. you'll probably need more project-specific setup.
  417. @section What OpenOCD does as it starts
  418. OpenOCD starts by processing the configuration commands provided
  419. on the command line or, if there were no @option{-c command} or
  420. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  421. @xref{Configuration Stage}.
  422. At the end of the configuration stage it verifies the JTAG scan
  423. chain defined using those commands; your configuration should
  424. ensure that this always succeeds.
  425. Normally, OpenOCD then starts running as a daemon.
  426. Alternatively, commands may be used to terminate the configuration
  427. stage early, perform work (such as updating some flash memory),
  428. and then shut down without acting as a daemon.
  429. Once OpenOCD starts running as a daemon, it waits for connections from
  430. clients (Telnet, GDB, Other) and processes the commands issued through
  431. those channels.
  432. If you are having problems, you can enable internal debug messages via
  433. the @option{-d} option.
  434. Also it is possible to interleave JIM-Tcl commands w/config scripts using the
  435. @option{-c} command line switch.
  436. To enable debug output (when reporting problems or working on OpenOCD
  437. itself), use the @option{-d} command line switch. This sets the
  438. @option{debug_level} to "3", outputting the most information,
  439. including debug messages. The default setting is "2", outputting only
  440. informational messages, warnings and errors. You can also change this
  441. setting from within a telnet or gdb session using @command{debug_level
  442. <n>} (@pxref{debug_level}).
  443. You can redirect all output from the daemon to a file using the
  444. @option{-l <logfile>} switch.
  445. For details on the @option{-p} option. @xref{Connecting to GDB}.
  446. Note! OpenOCD will launch the GDB & telnet server even if it can not
  447. establish a connection with the target. In general, it is possible for
  448. the JTAG controller to be unresponsive until the target is set up
  449. correctly via e.g. GDB monitor commands in a GDB init script.
  450. @node OpenOCD Project Setup
  451. @chapter OpenOCD Project Setup
  452. To use OpenOCD with your development projects, you need to do more than
  453. just connecting the JTAG adapter hardware (dongle) to your development board
  454. and then starting the OpenOCD server.
  455. You also need to configure that server so that it knows
  456. about that adapter and board, and helps your work.
  457. You may also want to connect OpenOCD to GDB, possibly
  458. using Eclipse or some other GUI.
  459. @section Hooking up the JTAG Adapter
  460. Today's most common case is a dongle with a JTAG cable on one side
  461. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  462. and a USB cable on the other.
  463. Instead of USB, some cables use Ethernet;
  464. older ones may use a PC parallel port, or even a serial port.
  465. @enumerate
  466. @item @emph{Start with power to your target board turned off},
  467. and nothing connected to your JTAG adapter.
  468. If you're particularly paranoid, unplug power to the board.
  469. It's important to have the ground signal properly set up,
  470. unless you are using a JTAG adapter which provides
  471. galvanic isolation between the target board and the
  472. debugging host.
  473. @item @emph{Be sure it's the right kind of JTAG connector.}
  474. If your dongle has a 20-pin ARM connector, you need some kind
  475. of adapter (or octopus, see below) to hook it up to
  476. boards using 14-pin or 10-pin connectors ... or to 20-pin
  477. connectors which don't use ARM's pinout.
  478. In the same vein, make sure the voltage levels are compatible.
  479. Not all JTAG adapters have the level shifters needed to work
  480. with 1.2 Volt boards.
  481. @item @emph{Be certain the cable is properly oriented} or you might
  482. damage your board. In most cases there are only two possible
  483. ways to connect the cable.
  484. Connect the JTAG cable from your adapter to the board.
  485. Be sure it's firmly connected.
  486. In the best case, the connector is keyed to physically
  487. prevent you from inserting it wrong.
  488. This is most often done using a slot on the board's male connector
  489. housing, which must match a key on the JTAG cable's female connector.
  490. If there's no housing, then you must look carefully and
  491. make sure pin 1 on the cable hooks up to pin 1 on the board.
  492. Ribbon cables are frequently all grey except for a wire on one
  493. edge, which is red. The red wire is pin 1.
  494. Sometimes dongles provide cables where one end is an ``octopus'' of
  495. color coded single-wire connectors, instead of a connector block.
  496. These are great when converting from one JTAG pinout to another,
  497. but are tedious to set up.
  498. Use these with connector pinout diagrams to help you match up the
  499. adapter signals to the right board pins.
  500. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  501. A USB, parallel, or serial port connector will go to the host which
  502. you are using to run OpenOCD.
  503. For Ethernet, consult the documentation and your network administrator.
  504. For USB based JTAG adapters you have an easy sanity check at this point:
  505. does the host operating system see the JTAG adapter? If that host is an
  506. MS-Windows host, you'll need to install a driver before OpenOCD works.
  507. @item @emph{Connect the adapter's power supply, if needed.}
  508. This step is primarily for non-USB adapters,
  509. but sometimes USB adapters need extra power.
  510. @item @emph{Power up the target board.}
  511. Unless you just let the magic smoke escape,
  512. you're now ready to set up the OpenOCD server
  513. so you can use JTAG to work with that board.
  514. @end enumerate
  515. Talk with the OpenOCD server using
  516. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  517. @xref{GDB and OpenOCD}.
  518. @section Project Directory
  519. There are many ways you can configure OpenOCD and start it up.
  520. A simple way to organize them all involves keeping a
  521. single directory for your work with a given board.
  522. When you start OpenOCD from that directory,
  523. it searches there first for configuration files, scripts,
  524. files accessed through semihosting,
  525. and for code you upload to the target board.
  526. It is also the natural place to write files,
  527. such as log files and data you download from the board.
  528. @section Configuration Basics
  529. There are two basic ways of configuring OpenOCD, and
  530. a variety of ways you can mix them.
  531. Think of the difference as just being how you start the server:
  532. @itemize
  533. @item Many @option{-f file} or @option{-c command} options on the command line
  534. @item No options, but a @dfn{user config file}
  535. in the current directory named @file{openocd.cfg}
  536. @end itemize
  537. Here is an example @file{openocd.cfg} file for a setup
  538. using a Signalyzer FT2232-based JTAG adapter to talk to
  539. a board with an Atmel AT91SAM7X256 microcontroller:
  540. @example
  541. source [find interface/signalyzer.cfg]
  542. # GDB can also flash my flash!
  543. gdb_memory_map enable
  544. gdb_flash_program enable
  545. source [find target/sam7x256.cfg]
  546. @end example
  547. Here is the command line equivalent of that configuration:
  548. @example
  549. openocd -f interface/signalyzer.cfg \
  550. -c "gdb_memory_map enable" \
  551. -c "gdb_flash_program enable" \
  552. -f target/sam7x256.cfg
  553. @end example
  554. You could wrap such long command lines in shell scripts,
  555. each supporting a different development task.
  556. One might re-flash the board with a specific firmware version.
  557. Another might set up a particular debugging or run-time environment.
  558. @quotation Important
  559. At this writing (October 2009) the command line method has
  560. problems with how it treats variables.
  561. For example, after @option{-c "set VAR value"}, or doing the
  562. same in a script, the variable @var{VAR} will have no value
  563. that can be tested in a later script.
  564. @end quotation
  565. Here we will focus on the simpler solution: one user config
  566. file, including basic configuration plus any TCL procedures
  567. to simplify your work.
  568. @section User Config Files
  569. @cindex config file, user
  570. @cindex user config file
  571. @cindex config file, overview
  572. A user configuration file ties together all the parts of a project
  573. in one place.
  574. One of the following will match your situation best:
  575. @itemize
  576. @item Ideally almost everything comes from configuration files
  577. provided by someone else.
  578. For example, OpenOCD distributes a @file{scripts} directory
  579. (probably in @file{/usr/share/openocd/scripts} on Linux).
  580. Board and tool vendors can provide these too, as can individual
  581. user sites; the @option{-s} command line option lets you say
  582. where to find these files. (@xref{Running}.)
  583. The AT91SAM7X256 example above works this way.
  584. Three main types of non-user configuration file each have their
  585. own subdirectory in the @file{scripts} directory:
  586. @enumerate
  587. @item @b{interface} -- one for each kind of JTAG adapter/dongle
  588. @item @b{board} -- one for each different board
  589. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  590. @end enumerate
  591. Best case: include just two files, and they handle everything else.
  592. The first is an interface config file.
  593. The second is board-specific, and it sets up the JTAG TAPs and
  594. their GDB targets (by deferring to some @file{target.cfg} file),
  595. declares all flash memory, and leaves you nothing to do except
  596. meet your deadline:
  597. @example
  598. source [find interface/olimex-jtag-tiny.cfg]
  599. source [find board/csb337.cfg]
  600. @end example
  601. Boards with a single microcontroller often won't need more
  602. than the target config file, as in the AT91SAM7X256 example.
  603. That's because there is no external memory (flash, DDR RAM), and
  604. the board differences are encapsulated by application code.
  605. @item Maybe you don't know yet what your board looks like to JTAG.
  606. Once you know the @file{interface.cfg} file to use, you may
  607. need help from OpenOCD to discover what's on the board.
  608. Once you find the TAPs, you can just search for appropriate
  609. configuration files ... or write your own, from the bottom up.
  610. @xref{Autoprobing}.
  611. @item You can often reuse some standard config files but
  612. need to write a few new ones, probably a @file{board.cfg} file.
  613. You will be using commands described later in this User's Guide,
  614. and working with the guidelines in the next chapter.
  615. For example, there may be configuration files for your JTAG adapter
  616. and target chip, but you need a new board-specific config file
  617. giving access to your particular flash chips.
  618. Or you might need to write another target chip configuration file
  619. for a new chip built around the Cortex M3 core.
  620. @quotation Note
  621. When you write new configuration files, please submit
  622. them for inclusion in the next OpenOCD release.
  623. For example, a @file{board/newboard.cfg} file will help the
  624. next users of that board, and a @file{target/newcpu.cfg}
  625. will help support users of any board using that chip.
  626. @end quotation
  627. @item
  628. You may may need to write some C code.
  629. It may be as simple as a supporting a new ft2232 or parport
  630. based dongle; a bit more involved, like a NAND or NOR flash
  631. controller driver; or a big piece of work like supporting
  632. a new chip architecture.
  633. @end itemize
  634. Reuse the existing config files when you can.
  635. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  636. You may find a board configuration that's a good example to follow.
  637. When you write config files, separate the reusable parts
  638. (things every user of that interface, chip, or board needs)
  639. from ones specific to your environment and debugging approach.
  640. @itemize
  641. @item
  642. For example, a @code{gdb-attach} event handler that invokes
  643. the @command{reset init} command will interfere with debugging
  644. early boot code, which performs some of the same actions
  645. that the @code{reset-init} event handler does.
  646. @item
  647. Likewise, the @command{arm9 vector_catch} command (or
  648. @cindex vector_catch
  649. its siblings @command{xscale vector_catch}
  650. and @command{cortex_m3 vector_catch}) can be a timesaver
  651. during some debug sessions, but don't make everyone use that either.
  652. Keep those kinds of debugging aids in your user config file,
  653. along with messaging and tracing setup.
  654. (@xref{Software Debug Messages and Tracing}.)
  655. @item
  656. You might need to override some defaults.
  657. For example, you might need to move, shrink, or back up the target's
  658. work area if your application needs much SRAM.
  659. @item
  660. TCP/IP port configuration is another example of something which
  661. is environment-specific, and should only appear in
  662. a user config file. @xref{TCP/IP Ports}.
  663. @end itemize
  664. @section Project-Specific Utilities
  665. A few project-specific utility
  666. routines may well speed up your work.
  667. Write them, and keep them in your project's user config file.
  668. For example, if you are making a boot loader work on a
  669. board, it's nice to be able to debug the ``after it's
  670. loaded to RAM'' parts separately from the finicky early
  671. code which sets up the DDR RAM controller and clocks.
  672. A script like this one, or a more GDB-aware sibling,
  673. may help:
  674. @example
  675. proc ramboot @{ @} @{
  676. # Reset, running the target's "reset-init" scripts
  677. # to initialize clocks and the DDR RAM controller.
  678. # Leave the CPU halted.
  679. reset init
  680. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  681. load_image u-boot.bin 0x20000000
  682. # Start running.
  683. resume 0x20000000
  684. @}
  685. @end example
  686. Then once that code is working you will need to make it
  687. boot from NOR flash; a different utility would help.
  688. Alternatively, some developers write to flash using GDB.
  689. (You might use a similar script if you're working with a flash
  690. based microcontroller application instead of a boot loader.)
  691. @example
  692. proc newboot @{ @} @{
  693. # Reset, leaving the CPU halted. The "reset-init" event
  694. # proc gives faster access to the CPU and to NOR flash;
  695. # "reset halt" would be slower.
  696. reset init
  697. # Write standard version of U-Boot into the first two
  698. # sectors of NOR flash ... the standard version should
  699. # do the same lowlevel init as "reset-init".
  700. flash protect 0 0 1 off
  701. flash erase_sector 0 0 1
  702. flash write_bank 0 u-boot.bin 0x0
  703. flash protect 0 0 1 on
  704. # Reboot from scratch using that new boot loader.
  705. reset run
  706. @}
  707. @end example
  708. You may need more complicated utility procedures when booting
  709. from NAND.
  710. That often involves an extra bootloader stage,
  711. running from on-chip SRAM to perform DDR RAM setup so it can load
  712. the main bootloader code (which won't fit into that SRAM).
  713. Other helper scripts might be used to write production system images,
  714. involving considerably more than just a three stage bootloader.
  715. @section Target Software Changes
  716. Sometimes you may want to make some small changes to the software
  717. you're developing, to help make JTAG debugging work better.
  718. For example, in C or assembly language code you might
  719. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  720. handling issues like:
  721. @itemize @bullet
  722. @item @b{ARM Semihosting}...
  723. @cindex ARM semihosting
  724. When linked with a special runtime library provided with many
  725. toolchains@footnote{See chapter 8 "Semihosting" in
  726. @uref{,
  727. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  728. The CodeSourcery EABI toolchain also includes a semihosting library.},
  729. your target code can use I/O facilities on the debug host. That library
  730. provides a small set of system calls which are handled by OpenOCD.
  731. It can let the debugger provide your system console and a file system,
  732. helping with early debugging or providing a more capable environment
  733. for sometimes-complex tasks like installing system firmware onto
  734. NAND or SPI flash.
  735. @item @b{ARM Wait-For-Interrupt}...
  736. Many ARM chips synchronize the JTAG clock using the core clock.
  737. Low power states which stop that core clock thus prevent JTAG access.
  738. Idle loops in tasking environments often enter those low power states
  739. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  740. You may want to @emph{disable that instruction} in source code,
  741. or otherwise prevent using that state,
  742. to ensure you can get JTAG access at any time.
  743. For example, the OpenOCD @command{halt} command may not
  744. work for an idle processor otherwise.
  745. @item @b{Delay after reset}...
  746. Not all chips have good support for debugger access
  747. right after reset; many LPC2xxx chips have issues here.
  748. Similarly, applications that reconfigure pins used for
  749. JTAG access as they start will also block debugger access.
  750. To work with boards like this, @emph{enable a short delay loop}
  751. the first thing after reset, before "real" startup activities.
  752. For example, one second's delay is usually more than enough
  753. time for a JTAG debugger to attach, so that
  754. early code execution can be debugged
  755. or firmware can be replaced.
  756. @item @b{Debug Communications Channel (DCC)}...
  757. Some processors include mechanisms to send messages over JTAG.
  758. Many ARM cores support these, as do some cores from other vendors.
  759. (OpenOCD may be able to use this DCC internally, speeding up some
  760. operations like writing to memory.)
  761. Your application may want to deliver various debugging messages
  762. over JTAG, by @emph{linking with a small library of code}
  763. provided with OpenOCD and using the utilities there to send
  764. various kinds of message.
  765. @xref{Software Debug Messages and Tracing}.
  766. @end itemize
  767. @node Config File Guidelines
  768. @chapter Config File Guidelines
  769. This chapter is aimed at any user who needs to write a config file,
  770. including developers and integrators of OpenOCD and any user who
  771. needs to get a new board working smoothly.
  772. It provides guidelines for creating those files.
  773. You should find the following directories under @t{$(INSTALLDIR)/scripts},
  774. with files including the ones listed here.
  775. Use them as-is where you can; or as models for new files.
  776. @itemize @bullet
  777. @item @file{interface} ...
  778. think JTAG Dongle. Files that configure JTAG adapters go here.
  779. @example
  780. $ ls interface
  781. arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
  782. arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
  783. at91rm9200.cfg jlink.cfg parport.cfg
  784. axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
  785. calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
  786. calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
  787. calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
  788. chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
  789. cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
  790. dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
  791. flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
  792. $
  793. @end example
  794. @item @file{board} ...
  795. think Circuit Board, PWA, PCB, they go by many names. Board files
  796. contain initialization items that are specific to a board.
  797. They reuse target configuration files, since the same
  798. microprocessor chips are used on many boards,
  799. but support for external parts varies widely. For
  800. example, the SDRAM initialization sequence for the board, or the type
  801. of external flash and what address it uses. Any initialization
  802. sequence to enable that external flash or SDRAM should be found in the
  803. board file. Boards may also contain multiple targets: two CPUs; or
  804. a CPU and an FPGA.
  805. @example
  806. $ ls board
  807. arm_evaluator7t.cfg keil_mcb1700.cfg
  808. at91rm9200-dk.cfg keil_mcb2140.cfg
  809. at91sam9g20-ek.cfg linksys_nslu2.cfg
  810. atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
  811. atmel_at91sam9260-ek.cfg mini2440.cfg
  812. atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
  813. crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
  814. csb337.cfg olimex_sam7_ex256.cfg
  815. csb732.cfg olimex_sam9_l9260.cfg
  816. digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
  817. dm355evm.cfg omap2420_h4.cfg
  818. dm365evm.cfg osk5912.cfg
  819. dm6446evm.cfg pic-p32mx.cfg
  820. eir.cfg propox_mmnet1001.cfg
  821. ek-lm3s1968.cfg pxa255_sst.cfg
  822. ek-lm3s3748.cfg sheevaplug.cfg
  823. ek-lm3s811.cfg stm3210e_eval.cfg
  824. ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
  825. hammer.cfg str910-eval.cfg
  826. hitex_lpc2929.cfg telo.cfg
  827. hitex_stm32-performancestick.cfg ti_beagleboard.cfg
  828. hitex_str9-comstick.cfg topas910.cfg
  829. iar_str912_sk.cfg topasa900.cfg
  830. imx27ads.cfg unknown_at91sam9260.cfg
  831. imx27lnst.cfg x300t.cfg
  832. imx31pdk.cfg zy1000.cfg
  833. $
  834. @end example
  835. @item @file{target} ...
  836. think chip. The ``target'' directory represents the JTAG TAPs
  837. on a chip
  838. which OpenOCD should control, not a board. Two common types of targets
  839. are ARM chips and FPGA or CPLD chips.
  840. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  841. the target config file defines all of them.
  842. @example
  843. $ ls target
  844. aduc702x.cfg imx27.cfg pxa255.cfg
  845. ar71xx.cfg imx31.cfg pxa270.cfg
  846. at91eb40a.cfg imx35.cfg readme.txt
  847. at91r40008.cfg is5114.cfg sam7se512.cfg
  848. at91rm9200.cfg ixp42x.cfg sam7x256.cfg
  849. at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
  850. at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
  851. at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
  852. at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
  853. at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
  854. at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
  855. at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
  856. at91sam7sx.cfg lpc2124.cfg smp8634.cfg
  857. at91sam9260.cfg lpc2129.cfg stm32.cfg
  858. c100.cfg lpc2148.cfg str710.cfg
  859. c100config.tcl lpc2294.cfg str730.cfg
  860. c100helper.tcl lpc2378.cfg str750.cfg
  861. c100regs.tcl lpc2478.cfg str912.cfg
  862. cs351x.cfg lpc2900.cfg telo.cfg
  863. davinci.cfg mega128.cfg ti_dm355.cfg
  864. dragonite.cfg netx500.cfg ti_dm365.cfg
  865. epc9301.cfg omap2420.cfg ti_dm6446.cfg
  866. feroceon.cfg omap3530.cfg tmpa900.cfg
  867. icepick.cfg omap5912.cfg tmpa910.cfg
  868. imx21.cfg pic32mx.cfg xba_revA3.cfg
  869. $
  870. @end example
  871. @item @emph{more} ... browse for other library files which may be useful.
  872. For example, there are various generic and CPU-specific utilities.
  873. @end itemize
  874. The @file{openocd.cfg} user config
  875. file may override features in any of the above files by
  876. setting variables before sourcing the target file, or by adding
  877. commands specific to their situation.
  878. @section Interface Config Files
  879. The user config file
  880. should be able to source one of these files with a command like this:
  881. @example
  882. source [find interface/FOOBAR.cfg]
  883. @end example
  884. A preconfigured interface file should exist for every interface in use
  885. today, that said, perhaps some interfaces have only been used by the
  886. sole developer who created it.
  887. A separate chapter gives information about how to set these up.
  888. @xref{Interface - Dongle Configuration}.
  889. Read the OpenOCD source code if you have a new kind of hardware interface
  890. and need to provide a driver for it.
  891. @section Board Config Files
  892. @cindex config file, board
  893. @cindex board config file
  894. The user config file
  895. should be able to source one of these files with a command like this:
  896. @example
  897. source [find board/FOOBAR.cfg]
  898. @end example
  899. The point of a board config file is to package everything
  900. about a given board that user config files need to know.
  901. In summary the board files should contain (if present)
  902. @enumerate
  903. @item One or more @command{source [target/...cfg]} statements
  904. @item NOR flash configuration (@pxref{NOR Configuration})
  905. @item NAND flash configuration (@pxref{NAND Configuration})
  906. @item Target @code{reset} handlers for SDRAM and I/O configuration
  907. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  908. @item All things that are not ``inside a chip''
  909. @end enumerate
  910. Generic things inside target chips belong in target config files,
  911. not board config files. So for example a @code{reset-init} event
  912. handler should know board-specific oscillator and PLL parameters,
  913. which it passes to target-specific utility code.
  914. The most complex task of a board config file is creating such a
  915. @code{reset-init} event handler.
  916. Define those handlers last, after you verify the rest of the board
  917. configuration works.
  918. @subsection Communication Between Config files
  919. In addition to target-specific utility code, another way that
  920. board and target config files communicate is by following a
  921. convention on how to use certain variables.
  922. The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
  923. Thus the rule we follow in OpenOCD is this: Variables that begin with
  924. a leading underscore are temporary in nature, and can be modified and
  925. used at will within a target configuration file.
  926. Complex board config files can do the things like this,
  927. for a board with three chips:
  928. @example
  929. # Chip #1: PXA270 for network side, big endian
  930. set CHIPNAME network
  931. set ENDIAN big
  932. source [find target/pxa270.cfg]
  933. # on return: _TARGETNAME = network.cpu
  934. # other commands can refer to the "network.cpu" target.
  935. $_TARGETNAME configure .... events for this CPU..
  936. # Chip #2: PXA270 for video side, little endian
  937. set CHIPNAME video
  938. set ENDIAN little
  939. source [find target/pxa270.cfg]
  940. # on return: _TARGETNAME = video.cpu
  941. # other commands can refer to the "video.cpu" target.
  942. $_TARGETNAME configure .... events for this CPU..
  943. # Chip #3: Xilinx FPGA for glue logic
  944. set CHIPNAME xilinx
  945. unset ENDIAN
  946. source [find target/spartan3.cfg]
  947. @end example
  948. That example is oversimplified because it doesn't show any flash memory,
  949. or the @code{reset-init} event handlers to initialize external DRAM
  950. or (assuming it needs it) load a configuration into the FPGA.
  951. Such features are usually needed for low-level work with many boards,
  952. where ``low level'' implies that the board initialization software may
  953. not be working. (That's a common reason to need JTAG tools. Another
  954. is to enable working with microcontroller-based systems, which often
  955. have no debugging support except a JTAG connector.)
  956. Target config files may also export utility functions to board and user
  957. config files. Such functions should use name prefixes, to help avoid
  958. naming collisions.
  959. Board files could also accept input variables from user config files.
  960. For example, there might be a @code{J4_JUMPER} setting used to identify
  961. what kind of flash memory a development board is using, or how to set
  962. up other clocks and peripherals.
  963. @subsection Variable Naming Convention
  964. @cindex variable names
  965. Most boards have only one instance of a chip.
  966. However, it should be easy to create a board with more than
  967. one such chip (as shown above).
  968. Accordingly, we encourage these conventions for naming
  969. variables associated with different @file{target.cfg} files,
  970. to promote consistency and
  971. so that board files can override target defaults.
  972. Inputs to target config files include:
  973. @itemize @bullet
  974. @item @code{CHIPNAME} ...
  975. This gives a name to the overall chip, and is used as part of
  976. tap identifier dotted names.
  977. While the default is normally provided by the chip manufacturer,
  978. board files may need to distinguish between instances of a chip.
  979. @item @code{ENDIAN} ...
  980. By default @option{little} - although chips may hard-wire @option{big}.
  981. Chips that can't change endianness don't need to use this variable.
  982. @item @code{CPUTAPID} ...
  983. When OpenOCD examines the JTAG chain, it can be told verify the
  984. chips against the JTAG IDCODE register.
  985. The target file will hold one or more defaults, but sometimes the
  986. chip in a board will use a different ID (perhaps a newer revision).
  987. @end itemize
  988. Outputs from target config files include:
  989. @itemize @bullet
  990. @item @code{_TARGETNAME} ...
  991. By convention, this variable is created by the target configuration
  992. script. The board configuration file may make use of this variable to
  993. configure things like a ``reset init'' script, or other things
  994. specific to that board and that target.
  995. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  996. @code{_TARGETNAME1}, ... etc.
  997. @end itemize
  998. @subsection The reset-init Event Handler
  999. @cindex event, reset-init
  1000. @cindex reset-init handler
  1001. Board config files run in the OpenOCD configuration stage;
  1002. they can't use TAPs or targets, since they haven't been
  1003. fully set up yet.
  1004. This means you can't write memory or access chip registers;
  1005. you can't even verify that a flash chip is present.
  1006. That's done later in event handlers, of which the target @code{reset-init}
  1007. handler is one of the most important.
  1008. Except on microcontrollers, the basic job of @code{reset-init} event
  1009. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1010. Microcontrollers rarely use boot loaders; they run right out of their
  1011. on-chip flash and SRAM memory. But they may want to use one of these
  1012. handlers too, if just for developer convenience.
  1013. @quotation Note
  1014. Because this is so very board-specific, and chip-specific, no examples
  1015. are included here.
  1016. Instead, look at the board config files distributed with OpenOCD.
  1017. If you have a boot loader, its source code will help; so will
  1018. configuration files for other JTAG tools
  1019. (@pxref{Translating Configuration Files}).
  1020. @end quotation
  1021. Some of this code could probably be shared between different boards.
  1022. For example, setting up a DRAM controller often doesn't differ by
  1023. much except the bus width (16 bits or 32?) and memory timings, so a
  1024. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1025. those as parameters.
  1026. Similarly with oscillator, PLL, and clock setup;
  1027. and disabling the watchdog.
  1028. Structure the code cleanly, and provide comments to help
  1029. the next developer doing such work.
  1030. (@emph{You might be that next person} trying to reuse init code!)
  1031. The last thing normally done in a @code{reset-init} handler is probing
  1032. whatever flash memory was configured. For most chips that needs to be
  1033. done while the associated target is halted, either because JTAG memory
  1034. access uses the CPU or to prevent conflicting CPU access.
  1035. @subsection JTAG Clock Rate
  1036. Before your @code{reset-init} handler has set up
  1037. the PLLs and clocking, you may need to run with
  1038. a low JTAG clock rate.
  1039. @xref{JTAG Speed}.
  1040. Then you'd increase that rate after your handler has
  1041. made it possible to use the faster JTAG clock.
  1042. When the initial low speed is board-specific, for example
  1043. because it depends on a board-specific oscillator speed, then
  1044. you should probably set it up in the board config file;
  1045. if it's target-specific, it belongs in the target config file.
  1046. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1047. @uref{} gives details.}
  1048. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1049. Consult chip documentation to determine the peak JTAG clock rate,
  1050. which might be less than that.
  1051. @quotation Warning
  1052. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1053. software using a @option{wait for interrupt} operation blocks JTAG access.
  1054. Adaptive clocking provides a partial workaround, but a more complete
  1055. solution just avoids using that instruction with JTAG debuggers.
  1056. @end quotation
  1057. If the board supports adaptive clocking, use the @command{jtag_rclk}
  1058. command, in case your board is used with JTAG adapter which
  1059. also supports it. Otherwise use @command{jtag_khz}.
  1060. Set the slow rate at the beginning of the reset sequence,
  1061. and the faster rate as soon as the clocks are at full speed.
  1062. @section Target Config Files
  1063. @cindex config file, target
  1064. @cindex target config file
  1065. Board config files communicate with target config files using
  1066. naming conventions as described above, and may source one or
  1067. more target config files like this:
  1068. @example
  1069. source [find target/FOOBAR.cfg]
  1070. @end example
  1071. The point of a target config file is to package everything
  1072. about a given chip that board config files need to know.
  1073. In summary the target files should contain
  1074. @enumerate
  1075. @item Set defaults
  1076. @item Add TAPs to the scan chain
  1077. @item Add CPU targets (includes GDB support)
  1078. @item CPU/Chip/CPU-Core specific features
  1079. @item On-Chip flash
  1080. @end enumerate
  1081. As a rule of thumb, a target file sets up only one chip.
  1082. For a microcontroller, that will often include a single TAP,
  1083. which is a CPU needing a GDB target, and its on-chip flash.
  1084. More complex chips may include multiple TAPs, and the target
  1085. config file may need to define them all before OpenOCD
  1086. can talk to the chip.
  1087. For example, some phone chips have JTAG scan chains that include
  1088. an ARM core for operating system use, a DSP,
  1089. another ARM core embedded in an image processing engine,
  1090. and other processing engines.
  1091. @subsection Default Value Boiler Plate Code
  1092. All target configuration files should start with code like this,
  1093. letting board config files express environment-specific
  1094. differences in how things should be set up.
  1095. @example
  1096. # Boards may override chip names, perhaps based on role,
  1097. # but the default should match what the vendor uses
  1098. if @{ [info exists CHIPNAME] @} @{
  1100. @} else @{
  1101. set _CHIPNAME sam7x256
  1102. @}
  1103. # ONLY use ENDIAN with targets that can change it.
  1104. if @{ [info exists ENDIAN] @} @{
  1105. set _ENDIAN $ENDIAN
  1106. @} else @{
  1107. set _ENDIAN little
  1108. @}
  1109. # TAP identifiers may change as chips mature, for example with
  1110. # new revision fields (the "3" here). Pick a good default; you
  1111. # can pass several such identifiers to the "jtag newtap" command.
  1112. if @{ [info exists CPUTAPID ] @} @{
  1114. @} else @{
  1115. set _CPUTAPID 0x3f0f0f0f
  1116. @}
  1117. @end example
  1118. @c but 0x3f0f0f0f is for an str73x part ...
  1119. @emph{Remember:} Board config files may include multiple target
  1120. config files, or the same target file multiple times
  1121. (changing at least @code{CHIPNAME}).
  1122. Likewise, the target configuration file should define
  1123. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1124. use it later on when defining debug targets:
  1125. @example
  1126. set _TARGETNAME $_CHIPNAME.cpu
  1127. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1128. @end example
  1129. @subsection Adding TAPs to the Scan Chain
  1130. After the ``defaults'' are set up,
  1131. add the TAPs on each chip to the JTAG scan chain.
  1132. @xref{TAP Declaration}, and the naming convention
  1133. for taps.
  1134. In the simplest case the chip has only one TAP,
  1135. probably for a CPU or FPGA.
  1136. The config file for the Atmel AT91SAM7X256
  1137. looks (in part) like this:
  1138. @example
  1139. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1140. @end example
  1141. A board with two such at91sam7 chips would be able
  1142. to source such a config file twice, with different
  1143. values for @code{CHIPNAME}, so
  1144. it adds a different TAP each time.
  1145. If there are nonzero @option{-expected-id} values,
  1146. OpenOCD attempts to verify the actual tap id against those values.
  1147. It will issue error messages if there is mismatch, which
  1148. can help to pinpoint problems in OpenOCD configurations.
  1149. @example
  1150. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1151. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1152. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1153. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1154. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1155. @end example
  1156. There are more complex examples too, with chips that have
  1157. multiple TAPs. Ones worth looking at include:
  1158. @itemize
  1159. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1160. plus a JRC to enable them
  1161. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1162. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1163. is not currently used)
  1164. @end itemize
  1165. @subsection Add CPU targets
  1166. After adding a TAP for a CPU, you should set it up so that
  1167. GDB and other commands can use it.
  1168. @xref{CPU Configuration}.
  1169. For the at91sam7 example above, the command can look like this;
  1170. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1171. to little endian, and this chip doesn't support changing that.
  1172. @example
  1173. set _TARGETNAME $_CHIPNAME.cpu
  1174. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1175. @end example
  1176. Work areas are small RAM areas associated with CPU targets.
  1177. They are used by OpenOCD to speed up downloads,
  1178. and to download small snippets of code to program flash chips.
  1179. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1180. a work area if you can.
  1181. Again using the at91sam7 as an example, this can look like:
  1182. @example
  1183. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1184. -work-area-size 0x4000 -work-area-backup 0
  1185. @end example
  1186. @subsection Chip Reset Setup
  1187. As a rule, you should put the @command{reset_config} command
  1188. into the board file. Most things you think you know about a
  1189. chip can be tweaked by the board.
  1190. Some chips have specific ways the TRST and SRST signals are
  1191. managed. In the unusual case that these are @emph{chip specific}
  1192. and can never be changed by board wiring, they could go here.
  1193. For example, some chips can't support JTAG debugging without
  1194. both signals.
  1195. Provide a @code{reset-assert} event handler if you can.
  1196. Such a handler uses JTAG operations to reset the target,
  1197. letting this target config be used in systems which don't
  1198. provide the optional SRST signal, or on systems where you
  1199. don't want to reset all targets at once.
  1200. Such a handler might write to chip registers to force a reset,
  1201. use a JRC to do that (preferable -- the target may be wedged!),
  1202. or force a watchdog timer to trigger.
  1203. (For Cortex-M3 targets, this is not necessary. The target
  1204. driver knows how to use trigger an NVIC reset when SRST is
  1205. not available.)
  1206. Some chips need special attention during reset handling if
  1207. they're going to be used with JTAG.
  1208. An example might be needing to send some commands right
  1209. after the target's TAP has been reset, providing a
  1210. @code{reset-deassert-post} event handler that writes a chip
  1211. register to report that JTAG debugging is being done.
  1212. Another would be reconfiguring the watchdog so that it stops
  1213. counting while the core is halted in the debugger.
  1214. JTAG clocking constraints often change during reset, and in
  1215. some cases target config files (rather than board config files)
  1216. are the right places to handle some of those issues.
  1217. For example, immediately after reset most chips run using a
  1218. slower clock than they will use later.
  1219. That means that after reset (and potentially, as OpenOCD
  1220. first starts up) they must use a slower JTAG clock rate
  1221. than they will use later.
  1222. @xref{JTAG Speed}.
  1223. @quotation Important
  1224. When you are debugging code that runs right after chip
  1225. reset, getting these issues right is critical.
  1226. In particular, if you see intermittent failures when
  1227. OpenOCD verifies the scan chain after reset,
  1228. look at how you are setting up JTAG clocking.
  1229. @end quotation
  1230. @subsection ARM Core Specific Hacks
  1231. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1232. special high speed download features - enable it.
  1233. If present, the MMU, the MPU and the CACHE should be disabled.
  1234. Some ARM cores are equipped with trace support, which permits
  1235. examination of the instruction and data bus activity. Trace
  1236. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1237. on one of the core's scan chains. The ETM emits voluminous data
  1238. through a ``trace port''. (@xref{ARM Hardware Tracing}.)
  1239. If you are using an external trace port,
  1240. configure it in your board config file.
  1241. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1242. configure it in your target config file.
  1243. @example
  1244. etm config $_TARGETNAME 16 normal full etb
  1245. etb config $_TARGETNAME $_CHIPNAME.etb
  1246. @end example
  1247. @subsection Internal Flash Configuration
  1248. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1249. @b{Never ever} in the ``target configuration file'' define any type of
  1250. flash that is external to the chip. (For example a BOOT flash on
  1251. Chip Select 0.) Such flash information goes in a board file - not
  1252. the TARGET (chip) file.
  1253. Examples:
  1254. @itemize @bullet
  1255. @item at91sam7x256 - has 256K flash YES enable it.
  1256. @item str912 - has flash internal YES enable it.
  1257. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1258. @item pxa270 - again - CS0 flash - it goes in the board file.
  1259. @end itemize
  1260. @anchor{Translating Configuration Files}
  1261. @section Translating Configuration Files
  1262. @cindex translation
  1263. If you have a configuration file for another hardware debugger
  1264. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1265. Lauterbach, Segger, Macraigor, etc.), translating
  1266. it into OpenOCD syntax is often quite straightforward. The most tricky
  1267. part of creating a configuration script is oftentimes the reset init
  1268. sequence where e.g. PLLs, DRAM and the like is set up.
  1269. One trick that you can use when translating is to write small
  1270. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1271. can avoid manual translation errors and make it easier to
  1272. convert other scripts later on.
  1273. Example of transforming quirky arguments to a simple search and
  1274. replace job:
  1275. @example
  1276. # Lauterbach syntax(?)
  1277. #
  1278. # Data.Set c15:0x042f %long 0x40000015
  1279. #
  1280. # OpenOCD syntax when using procedure below.
  1281. #
  1282. # setc15 0x01 0x00050078
  1283. proc setc15 @{regs value@} @{
  1284. global TARGETNAME
  1285. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1286. arm mcr 15 [expr ($regs>>12)&0x7] \
  1287. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1288. [expr ($regs>>8)&0x7] $value
  1289. @}
  1290. @end example
  1291. @node Daemon Configuration
  1292. @chapter Daemon Configuration
  1293. @cindex initialization
  1294. The commands here are commonly found in the openocd.cfg file and are
  1295. used to specify what TCP/IP ports are used, and how GDB should be
  1296. supported.
  1297. @anchor{Configuration Stage}
  1298. @section Configuration Stage
  1299. @cindex configuration stage
  1300. @cindex config command
  1301. When the OpenOCD server process starts up, it enters a
  1302. @emph{configuration stage} which is the only time that
  1303. certain commands, @emph{configuration commands}, may be issued.
  1304. In this manual, the definition of a configuration command is
  1305. presented as a @emph{Config Command}, not as a @emph{Command}
  1306. which may be issued interactively.
  1307. Those configuration commands include declaration of TAPs,
  1308. flash banks,
  1309. the interface used for JTAG communication,
  1310. and other basic setup.
  1311. The server must leave the configuration stage before it
  1312. may access or activate TAPs.
  1313. After it leaves this stage, configuration commands may no
  1314. longer be issued.
  1315. @section Entering the Run Stage
  1316. The first thing OpenOCD does after leaving the configuration
  1317. stage is to verify that it can talk to the scan chain
  1318. (list of TAPs) which has been configured.
  1319. It will warn if it doesn't find TAPs it expects to find,
  1320. or finds TAPs that aren't supposed to be there.
  1321. You should see no errors at this point.
  1322. If you see errors, resolve them by correcting the
  1323. commands you used to configure the server.
  1324. Common errors include using an initial JTAG speed that's too
  1325. fast, and not providing the right IDCODE values for the TAPs
  1326. on the scan chain.
  1327. Once OpenOCD has entered the run stage, a number of commands
  1328. become available.
  1329. A number of these relate to the debug targets you may have declared.
  1330. For example, the @command{mww} command will not be available until
  1331. a target has been successfuly instantiated.
  1332. If you want to use those commands, you may need to force
  1333. entry to the run stage.
  1334. @deffn {Config Command} init
  1335. This command terminates the configuration stage and
  1336. enters the run stage. This helps when you need to have
  1337. the startup scripts manage tasks such as resetting the target,
  1338. programming flash, etc. To reset the CPU upon startup, add "init" and
  1339. "reset" at the end of the config script or at the end of the OpenOCD
  1340. command line using the @option{-c} command line switch.
  1341. If this command does not appear in any startup/configuration file
  1342. OpenOCD executes the command for you after processing all
  1343. configuration files and/or command line options.
  1344. @b{NOTE:} This command normally occurs at or near the end of your
  1345. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1346. targets ready. For example: If your openocd.cfg file needs to
  1347. read/write memory on your target, @command{init} must occur before
  1348. the memory read/write commands. This includes @command{nand probe}.
  1349. @end deffn
  1350. @deffn {Overridable Procedure} jtag_init
  1351. This is invoked at server startup to verify that it can talk
  1352. to the scan chain (list of TAPs) which has been configured.
  1353. The default implementation first tries @command{jtag arp_init},
  1354. which uses only a lightweight JTAG reset before examining the
  1355. scan chain.
  1356. If that fails, it tries again, using a harder reset
  1357. from the overridable procedure @command{init_reset}.
  1358. Implementations must have verified the JTAG scan chain before
  1359. they return.
  1360. This is done by calling @command{jtag arp_init}
  1361. (or @command{jtag arp_init-reset}).
  1362. @end deffn
  1363. @anchor{TCP/IP Ports}
  1364. @section TCP/IP Ports
  1365. @cindex TCP port
  1366. @cindex server
  1367. @cindex port
  1368. @cindex security
  1369. The OpenOCD server accepts remote commands in several syntaxes.
  1370. Each syntax uses a different TCP/IP port, which you may specify
  1371. only during configuration (before those ports are opened).
  1372. For reasons including security, you may wish to prevent remote
  1373. access using one or more of these ports.
  1374. In such cases, just specify the relevant port number as zero.
  1375. If you disable all access through TCP/IP, you will need to
  1376. use the command line @option{-pipe} option.
  1377. @deffn {Command} gdb_port (number)
  1378. @cindex GDB server
  1379. Specify or query the first port used for incoming GDB connections.
  1380. The GDB port for the
  1381. first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
  1382. When not specified during the configuration stage,
  1383. the port @var{number} defaults to 3333.
  1384. When specified as zero, this port is not activated.
  1385. @end deffn
  1386. @deffn {Command} tcl_port (number)
  1387. Specify or query the port used for a simplified RPC
  1388. connection that can be used by clients to issue TCL commands and get the
  1389. output from the Tcl engine.
  1390. Intended as a machine interface.
  1391. When not specified during the configuration stage,
  1392. the port @var{number} defaults to 6666.
  1393. When specified as zero, this port is not activated.
  1394. @end deffn
  1395. @deffn {Command} telnet_port (number)
  1396. Specify or query the
  1397. port on which to listen for incoming telnet connections.
  1398. This port is intended for interaction with one human through TCL commands.
  1399. When not specified during the configuration stage,
  1400. the port @var{number} defaults to 4444.
  1401. When specified as zero, this port is not activated.
  1402. @end deffn
  1403. @anchor{GDB Configuration}
  1404. @section GDB Configuration
  1405. @cindex GDB
  1406. @cindex GDB configuration
  1407. You can reconfigure some GDB behaviors if needed.
  1408. The ones listed here are static and global.
  1409. @xref{Target Configuration}, about configuring individual targets.
  1410. @xref{Target Events}, about configuring target-specific event handling.
  1411. @anchor{gdb_breakpoint_override}
  1412. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1413. Force breakpoint type for gdb @command{break} commands.
  1414. This option supports GDB GUIs which don't
  1415. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1416. GDB behaviour is not sufficient. GDB normally uses hardware
  1417. breakpoints if the memory map has been set up for flash regions.
  1418. @end deffn
  1419. @anchor{gdb_flash_program}
  1420. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1421. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1422. vFlash packet is received.
  1423. The default behaviour is @option{enable}.
  1424. @end deffn
  1425. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1426. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1427. requested. GDB will then know when to set hardware breakpoints, and program flash
  1428. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1429. for flash programming to work.
  1430. Default behaviour is @option{enable}.
  1431. @xref{gdb_flash_program}.
  1432. @end deffn
  1433. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1434. Specifies whether data aborts cause an error to be reported
  1435. by GDB memory read packets.
  1436. The default behaviour is @option{disable};
  1437. use @option{enable} see these errors reported.
  1438. @end deffn
  1439. @anchor{Event Polling}
  1440. @section Event Polling
  1441. Hardware debuggers are parts of asynchronous systems,
  1442. where significant events can happen at any time.
  1443. The OpenOCD server needs to detect some of these events,
  1444. so it can report them to through TCL command line
  1445. or to GDB.
  1446. Examples of such events include:
  1447. @itemize
  1448. @item One of the targets can stop running ... maybe it triggers
  1449. a code breakpoint or data watchpoint, or halts itself.
  1450. @item Messages may be sent over ``debug message'' channels ... many
  1451. targets support such messages sent over JTAG,
  1452. for receipt by the person debugging or tools.
  1453. @item Loss of power ... some adapters can detect these events.
  1454. @item Resets not issued through JTAG ... such reset sources
  1455. can include button presses or other system hardware, sometimes
  1456. including the target itself (perhaps through a watchdog).
  1457. @item Debug instrumentation sometimes supports event triggering
  1458. such as ``trace buffer full'' (so it can quickly be emptied)
  1459. or other signals (to correlate with code behavior).
  1460. @end itemize
  1461. None of those events are signaled through standard JTAG signals.
  1462. However, most conventions for JTAG connectors include voltage
  1463. level and system reset (SRST) signal detection.
  1464. Some connectors also include instrumentation signals, which
  1465. can imply events when those signals are inputs.
  1466. In general, OpenOCD needs to periodically check for those events,
  1467. either by looking at the status of signals on the JTAG connector
  1468. or by sending synchronous ``tell me your status'' JTAG requests
  1469. to the various active targets.
  1470. There is a command to manage and monitor that polling,
  1471. which is normally done in the background.
  1472. @deffn Command poll [@option{on}|@option{off}]
  1473. Poll the current target for its current state.
  1474. (Also, @pxref{target curstate}.)
  1475. If that target is in debug mode, architecture
  1476. specific information about the current state is printed.
  1477. An optional parameter
  1478. allows background polling to be enabled and disabled.
  1479. You could use this from the TCL command shell, or
  1480. from GDB using @command{monitor poll} command.
  1481. @example
  1482. > poll
  1483. background polling: on
  1484. target state: halted
  1485. target halted in ARM state due to debug-request, \
  1486. current mode: Supervisor
  1487. cpsr: 0x800000d3 pc: 0x11081bfc
  1488. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1489. >
  1490. @end example
  1491. @end deffn
  1492. @node Interface - Dongle Configuration
  1493. @chapter Interface - Dongle Configuration
  1494. @cindex config file, interface
  1495. @cindex interface config file
  1496. JTAG Adapters/Interfaces/Dongles are normally configured
  1497. through commands in an interface configuration
  1498. file which is sourced by your @file{openocd.cfg} file, or
  1499. through a command line @option{-f interface/....cfg} option.
  1500. @example
  1501. source [find interface/olimex-jtag-tiny.cfg]
  1502. @end example
  1503. These commands tell
  1504. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1505. A few cases are so simple that you only need to say what driver to use:
  1506. @example
  1507. # jlink interface
  1508. interface jlink
  1509. @end example
  1510. Most adapters need a bit more configuration than that.
  1511. @section Interface Configuration
  1512. The interface command tells OpenOCD what type of JTAG dongle you are
  1513. using. Depending on the type of dongle, you may need to have one or
  1514. more additional commands.
  1515. @deffn {Config Command} {interface} name
  1516. Use the interface driver @var{name} to connect to the
  1517. target.
  1518. @end deffn
  1519. @deffn Command {interface_list}
  1520. List the interface drivers that have been built into
  1521. the running copy of OpenOCD.
  1522. @end deffn
  1523. @deffn Command {jtag interface}
  1524. Returns the name of the interface driver being used.
  1525. @end deffn
  1526. @section Interface Drivers
  1527. Each of the interface drivers listed here must be explicitly
  1528. enabled when OpenOCD is configured, in order to be made
  1529. available at run time.
  1530. @deffn {Interface Driver} {amt_jtagaccel}
  1531. Amontec Chameleon in its JTAG Accelerator configuration,
  1532. connected to a PC's EPP mode parallel port.
  1533. This defines some driver-specific commands:
  1534. @deffn {Config Command} {parport_port} number
  1535. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1536. the number of the @file{/dev/parport} device.
  1537. @end deffn
  1538. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  1539. Displays status of RTCK option.
  1540. Optionally sets that option first.
  1541. @end deffn
  1542. @end deffn
  1543. @deffn {Interface Driver} {arm-jtag-ew}
  1544. Olimex ARM-JTAG-EW USB adapter
  1545. This has one driver-specific command:
  1546. @deffn Command {armjtagew_info}
  1547. Logs some status
  1548. @end deffn
  1549. @end deffn
  1550. @deffn {Interface Driver} {at91rm9200}
  1551. Supports bitbanged JTAG from the local system,
  1552. presuming that system is an Atmel AT91rm9200
  1553. and a specific set of GPIOs is used.
  1554. @c command: at91rm9200_device NAME
  1555. @c chooses among list of bit configs ... only one option
  1556. @end deffn
  1557. @deffn {Interface Driver} {dummy}
  1558. A dummy software-only driver for debugging.
  1559. @end deffn
  1560. @deffn {Interface Driver} {ep93xx}
  1561. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1562. @end deffn
  1563. @deffn {Interface Driver} {ft2232}
  1564. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  1565. These interfaces have several commands, used to configure the driver
  1566. before initializing the JTAG scan chain:
  1567. @deffn {Config Command} {ft2232_device_desc} description
  1568. Provides the USB device description (the @emph{iProduct string})
  1569. of the FTDI FT2232 device. If not
  1570. specified, the FTDI default value is used. This setting is only valid
  1571. if compiled with FTD2XX support.
  1572. @end deffn
  1573. @deffn {Config Command} {ft2232_serial} serial-number
  1574. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  1575. in case the vendor provides unique IDs and more than one FT2232 device
  1576. is connected to the host.
  1577. If not specified, serial numbers are not considered.
  1578. (Note that USB serial numbers can be arbitrary Unicode strings,
  1579. and are not restricted to containing only decimal digits.)
  1580. @end deffn
  1581. @deffn {Config Command} {ft2232_layout} name
  1582. Each vendor's FT2232 device can use different GPIO signals
  1583. to control output-enables, reset signals, and LEDs.
  1584. Currently valid layout @var{name} values include:
  1585. @itemize @minus
  1586. @item @b{axm0432_jtag} Axiom AXM-0432
  1587. @item @b{comstick} Hitex STR9 comstick
  1588. @item @b{cortino} Hitex Cortino JTAG interface
  1589. @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
  1590. either for the local Cortex-M3 (SRST only)
  1591. or in a passthrough mode (neither SRST nor TRST)
  1592. @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
  1593. @item @b{flyswatter} Tin Can Tools Flyswatter
  1594. @item @b{icebear} ICEbear JTAG adapter from Section 5
  1595. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  1596. @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
  1597. @item @b{m5960} American Microsystems M5960
  1598. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  1599. @item @b{oocdlink} OOCDLink
  1600. @c oocdlink ~= jtagkey_prototype_v1
  1601. @item @b{sheevaplug} Marvell Sheevaplug development kit
  1602. @item @b{signalyzer} Xverve Signalyzer
  1603. @item @b{stm32stick} Hitex STM32 Performance Stick
  1604. @item @b{turtelizer2} egnite Software turtelizer2
  1605. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  1606. @end itemize
  1607. @end deffn
  1608. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  1609. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  1610. default values are used.
  1611. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1612. @example
  1613. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  1614. @end example
  1615. @end deffn
  1616. @deffn {Config Command} {ft2232_latency} ms
  1617. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  1618. ft2232_read() fails to return the expected number of bytes. This can be caused by
  1619. USB communication delays and has proved hard to reproduce and debug. Setting the
  1620. FT2232 latency timer to a larger value increases delays for short USB packets but it
  1621. also reduces the risk of timeouts before receiving the expected number of bytes.
  1622. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  1623. @end deffn
  1624. For example, the interface config file for a
  1625. Turtelizer JTAG Adapter looks something like this:
  1626. @example
  1627. interface ft2232
  1628. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  1629. ft2232_layout turtelizer2
  1630. ft2232_vid_pid 0x0403 0xbdc8
  1631. @end example
  1632. @end deffn
  1633. @deffn {Interface Driver} {gw16012}
  1634. Gateworks GW16012 JTAG programmer.
  1635. This has one driver-specific command:
  1636. @deffn {Config Command} {parport_port} number
  1637. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1638. the number of the @file{/dev/parport} device.
  1639. @end deffn
  1640. @end deffn
  1641. @deffn {Interface Driver} {jlink}
  1642. Segger jlink USB adapter
  1643. @c command: jlink_info
  1644. @c dumps status
  1645. @c command: jlink_hw_jtag (2|3)
  1646. @c sets version 2 or 3
  1647. @end deffn
  1648. @deffn {Interface Driver} {parport}
  1649. Supports PC parallel port bit-banging cables:
  1650. Wigglers, PLD download cable, and more.
  1651. These interfaces have several commands, used to configure the driver
  1652. before initializing the JTAG scan chain:
  1653. @deffn {Config Command} {parport_cable} name
  1654. The layout of the parallel port cable used to connect to the target.
  1655. Currently valid cable @var{name} values include:
  1656. @itemize @minus
  1657. @item @b{altium} Altium Universal JTAG cable.
  1658. @item @b{arm-jtag} Same as original wiggler except SRST and
  1659. TRST connections reversed and TRST is also inverted.
  1660. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  1661. in configuration mode. This is only used to
  1662. program the Chameleon itself, not a connected target.
  1663. @item @b{dlc5} The Xilinx Parallel cable III.
  1664. @item @b{flashlink} The ST Parallel cable.
  1665. @item @b{lattice} Lattice ispDOWNLOAD Cable
  1666. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  1667. some versions of
  1668. Amontec's Chameleon Programmer. The new version available from
  1669. the website uses the original Wiggler layout ('@var{wiggler}')
  1670. @item @b{triton} The parallel port adapter found on the
  1671. ``Karo Triton 1 Development Board''.
  1672. This is also the layout used by the HollyGates design
  1673. (see @uref{}).
  1674. @item @b{wiggler} The original Wiggler layout, also supported by
  1675. several clones, such as the Olimex ARM-JTAG
  1676. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  1677. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  1678. @end itemize
  1679. @end deffn
  1680. @deffn {Config Command} {parport_port} number
  1681. Either the address of the I/O port (default: 0x378 for LPT1) or the number of
  1682. the @file{/dev/parport} device
  1683. When using PPDEV to access the parallel port, use the number of the parallel port:
  1684. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  1685. you may encounter a problem.
  1686. @end deffn
  1687. @deffn Command {parport_toggling_time} [nanoseconds]
  1688. Displays how many nanoseconds the hardware needs to toggle TCK;
  1689. the parport driver uses this value to obey the
  1690. @command{jtag_khz} configuration.
  1691. When the optional @var{nanoseconds} parameter is given,
  1692. that setting is changed before displaying the current value.
  1693. The default setting should work reasonably well on commodity PC hardware.
  1694. However, you may want to calibrate for your specific hardware.
  1695. @quotation Tip
  1696. To measure the toggling time with a logic analyzer or a digital storage
  1697. oscilloscope, follow the procedure below:
  1698. @example
  1699. > parport_toggling_time 1000
  1700. > jtag_khz 500
  1701. @end example
  1702. This sets the maximum JTAG clock speed of the hardware, but
  1703. the actual speed probably deviates from the requested 500 kHz.
  1704. Now, measure the time between the two closest spaced TCK transitions.
  1705. You can use @command{runtest 1000} or something similar to generate a
  1706. large set of samples.
  1707. Update the setting to match your measurement:
  1708. @example
  1709. > parport_toggling_time <measured nanoseconds>
  1710. @end example
  1711. Now the clock speed will be a better match for @command{jtag_khz rate}
  1712. commands given in OpenOCD scripts and event handlers.
  1713. You can do something similar with many digital multimeters, but note
  1714. that you'll probably need to run the clock continuously for several
  1715. seconds before it decides what clock rate to show. Adjust the
  1716. toggling time up or down until the measured clock rate is a good
  1717. match for the jtag_khz rate you specified; be conservative.
  1718. @end quotation
  1719. @end deffn
  1720. @deffn {Config Command} {parport_write_on_exit} (on|off)
  1721. This will configure the parallel driver to write a known
  1722. cable-specific value to the parallel interface on exiting OpenOCD
  1723. @end deffn
  1724. For example, the interface configuration file for a
  1725. classic ``Wiggler'' cable might look something like this:
  1726. @example
  1727. interface parport
  1728. parport_port 0xc8b8
  1729. parport_cable wiggler
  1730. @end example
  1731. @end deffn
  1732. @deffn {Interface Driver} {presto}
  1733. ASIX PRESTO USB JTAG programmer.
  1734. @c command: presto_serial str
  1735. @c sets serial number
  1736. @end deffn
  1737. @deffn {Interface Driver} {rlink}
  1738. Raisonance RLink USB adapter
  1739. @end deffn
  1740. @deffn {Interface Driver} {usbprog}
  1741. usbprog is a freely programmable USB adapter.
  1742. @end deffn
  1743. @deffn {Interface Driver} {vsllink}
  1744. vsllink is part of Versaloon which is a versatile USB programmer.
  1745. @quotation Note
  1746. This defines quite a few driver-specific commands,
  1747. which are not currently documented here.
  1748. @end quotation
  1749. @end deffn
  1750. @deffn {Interface Driver} {ZY1000}
  1751. This is the Zylin ZY1000 JTAG debugger.
  1752. @quotation Note
  1753. This defines some driver-specific commands,
  1754. which are not currently documented here.
  1755. @end quotation
  1756. @deffn Command power [@option{on}|@option{off}]
  1757. Turn power switch to target on/off.
  1758. No arguments: print status.
  1759. @end deffn
  1760. @end deffn
  1761. @anchor{JTAG Speed}
  1762. @section JTAG Speed
  1763. JTAG clock setup is part of system setup.
  1764. It @emph{does not belong with interface setup} since any interface
  1765. only knows a few of the constraints for the JTAG clock speed.
  1766. Sometimes the JTAG speed is
  1767. changed during the target initialization process: (1) slow at
  1768. reset, (2) program the CPU clocks, (3) run fast.
  1769. Both the "slow" and "fast" clock rates are functions of the
  1770. oscillators used, the chip, the board design, and sometimes
  1771. power management software that may be active.
  1772. The speed used during reset, and the scan chain verification which
  1773. follows reset, can be adjusted using a @code{reset-start}
  1774. target event handler.
  1775. It can then be reconfigured to a faster speed by a
  1776. @code{reset-init} target event handler after it reprograms those
  1777. CPU clocks, or manually (if something else, such as a boot loader,
  1778. sets up those clocks).
  1779. @xref{Target Events}.
  1780. When the initial low JTAG speed is a chip characteristic, perhaps
  1781. because of a required oscillator speed, provide such a handler
  1782. in the target config file.
  1783. When that speed is a function of a board-specific characteristic
  1784. such as which speed oscillator is used, it belongs in the board
  1785. config file instead.
  1786. In both cases it's safest to also set the initial JTAG clock rate
  1787. to that same slow speed, so that OpenOCD never starts up using a
  1788. clock speed that's faster than the scan chain can support.
  1789. @example
  1790. jtag_rclk 3000
  1791. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  1792. @end example
  1793. If your system supports adaptive clocking (RTCK), configuring
  1794. JTAG to use that is probably the most robust approach.
  1795. However, it introduces delays to synchronize clocks; so it
  1796. may not be the fastest solution.
  1797. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  1798. instead of @command{jtag_khz}.
  1799. @deffn {Command} jtag_khz max_speed_kHz
  1800. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  1801. JTAG interfaces usually support a limited number of
  1802. speeds. The speed actually used won't be faster
  1803. than the speed specified.
  1804. Chip data sheets generally include a top JTAG clock rate.
  1805. The actual rate is often a function of a CPU core clock,
  1806. and is normally less than that peak rate.
  1807. For example, most ARM cores accept at most one sixth of the CPU clock.
  1808. Speed 0 (khz) selects RTCK method.
  1809. @xref{FAQ RTCK}.
  1810. If your system uses RTCK, you won't need to change the
  1811. JTAG clocking after setup.
  1812. Not all interfaces, boards, or targets support ``rtck''.
  1813. If the interface device can not
  1814. support it, an error is returned when you try to use RTCK.
  1815. @end deffn
  1816. @defun jtag_rclk fallback_speed_kHz
  1817. @cindex adaptive clocking
  1818. @cindex RTCK
  1819. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  1820. If that fails (maybe the interface, board, or target doesn't
  1821. support it), falls back to the specified frequency.
  1822. @example
  1823. # Fall back to 3mhz if RTCK is not supported
  1824. jtag_rclk 3000
  1825. @end example
  1826. @end defun
  1827. @node Reset Configuration
  1828. @chapter Reset Configuration
  1829. @cindex Reset Configuration
  1830. Every system configuration may require a different reset
  1831. configuration. This can also be quite confusing.
  1832. Resets also interact with @var{reset-init} event handlers,
  1833. which do things like setting up clocks and DRAM, and
  1834. JTAG clock rates. (@xref{JTAG Speed}.)
  1835. They can also interact with JTAG routers.
  1836. Please see the various board files for examples.
  1837. @quotation Note
  1838. To maintainers and integrators:
  1839. Reset configuration touches several things at once.
  1840. Normally the board configuration file
  1841. should define it and assume that the JTAG adapter supports
  1842. everything that's wired up to the board's JTAG connector.
  1843. However, the target configuration file could also make note
  1844. of something the silicon vendor has done inside the chip,
  1845. which will be true for most (or all) boards using that chip.
  1846. And when the JTAG adapter doesn't support everything, the
  1847. user configuration file will need to override parts of
  1848. the reset configuration provided by other files.
  1849. @end quotation
  1850. @section Types of Reset
  1851. There are many kinds of reset possible through JTAG, but
  1852. they may not all work with a given board and adapter.
  1853. That's part of why reset configuration can be error prone.
  1854. @itemize @bullet
  1855. @item
  1856. @emph{System Reset} ... the @emph{SRST} hardware signal
  1857. resets all chips connected to the JTAG adapter, such as processors,
  1858. power management chips, and I/O controllers. Normally resets triggered
  1859. with this signal behave exactly like pressing a RESET button.
  1860. @item
  1861. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  1862. just the TAP controllers connected to the JTAG adapter.
  1863. Such resets should not be visible to the rest of the system; resetting a
  1864. device's the TAP controller just puts that controller into a known state.
  1865. @item
  1866. @emph{Emulation Reset} ... many devices can be reset through JTAG
  1867. commands. These resets are often distinguishable from system
  1868. resets, either explicitly (a "reset reason" register says so)
  1869. or implicitly (not all parts of the chip get reset).
  1870. @item
  1871. @emph{Other Resets} ... system-on-chip devices often support
  1872. several other types of reset.
  1873. You may need to arrange that a watchdog timer stops
  1874. while debugging, preventing a watchdog reset.
  1875. There may be individual module resets.
  1876. @end itemize
  1877. In the best case, OpenOCD can hold SRST, then reset
  1878. the TAPs via TRST and send commands through JTAG to halt the
  1879. CPU at the reset vector before the 1st instruction is executed.
  1880. Then when it finally releases the SRST signal, the system is
  1881. halted under debugger control before any code has executed.
  1882. This is the behavior required to support the @command{reset halt}
  1883. and @command{reset init} commands; after @command{reset init} a
  1884. board-specific script might do things like setting up DRAM.
  1885. (@xref{Reset Command}.)
  1886. @anchor{SRST and TRST Issues}
  1887. @section SRST and TRST Issues
  1888. Because SRST and TRST are hardware signals, they can have a
  1889. variety of system-specific constraints. Some of the most
  1890. common issues are:
  1891. @itemize @bullet
  1892. @item @emph{Signal not available} ... Some boards don't wire
  1893. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  1894. support such signals even if they are wired up.
  1895. Use the @command{reset_config} @var{signals} options to say
  1896. when either of those signals is not connected.
  1897. When SRST is not available, your code might not be able to rely
  1898. on controllers having been fully reset during code startup.
  1899. Missing TRST is not a problem, since JTAG level resets can
  1900. be triggered using with TMS signaling.
  1901. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  1902. adapter will connect SRST to TRST, instead of keeping them separate.
  1903. Use the @command{reset_config} @var{combination} options to say
  1904. when those signals aren't properly independent.
  1905. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  1906. delay circuit, reset supervisor, or on-chip features can extend
  1907. the effect of a JTAG adapter's reset for some time after the adapter
  1908. stops issuing the reset. For example, there may be chip or board
  1909. requirements that all reset pulses last for at least a
  1910. certain amount of time; and reset buttons commonly have
  1911. hardware debouncing.
  1912. Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
  1913. commands to say when extra delays are needed.
  1914. @item @emph{Drive type} ... Reset lines often have a pullup
  1915. resistor, letting the JTAG interface treat them as open-drain
  1916. signals. But that's not a requirement, so the adapter may need
  1917. to use push/pull output drivers.
  1918. Also, with weak pullups it may be advisable to drive
  1919. signals to both levels (push/pull) to minimize rise times.
  1920. Use the @command{reset_config} @var{trst_type} and
  1921. @var{srst_type} parameters to say how to drive reset signals.
  1922. @item @emph{Special initialization} ... Targets sometimes need
  1923. special JTAG initialization sequences to handle chip-specific
  1924. issues (not limited to errata).
  1925. For example, certain JTAG commands might need to be issued while
  1926. the system as a whole is in a reset state (SRST active)
  1927. but the JTAG scan chain is usable (TRST inactive).
  1928. Many systems treat combined assertion of SRST and TRST as a
  1929. trigger for a harder reset than SRST alone.
  1930. Such custom reset handling is discussed later in this chapter.
  1931. @end itemize
  1932. There can also be other issues.
  1933. Some devices don't fully conform to the JTAG specifications.
  1934. Trivial system-specific differences are common, such as
  1935. SRST and TRST using slightly different names.
  1936. There are also vendors who distribute key JTAG documentation for
  1937. their chips only to developers who have signed a Non-Disclosure
  1938. Agreement (NDA).
  1939. Sometimes there are chip-specific extensions like a requirement to use
  1940. the normally-optional TRST signal (precluding use of JTAG adapters which
  1941. don't pass TRST through), or needing extra steps to complete a TAP reset.
  1942. In short, SRST and especially TRST handling may be very finicky,
  1943. needing to cope with both architecture and board specific constraints.
  1944. @section Commands for Handling Resets
  1945. @deffn {Command} jtag_nsrst_assert_width milliseconds
  1946. Minimum amount of time (in milliseconds) OpenOCD should wait
  1947. after asserting nSRST (active-low system reset) before
  1948. allowing it to be deasserted.
  1949. @end deffn
  1950. @deffn {Command} jtag_nsrst_delay milliseconds
  1951. How long (in milliseconds) OpenOCD should wait after deasserting
  1952. nSRST (active-low system reset) before starting new JTAG operations.
  1953. When a board has a reset button connected to SRST line it will
  1954. probably have hardware debouncing, implying you should use this.
  1955. @end deffn
  1956. @deffn {Command} jtag_ntrst_assert_width milliseconds
  1957. Minimum amount of time (in milliseconds) OpenOCD should wait
  1958. after asserting nTRST (active-low JTAG TAP reset) before
  1959. allowing it to be deasserted.
  1960. @end deffn
  1961. @deffn {Command} jtag_ntrst_delay milliseconds
  1962. How long (in milliseconds) OpenOCD should wait after deasserting
  1963. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  1964. @end deffn
  1965. @deffn {Command} reset_config mode_flag ...
  1966. This command displays or modifies the reset configuration
  1967. of your combination of JTAG board and target in target
  1968. configuration scripts.
  1969. Information earlier in this section describes the kind of problems
  1970. the command is intended to address (@pxref{SRST and TRST Issues}).
  1971. As a rule this command belongs only in board config files,
  1972. describing issues like @emph{board doesn't connect TRST};
  1973. or in user config files, addressing limitations derived
  1974. from a particular combination of interface and board.
  1975. (An unlikely example would be using a TRST-only adapter
  1976. with a board that only wires up SRST.)
  1977. The @var{mode_flag} options can be specified in any order, but only one
  1978. of each type -- @var{signals}, @var{combination},
  1979. @var{gates},
  1980. @var{trst_type},
  1981. and @var{srst_type} -- may be specified at a time.
  1982. If you don't provide a new value for a given type, its previous
  1983. value (perhaps the default) is unchanged.
  1984. For example, this means that you don't need to say anything at all about
  1985. TRST just to declare that if the JTAG adapter should want to drive SRST,
  1986. it must explicitly be driven high (@option{srst_push_pull}).
  1987. @itemize
  1988. @item
  1989. @var{signals} can specify which of the reset signals are connected.
  1990. For example, If the JTAG interface provides SRST, but the board doesn't
  1991. connect that signal properly, then OpenOCD can't use it.
  1992. Possible values are @option{none} (the default), @option{trst_only},
  1993. @option{srst_only} and @option{trst_and_srst}.
  1994. @quotation Tip
  1995. If your board provides SRST and/or TRST through the JTAG connector,
  1996. you must declare that so those signals can be used.
  1997. @end quotation
  1998. @item
  1999. The @var{combination} is an optional value specifying broken reset
  2000. signal implementations.
  2001. The default behaviour if no option given is @option{separate},
  2002. indicating everything behaves normally.
  2003. @option{srst_pulls_trst} states that the
  2004. test logic is reset together with the reset of the system (e.g. Philips
  2005. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  2006. the system is reset together with the test logic (only hypothetical, I
  2007. haven't seen hardware with such a bug, and can be worked around).
  2008. @option{combined} implies both @option{srst_pulls_trst} and
  2009. @option{trst_pulls_srst}.
  2010. @item
  2011. The @var{gates} tokens control flags that describe some cases where
  2012. JTAG may be unvailable during reset.
  2013. @option{srst_gates_jtag} (default)
  2014. indicates that asserting SRST gates the
  2015. JTAG clock. This means that no communication can happen on JTAG
  2016. while SRST is asserted.
  2017. Its converse is @option{srst_nogate}, indicating that JTAG commands
  2018. can safely be issued while SRST is active.
  2019. @end itemize
  2020. The optional @var{trst_type} and @var{srst_type} parameters allow the
  2021. driver mode of each reset line to be specified. These values only affect
  2022. JTAG interfaces with support for different driver modes, like the Amontec
  2023. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  2024. relevant signal (TRST or SRST) is not connected.
  2025. @itemize
  2026. @item
  2027. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  2028. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  2029. Most boards connect this signal to a pulldown, so the JTAG TAPs
  2030. never leave reset unless they are hooked up to a JTAG adapter.
  2031. @item
  2032. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  2033. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  2034. Most boards connect this signal to a pullup, and allow the
  2035. signal to be pulled low by various events including system
  2036. powerup and pressing a reset button.
  2037. @end itemize
  2038. @end deffn
  2039. @section Custom Reset Handling
  2040. @cindex events
  2041. OpenOCD has several ways to help support the various reset
  2042. mechanisms provided by chip and board vendors.
  2043. The commands shown in the previous section give standard parameters.
  2044. There are also @emph{event handlers} associated with TAPs or Targets.
  2045. Those handlers are Tcl procedures you can provide, which are invoked
  2046. at particular points in the reset sequence.
  2047. @emph{When SRST is not an option} you must set
  2048. up a @code{reset-assert} event handler for your target.
  2049. For example, some JTAG adapters don't include the SRST signal;
  2050. and some boards have multiple targets, and you won't always
  2051. want to reset everything at once.
  2052. After configuring those mechanisms, you might still
  2053. find your board doesn't start up or reset correctly.
  2054. For example, maybe it needs a slightly different sequence
  2055. of SRST and/or TRST manipulations, because of quirks that
  2056. the @command{reset_config} mechanism doesn't address;
  2057. or asserting both might trigger a stronger reset, which
  2058. needs special attention.
  2059. Experiment with lower level operations, such as @command{jtag_reset}
  2060. and the @command{jtag arp_*} operations shown here,
  2061. to find a sequence of operations that works.
  2062. @xref{JTAG Commands}.
  2063. When you find a working sequence, it can be used to override
  2064. @command{jtag_init}, which fires during OpenOCD startup
  2065. (@pxref{Configuration Stage});
  2066. or @command{init_reset}, which fires during reset processing.
  2067. You might also want to provide some project-specific reset
  2068. schemes. For example, on a multi-target board the standard
  2069. @command{reset} command would reset all targets, but you
  2070. may need the ability to reset only one target at time and
  2071. thus want to avoid using the board-wide SRST signal.
  2072. @deffn {Overridable Procedure} init_reset mode
  2073. This is invoked near the beginning of the @command{reset} command,
  2074. usually to provide as much of a cold (power-up) reset as practical.
  2075. By default it is also invoked from @command{jtag_init} if
  2076. the scan chain does not respond to pure JTAG operations.
  2077. The @var{mode} parameter is the parameter given to the
  2078. low level reset command (@option{halt},
  2079. @option{init}, or @option{run}), @option{setup},
  2080. or potentially some other value.
  2081. The default implementation just invokes @command{jtag arp_init-reset}.
  2082. Replacements will normally build on low level JTAG
  2083. operations such as @command{jtag_reset}.
  2084. Operations here must not address individual TAPs
  2085. (or their associated targets)
  2086. until the JTAG scan chain has first been verified to work.
  2087. Implementations must have verified the JTAG scan chain before
  2088. they return.
  2089. This is done by calling @command{jtag arp_init}
  2090. (or @command{jtag arp_init-reset}).
  2091. @end deffn
  2092. @deffn Command {jtag arp_init}
  2093. This validates the scan chain using just the four
  2094. standard JTAG signals (TMS, TCK, TDI, TDO).
  2095. It starts by issuing a JTAG-only reset.
  2096. Then it performs checks to verify that the scan chain configuration
  2097. matches the TAPs it can observe.
  2098. Those checks include checking IDCODE values for each active TAP,
  2099. and verifying the length of their instruction registers using
  2100. TAP @code{-ircapture} and @code{-irmask} values.
  2101. If these tests all pass, TAP @code{setup} events are
  2102. issued to all TAPs with handlers for that event.
  2103. @end deffn
  2104. @deffn Command {jtag arp_init-reset}
  2105. This uses TRST and SRST to try resetting
  2106. everything on the JTAG scan chain
  2107. (and anything else connected to SRST).
  2108. It then invokes the logic of @command{jtag arp_init}.
  2109. @end deffn
  2110. @node TAP Declaration
  2111. @chapter TAP Declaration
  2112. @cindex TAP declaration
  2113. @cindex TAP configuration
  2114. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  2115. TAPs serve many roles, including:
  2116. @itemize @bullet
  2117. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
  2118. @item @b{Flash Programing} Some chips program the flash directly via JTAG.
  2119. Others do it indirectly, making a CPU do it.
  2120. @item @b{Program Download} Using the same CPU support GDB uses,
  2121. you can initialize a DRAM controller, download code to DRAM, and then
  2122. start running that code.
  2123. @item @b{Boundary Scan} Most chips support boundary scan, which
  2124. helps test for board assembly problems like solder bridges
  2125. and missing connections
  2126. @end itemize
  2127. OpenOCD must know about the active TAPs on your board(s).
  2128. Setting up the TAPs is the core task of your configuration files.
  2129. Once those TAPs are set up, you can pass their names to code
  2130. which sets up CPUs and exports them as GDB targets,
  2131. probes flash memory, performs low-level JTAG operations, and more.
  2132. @section Scan Chains
  2133. @cindex scan chain
  2134. TAPs are part of a hardware @dfn{scan chain},
  2135. which is daisy chain of TAPs.
  2136. They also need to be added to
  2137. OpenOCD's software mirror of that hardware list,
  2138. giving each member a name and associating other data with it.
  2139. Simple scan chains, with a single TAP, are common in
  2140. systems with a single microcontroller or microprocessor.
  2141. More complex chips may have several TAPs internally.
  2142. Very complex scan chains might have a dozen or more TAPs:
  2143. several in one chip, more in the next, and connecting
  2144. to other boards with their own chips and TAPs.
  2145. You can display the list with the @command{scan_chain} command.
  2146. (Don't confuse this with the list displayed by the @command{targets}
  2147. command, presented in the next chapter.
  2148. That only displays TAPs for CPUs which are configured as
  2149. debugging targets.)
  2150. Here's what the scan chain might look like for a chip more than one TAP:
  2151. @verbatim
  2152. TapName Enabled IdCode Expected IrLen IrCap IrMask
  2153. -- ------------------ ------- ---------- ---------- ----- ----- ------
  2154. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  2155. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  2156. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  2157. @end verbatim
  2158. OpenOCD can detect some of that information, but not all
  2159. of it. @xref{Autoprobing}.
  2160. Unfortunately those TAPs can't always be autoconfigured,
  2161. because not all devices provide good support for that.
  2162. JTAG doesn't require supporting IDCODE instructions, and
  2163. chips with JTAG routers may not link TAPs into the chain
  2164. until they are told to do so.
  2165. The configuration mechanism currently supported by OpenOCD
  2166. requires explicit configuration of all TAP devices using
  2167. @command{jtag newtap} commands, as detailed later in this chapter.
  2168. A command like this would declare one tap and name it @code{chip1.cpu}:
  2169. @example
  2170. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  2171. @end example
  2172. Each target configuration file lists the TAPs provided
  2173. by a given chip.
  2174. Board configuration files combine all the targets on a board,
  2175. and so forth.
  2176. Note that @emph{the order in which TAPs are declared is very important.}
  2177. It must match the order in the JTAG scan chain, both inside
  2178. a single chip and between them.
  2179. @xref{FAQ TAP Order}.
  2180. For example, the ST Microsystems STR912 chip has
  2181. three separate TAPs@footnote{See the ST
  2182. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  2183. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  2184. @url{}}.
  2185. To configure those taps, @file{target/str912.cfg}
  2186. includes commands something like this:
  2187. @example
  2188. jtag newtap str912 flash ... params ...
  2189. jtag newtap str912 cpu ... params ...
  2190. jtag newtap str912 bs ... params ...
  2191. @end example
  2192. Actual config files use a variable instead of literals like
  2193. @option{str912}, to support more than one chip of each type.
  2194. @xref{Config File Guidelines}.
  2195. @deffn Command {jtag names}
  2196. Returns the names of all current TAPs in the scan chain.
  2197. Use @command{jtag cget} or @command{jtag tapisenabled}
  2198. to examine attributes and state of each TAP.
  2199. @example
  2200. foreach t [jtag names] @{
  2201. puts [format "TAP: %s\n" $t]
  2202. @}
  2203. @end example
  2204. @end deffn
  2205. @deffn Command {scan_chain}
  2206. Displays the TAPs in the scan chain configuration,
  2207. and their status.
  2208. The set of TAPs listed by this command is fixed by
  2209. exiting the OpenOCD configuration stage,
  2210. but systems with a JTAG router can
  2211. enable or disable TAPs dynamically.
  2212. @end deffn
  2213. @c FIXME! "jtag cget" should be able to return all TAP
  2214. @c attributes, like "$target_name cget" does for targets.
  2215. @c Probably want "jtag eventlist", and a "tap-reset" event
  2216. @c (on entry to RESET state).
  2217. @section TAP Names
  2218. @cindex dotted name
  2219. When TAP objects are declared with @command{jtag newtap},
  2220. a @dfn{} is created for the TAP, combining the
  2221. name of a module (usually a chip) and a label for the TAP.
  2222. For example: @code{xilinx.tap}, @code{str912.flash},
  2223. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  2224. Many other commands use that to manipulate or
  2225. refer to the TAP. For example, CPU configuration uses the
  2226. name, as does declaration of NAND or NOR flash banks.
  2227. The components of a dotted name should follow ``C'' symbol
  2228. name rules: start with an alphabetic character, then numbers
  2229. and underscores are OK; while others (including dots!) are not.
  2230. @quotation Tip
  2231. In older code, JTAG TAPs were numbered from 0..N.
  2232. This feature is still present.
  2233. However its use is highly discouraged, and
  2234. should not be relied on; it will be removed by mid-2010.
  2235. Update all of your scripts to use TAP names rather than numbers,
  2236. by paying attention to the runtime warnings they trigger.
  2237. Using TAP numbers in target configuration scripts prevents
  2238. reusing those scripts on boards with multiple targets.
  2239. @end quotation
  2240. @section TAP Declaration Commands
  2241. @c shouldn't this be(come) a {Config Command}?
  2242. @anchor{jtag newtap}
  2243. @deffn Command {jtag newtap} chipname tapname configparams...
  2244. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  2245. and configured according to the various @var{configparams}.
  2246. The @var{chipname} is a symbolic name for the chip.
  2247. Conventionally target config files use @code{$_CHIPNAME},
  2248. defaulting to the model name given by the chip vendor but
  2249. overridable.
  2250. @cindex TAP naming convention
  2251. The @var{tapname} reflects the role of that TAP,
  2252. and should follow this convention:
  2253. @itemize @bullet
  2254. @item @code{bs} -- For boundary scan if this is a seperate TAP;
  2255. @item @code{cpu} -- The main CPU of the chip, alternatively
  2256. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  2257. @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
  2258. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  2259. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  2260. @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
  2261. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  2262. @item @code{tap} -- Should be used only FPGA or CPLD like devices
  2263. with a single TAP;
  2264. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  2265. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  2266. For example, the Freescale IMX31 has a SDMA (Smart DMA) with
  2267. a JTAG TAP; that TAP should be named @code{sdma}.
  2268. @end itemize
  2269. Every TAP requires at least the following @var{configparams}:
  2270. @itemize @bullet
  2271. @item @code{-irlen} @var{NUMBER}
  2272. @*The length in bits of the
  2273. instruction register, such as 4 or 5 bits.
  2274. @end itemize
  2275. A TAP may also provide optional @var{configparams}:
  2276. @itemize @bullet
  2277. @item @code{-disable} (or @code{-enable})
  2278. @*Use the @code{-disable} parameter to flag a TAP which is not
  2279. linked in to the scan chain after a reset using either TRST
  2280. or the JTAG state machine's @sc{reset} state.
  2281. You may use @code{-enable} to highlight the default state
  2282. (the TAP is linked in).
  2283. @xref{Enabling and Disabling TAPs}.
  2284. @item @code{-expected-id} @var{number}
  2285. @*A non-zero @var{number} represents a 32-bit IDCODE
  2286. which you expect to find when the scan chain is examined.
  2287. These codes are not required by all JTAG devices.
  2288. @emph{Repeat the option} as many times as required if more than one
  2289. ID code could appear (for example, multiple versions).
  2290. Specify @var{number} as zero to suppress warnings about IDCODE
  2291. values that were found but not included in the list.
  2292. Provide this value if at all possible, since it lets OpenOCD
  2293. tell when the scan chain it sees isn't right. These values
  2294. are provided in vendors' chip documentation, usually a technical
  2295. reference manual. Sometimes you may need to probe the JTAG
  2296. hardware to find these values.
  2297. @xref{Autoprobing}.
  2298. @item @code{-ignore-version}
  2299. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  2300. option. When vendors put out multiple versions of a chip, or use the same
  2301. JTAG-level ID for several largely-compatible chips, it may be more practical
  2302. to ignore the version field than to update config files to handle all of
  2303. the various chip IDs.
  2304. @item @code{-ircapture} @var{NUMBER}
  2305. @*The bit pattern loaded by the TAP into the JTAG shift register
  2306. on entry to the @sc{ircapture} state, such as 0x01.
  2307. JTAG requires the two LSBs of this value to be 01.
  2308. By default, @code{-ircapture} and @code{-irmask} are set
  2309. up to verify that two-bit value. You may provide
  2310. additional bits, if you know them, or indicate that
  2311. a TAP doesn't conform to the JTAG specification.
  2312. @item @code{-irmask} @var{NUMBER}
  2313. @*A mask used with @code{-ircapture}
  2314. to verify that instruction scans work correctly.
  2315. Such scans are not used by OpenOCD except to verify that
  2316. there seems to be no problems with JTAG scan chain operations.
  2317. @end itemize
  2318. @end deffn
  2319. @section Other TAP commands
  2320. @deffn Command {jtag cget} @option{-event} name
  2321. @deffnx Command {jtag configure} @option{-event} name string
  2322. At this writing this TAP attribute
  2323. mechanism is used only for event handling.
  2324. (It is not a direct analogue of the @code{cget}/@code{configure}
  2325. mechanism for debugger targets.)
  2326. See the next section for information about the available events.
  2327. The @code{configure} subcommand assigns an event handler,
  2328. a TCL string which is evaluated when the event is triggered.
  2329. The @code{cget} subcommand returns that handler.
  2330. @end deffn
  2331. @anchor{TAP Events}
  2332. @section TAP Events
  2333. @cindex events
  2334. @cindex TAP events
  2335. OpenOCD includes two event mechanisms.
  2336. The one presented here applies to all JTAG TAPs.
  2337. The other applies to debugger targets,
  2338. which are associated with certain TAPs.
  2339. The TAP events currently defined are:
  2340. @itemize @bullet
  2341. @item @b{post-reset}
  2342. @* The TAP has just completed a JTAG reset.
  2343. The tap may still be in the JTAG @sc{reset} state.
  2344. Handlers for these events might perform initialization sequences
  2345. such as issuing TCK cycles, TMS sequences to ensure
  2346. exit from the ARM SWD mode, and more.
  2347. Because the scan chain has not yet been verified, handlers for these events
  2348. @emph{should not issue commands which scan the JTAG IR or DR registers}
  2349. of any particular target.
  2350. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  2351. @item @b{setup}
  2352. @* The scan chain has been reset and verified.
  2353. This handler may enable TAPs as needed.
  2354. @item @b{tap-disable}
  2355. @* The TAP needs to be disabled. This handler should
  2356. implement @command{jtag tapdisable}
  2357. by issuing the relevant JTAG commands.
  2358. @item @b{tap-enable}
  2359. @* The TAP needs to be enabled. This handler should
  2360. implement @command{jtag tapenable}
  2361. by issuing the relevant JTAG commands.
  2362. @end itemize
  2363. If you need some action after each JTAG reset, which isn't actually
  2364. specific to any TAP (since you can't yet trust the scan chain's
  2365. contents to be accurate), you might:
  2366. @example
  2367. jtag configure CHIP.jrc -event post-reset @{
  2368. echo "JTAG Reset done"
  2369. ... non-scan jtag operations to be done after reset
  2370. @}
  2371. @end example
  2372. @anchor{Enabling and Disabling TAPs}
  2373. @section Enabling and Disabling TAPs
  2374. @cindex JTAG Route Controller
  2375. @cindex jrc
  2376. In some systems, a @dfn{JTAG Route Controller} (JRC)
  2377. is used to enable and/or disable specific JTAG TAPs.
  2378. Many ARM based chips from Texas Instruments include
  2379. an ``ICEpick'' module, which is a JRC.
  2380. Such chips include DaVinci and OMAP3 processors.
  2381. A given TAP may not be visible until the JRC has been
  2382. told to link it into the scan chain; and if the JRC
  2383. has been told to unlink that TAP, it will no longer
  2384. be visible.
  2385. Such routers address problems that JTAG ``bypass mode''
  2386. ignores, such as:
  2387. @itemize
  2388. @item The scan chain can only go as fast as its slowest TAP.
  2389. @item Having many TAPs slows instruction scans, since all
  2390. TAPs receive new instructions.
  2391. @item TAPs in the scan chain must be powered up, which wastes
  2392. power and prevents debugging some power management mechanisms.
  2393. @end itemize
  2394. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  2395. as implied by the existence of JTAG routers.
  2396. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  2397. does include a kind of JTAG router functionality.
  2398. @c (a) currently the event handlers don't seem to be able to
  2399. @c fail in a way that could lead to no-change-of-state.
  2400. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  2401. shown below, and is implemented using TAP event handlers.
  2402. So for example, when defining a TAP for a CPU connected to
  2403. a JTAG router, your @file{target.cfg} file
  2404. should define TAP event handlers using
  2405. code that looks something like this:
  2406. @example
  2407. jtag configure CHIP.cpu -event tap-enable @{
  2408. ... jtag operations using CHIP.jrc
  2409. @}
  2410. jtag configure CHIP.cpu -event tap-disable @{
  2411. ... jtag operations using CHIP.jrc
  2412. @}
  2413. @end example
  2414. Then you might want that CPU's TAP enabled almost all the time:
  2415. @example
  2416. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  2417. @end example
  2418. Note how that particular setup event handler declaration
  2419. uses quotes to evaluate @code{$CHIP} when the event is configured.
  2420. Using brackets @{ @} would cause it to be evaluated later,
  2421. at runtime, when it might have a different value.
  2422. @deffn Command {jtag tapdisable}
  2423. If necessary, disables the tap
  2424. by sending it a @option{tap-disable} event.
  2425. Returns the string "1" if the tap
  2426. specified by @var{} is enabled,
  2427. and "0" if it is disabled.
  2428. @end deffn
  2429. @deffn Command {jtag tapenable}
  2430. If necessary, enables the tap
  2431. by sending it a @option{tap-enable} event.
  2432. Returns the string "1" if the tap
  2433. specified by @var{} is enabled,
  2434. and "0" if it is disabled.
  2435. @end deffn
  2436. @deffn Command {jtag tapisenabled}
  2437. Returns the string "1" if the tap
  2438. specified by @var{} is enabled,
  2439. and "0" if it is disabled.
  2440. @quotation Note
  2441. Humans will find the @command{scan_chain} command more helpful
  2442. for querying the state of the JTAG taps.
  2443. @end quotation
  2444. @end deffn
  2445. @anchor{Autoprobing}
  2446. @section Autoprobing
  2447. @cindex autoprobe
  2448. @cindex JTAG autoprobe
  2449. TAP configuration is the first thing that needs to be done
  2450. after interface and reset configuration. Sometimes it's
  2451. hard finding out what TAPs exist, or how they are identified.
  2452. Vendor documentation is not always easy to find and use.
  2453. To help you get past such problems, OpenOCD has a limited
  2454. @emph{autoprobing} ability to look at the scan chain, doing
  2455. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  2456. To use this mechanism, start the OpenOCD server with only data
  2457. that configures your JTAG interface, and arranges to come up
  2458. with a slow clock (many devices don't support fast JTAG clocks
  2459. right when they come out of reset).
  2460. For example, your @file{openocd.cfg} file might have:
  2461. @example
  2462. source [find interface/olimex-arm-usb-tiny-h.cfg]
  2463. reset_config trst_and_srst
  2464. jtag_rclk 8
  2465. @end example
  2466. When you start the server without any TAPs configured, it will
  2467. attempt to autoconfigure the TAPs. There are two parts to this:
  2468. @enumerate
  2469. @item @emph{TAP discovery} ...
  2470. After a JTAG reset (sometimes a system reset may be needed too),
  2471. each TAP's data registers will hold the contents of either the
  2472. IDCODE or BYPASS register.
  2473. If JTAG communication is working, OpenOCD will see each TAP,
  2474. and report what @option{-expected-id} to use with it.
  2475. @item @emph{IR Length discovery} ...
  2476. Unfortunately JTAG does not provide a reliable way to find out
  2477. the value of the @option{-irlen} parameter to use with a TAP
  2478. that is discovered.
  2479. If OpenOCD can discover the length of a TAP's instruction
  2480. register, it will report it.
  2481. Otherwise you may need to consult vendor documentation, such
  2482. as chip data sheets or BSDL files.
  2483. @end enumerate
  2484. In many cases your board will have a simple scan chain with just
  2485. a single device. Here's what OpenOCD reported with one board
  2486. that's a bit more complex:
  2487. @example
  2488. clock speed 8 kHz
  2489. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  2490. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  2491. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  2492. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  2493. AUTO auto0.tap - use "... -irlen 4"
  2494. AUTO auto1.tap - use "... -irlen 4"
  2495. AUTO auto2.tap - use "... -irlen 6"
  2496. no gdb ports allocated as no target has been specified
  2497. @end example
  2498. Given that information, you should be able to either find some existing
  2499. config files to use, or create your own. If you create your own, you
  2500. would configure from the bottom up: first a @file{target.cfg} file
  2501. with these TAPs, any targets associated with them, and any on-chip
  2502. resources; then a @file{board.cfg} with off-chip resources, clocking,
  2503. and so forth.
  2504. @node CPU Configuration
  2505. @chapter CPU Configuration
  2506. @cindex GDB target
  2507. This chapter discusses how to set up GDB debug targets for CPUs.
  2508. You can also access these targets without GDB
  2509. (@pxref{Architecture and Core Commands},
  2510. and @ref{Target State handling}) and
  2511. through various kinds of NAND and NOR flash commands.
  2512. If you have multiple CPUs you can have multiple such targets.
  2513. We'll start by looking at how to examine the targets you have,
  2514. then look at how to add one more target and how to configure it.
  2515. @section Target List
  2516. @cindex target, current
  2517. @cindex target, list
  2518. All targets that have been set up are part of a list,
  2519. where each member has a name.
  2520. That name should normally be the same as the TAP name.
  2521. You can display the list with the @command{targets}
  2522. (plural!) command.
  2523. This display often has only one CPU; here's what it might
  2524. look like with more than one:
  2525. @verbatim
  2526. TargetName Type Endian TapName State
  2527. -- ------------------ ---------- ------ ------------------ ------------
  2528. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  2529. 1 MyTarget cortex_m3 little tap-disabled
  2530. @end verbatim
  2531. One member of that list is the @dfn{current target}, which
  2532. is implicitly referenced by many commands.
  2533. It's the one marked with a @code{*} near the target name.
  2534. In particular, memory addresses often refer to the address
  2535. space seen by that current target.
  2536. Commands like @command{mdw} (memory display words)
  2537. and @command{flash erase_address} (erase NOR flash blocks)
  2538. are examples; and there are many more.
  2539. Several commands let you examine the list of targets:
  2540. @deffn Command {target count}
  2541. @emph{Note: target numbers are deprecated; don't use them.
  2542. They will be removed shortly after August 2010, including this command.
  2543. Iterate target using @command{target names}, not by counting.}
  2544. Returns the number of targets, @math{N}.
  2545. The highest numbered target is @math{N - 1}.
  2546. @example
  2547. set c [target count]
  2548. for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
  2549. # Assuming you have created this function
  2550. print_target_details $x
  2551. @}
  2552. @end example
  2553. @end deffn
  2554. @deffn Command {target current}
  2555. Returns the name of the current target.
  2556. @end deffn
  2557. @deffn Command {target names}
  2558. Lists the names of all current targets in the list.
  2559. @example
  2560. foreach t [target names] @{
  2561. puts [format "Target: %s\n" $t]
  2562. @}
  2563. @end example
  2564. @end deffn
  2565. @deffn Command {target number} number
  2566. @emph{Note: target numbers are deprecated; don't use them.
  2567. They will be removed shortly after August 2010, including this command.}
  2568. The list of targets is numbered starting at zero.
  2569. This command returns the name of the target at index @var{number}.
  2570. @example
  2571. set thename [target number $x]
  2572. puts [format "Target %d is: %s\n" $x $thename]
  2573. @end example
  2574. @end deffn
  2575. @c yep, "target list" would have been better.
  2576. @c plus maybe "target setdefault".
  2577. @deffn Command targets [name]
  2578. @emph{Note: the name of this command is plural. Other target
  2579. command names are singular.}
  2580. With no parameter, this command displays a table of all known
  2581. targets in a user friendly form.
  2582. With a parameter, this command sets the current target to
  2583. the given target with the given @var{name}; this is
  2584. only relevant on boards which have more than one target.
  2585. @end deffn
  2586. @section Target CPU Types and Variants
  2587. @cindex target type
  2588. @cindex CPU type
  2589. @cindex CPU variant
  2590. Each target has a @dfn{CPU type}, as shown in the output of
  2591. the @command{targets} command. You need to specify that type
  2592. when calling @command{target create}.
  2593. The CPU type indicates more than just the instruction set.
  2594. It also indicates how that instruction set is implemented,
  2595. what kind of debug support it integrates,
  2596. whether it has an MMU (and if so, what kind),
  2597. what core-specific commands may be available
  2598. (@pxref{Architecture and Core Commands}),
  2599. and more.
  2600. For some CPU types, OpenOCD also defines @dfn{variants} which
  2601. indicate differences that affect their handling.
  2602. For example, a particular implementation bug might need to be
  2603. worked around in some chip versions.
  2604. It's easy to see what target types are supported,
  2605. since there's a command to list them.
  2606. However, there is currently no way to list what target variants
  2607. are supported (other than by reading the OpenOCD source code).
  2608. @anchor{target types}
  2609. @deffn Command {target types}
  2610. Lists all supported target types.
  2611. At this writing, the supported CPU types and variants are:
  2612. @itemize @bullet
  2613. @item @code{arm11} -- this is a generation of ARMv6 cores
  2614. @item @code{arm720t} -- this is an ARMv4 core with an MMU
  2615. @item @code{arm7tdmi} -- this is an ARMv4 core
  2616. @item @code{arm920t} -- this is an ARMv5 core with an MMU
  2617. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
  2618. @item @code{arm966e} -- this is an ARMv5 core
  2619. @item @code{arm9tdmi} -- this is an ARMv4 core
  2620. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  2621. (Support for this is preliminary and incomplete.)
  2622. @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
  2623. @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
  2624. compact Thumb2 instruction set. It supports one variant:
  2625. @itemize @minus
  2626. @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
  2627. This will cause OpenOCD to use a software reset rather than asserting
  2628. SRST, to avoid a issue with clearing the debug registers.
  2629. This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
  2630. be detected and the normal reset behaviour used.
  2631. @end itemize
  2632. @item @code{dragonite} -- resembles arm966e
  2633. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  2634. (Support for this is still incomplete.)
  2635. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  2636. @item @code{feroceon} -- resembles arm926
  2637. @item @code{mips_m4k} -- a MIPS core. This supports one variant:
  2638. @itemize @minus
  2639. @item @code{ejtag_srst} ... Use this when debugging targets that do not
  2640. provide a functional SRST line on the EJTAG connector. This causes
  2641. OpenOCD to instead use an EJTAG software reset command to reset the
  2642. processor.
  2643. You still need to enable @option{srst} on the @command{reset_config}
  2644. command to enable OpenOCD hardware reset functionality.
  2645. @end itemize
  2646. @item @code{xscale} -- this is actually an architecture,
  2647. not a CPU type. It is based on the ARMv5 architecture.
  2648. There are several variants defined:
  2649. @itemize @minus
  2650. @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
  2651. @code{pxa27x} ... instruction register length is 7 bits
  2652. @item @code{pxa250}, @code{pxa255},
  2653. @code{pxa26x} ... instruction register length is 5 bits
  2654. @item @code{pxa3xx} ... instruction register length is 11 bits
  2655. @end itemize
  2656. @end itemize
  2657. @end deffn
  2658. To avoid being confused by the variety of ARM based cores, remember
  2659. this key point: @emph{ARM is a technology licencing company}.
  2660. (See: @url{}.)
  2661. The CPU name used by OpenOCD will reflect the CPU design that was
  2662. licenced, not a vendor brand which incorporates that design.
  2663. Name prefixes like arm7, arm9, arm11, and cortex
  2664. reflect design generations;
  2665. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  2666. reflect an architecture version implemented by a CPU design.
  2667. @anchor{Target Configuration}
  2668. @section Target Configuration
  2669. Before creating a ``target'', you must have added its TAP to the scan chain.
  2670. When you've added that TAP, you will have a @code{}
  2671. which is used to set up the CPU support.
  2672. The chip-specific configuration file will normally configure its CPU(s)
  2673. right after it adds all of the chip's TAPs to the scan chain.
  2674. Although you can set up a target in one step, it's often clearer if you
  2675. use shorter commands and do it in two steps: create it, then configure
  2676. optional parts.
  2677. All operations on the target after it's created will use a new
  2678. command, created as part of target creation.
  2679. The two main things to configure after target creation are
  2680. a work area, which usually has target-specific defaults even
  2681. if the board setup code overrides them later;
  2682. and event handlers (@pxref{Target Events}), which tend
  2683. to be much more board-specific.
  2684. The key steps you use might look something like this
  2685. @example
  2686. target create MyTarget cortex_m3 -chain-position mychip.cpu
  2687. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  2688. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  2689. $MyTarget configure -event reset-init @{ myboard_reinit @}
  2690. @end example
  2691. You should specify a working area if you can; typically it uses some
  2692. on-chip SRAM.
  2693. Such a working area can speed up many things, including bulk
  2694. writes to target memory;
  2695. flash operations like checking to see if memory needs to be erased;
  2696. GDB memory checksumming;
  2697. and more.
  2698. @quotation Warning
  2699. On more complex chips, the work area can become
  2700. inaccessible when application code
  2701. (such as an operating system)
  2702. enables or disables the MMU.
  2703. For example, the particular MMU context used to acess the virtual
  2704. address will probably matter ... and that context might not have
  2705. easy access to other addresses needed.
  2706. At this writing, OpenOCD doesn't have much MMU intelligence.
  2707. @end quotation
  2708. It's often very useful to define a @code{reset-init} event handler.
  2709. For systems that are normally used with a boot loader,
  2710. common tasks include updating clocks and initializing memory
  2711. controllers.
  2712. That may be needed to let you write the boot loader into flash,
  2713. in order to ``de-brick'' your board; or to load programs into
  2714. external DDR memory without having run the boot loader.
  2715. @deffn Command {target create} target_name type configparams...
  2716. This command creates a GDB debug target that refers to a specific JTAG tap.
  2717. It enters that target into a list, and creates a new
  2718. command (@command{@var{target_name}}) which is used for various
  2719. purposes including additional configuration.
  2720. @itemize @bullet
  2721. @item @var{target_name} ... is the name of the debug target.
  2722. By convention this should be the same as the @emph{}
  2723. of the TAP associated with this target, which must be specified here
  2724. using the @code{-chain-position @var{}} configparam.
  2725. This name is also used to create the target object command,
  2726. referred to here as @command{$target_name},
  2727. and in other places the target needs to be identified.
  2728. @item @var{type} ... specifies the target type. @xref{target types}.
  2729. @item @var{configparams} ... all parameters accepted by
  2730. @command{$target_name configure} are permitted.
  2731. If the target is big-endian, set it here with @code{-endian big}.
  2732. If the variant matters, set it here with @code{-variant}.
  2733. You @emph{must} set the @code{-chain-position @var{}} here.
  2734. @end itemize
  2735. @end deffn
  2736. @deffn Command {$target_name configure} configparams...
  2737. The options accepted by this command may also be
  2738. specified as parameters to @command{target create}.
  2739. Their values can later be queried one at a time by
  2740. using the @command{$target_name cget} command.
  2741. @emph{Warning:} changing some of these after setup is dangerous.
  2742. For example, moving a target from one TAP to another;
  2743. and changing its endianness or variant.
  2744. @itemize @bullet
  2745. @item @code{-chain-position} @var{} -- names the TAP
  2746. used to access this target.
  2747. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  2748. whether the CPU uses big or little endian conventions
  2749. @item @code{-event} @var{event_name} @var{event_body} --
  2750. @xref{Target Events}.
  2751. Note that this updates a list of named event handlers.
  2752. Calling this twice with two different event names assigns
  2753. two different handlers, but calling it twice with the
  2754. same event name assigns only one handler.
  2755. @item @code{-variant} @var{name} -- specifies a variant of the target,
  2756. which OpenOCD needs to know about.
  2757. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  2758. whether the work area gets backed up; by default,
  2759. @emph{it is not backed up.}
  2760. When possible, use a working_area that doesn't need to be backed up,
  2761. since performing a backup slows down operations.
  2762. For example, the beginning of an SRAM block is likely to
  2763. be used by most build systems, but the end is often unused.
  2764. @item @code{-work-area-size} @var{size} -- specify work are size,
  2765. in bytes. The same size applies regardless of whether its physical
  2766. or virtual address is being used.
  2767. @item @code{-work-area-phys} @var{address} -- set the work area
  2768. base @var{address} to be used when no MMU is active.
  2769. @item @code{-work-area-virt} @var{address} -- set the work area
  2770. base @var{address} to be used when an MMU is active.
  2771. @emph{Do not specify a value for this except on targets with an MMU.}
  2772. The value should normally correspond to a static mapping for the
  2773. @code{-work-area-phys} address, set up by the current operating system.
  2774. @end itemize
  2775. @end deffn
  2776. @section Other $target_name Commands
  2777. @cindex object command
  2778. The Tcl/Tk language has the concept of object commands,
  2779. and OpenOCD adopts that same model for targets.
  2780. A good Tk example is a on screen button.
  2781. Once a button is created a button
  2782. has a name (a path in Tk terms) and that name is useable as a first
  2783. class command. For example in Tk, one can create a button and later
  2784. configure it like this:
  2785. @example
  2786. # Create
  2787. button .foobar -background red -command @{ foo @}
  2788. # Modify
  2789. .foobar configure -foreground blue
  2790. # Query
  2791. set x [.foobar cget -background]
  2792. # Report
  2793. puts [format "The button is %s" $x]
  2794. @end example
  2795. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  2796. button, and its object commands are invoked the same way.
  2797. @example
  2798. str912.cpu mww 0x1234 0x42
  2799. omap3530.cpu mww 0x5555 123
  2800. @end example
  2801. The commands supported by OpenOCD target objects are:
  2802. @deffn Command {$target_name arp_examine}
  2803. @deffnx Command {$target_name arp_halt}
  2804. @deffnx Command {$target_name arp_poll}
  2805. @deffnx Command {$target_name arp_reset}
  2806. @deffnx Command {$target_name arp_waitstate}
  2807. Internal OpenOCD scripts (most notably @file{startup.tcl})
  2808. use these to deal with specific reset cases.
  2809. They are not otherwise documented here.
  2810. @end deffn
  2811. @deffn Command {$target_name array2mem} arrayname width address count
  2812. @deffnx Command {$target_name mem2array} arrayname width address count
  2813. These provide an efficient script-oriented interface to memory.
  2814. The @code{array2mem} primitive writes bytes, halfwords, or words;
  2815. while @code{mem2array} reads them.
  2816. In both cases, the TCL side uses an array, and
  2817. the target side uses raw memory.
  2818. The efficiency comes from enabling the use of
  2819. bulk JTAG data transfer operations.
  2820. The script orientation comes from working with data
  2821. values that are packaged for use by TCL scripts;
  2822. @command{mdw} type primitives only print data they retrieve,
  2823. and neither store nor return those values.
  2824. @itemize
  2825. @item @var{arrayname} ... is the name of an array variable
  2826. @item @var{width} ... is 8/16/32 - indicating the memory access size
  2827. @item @var{address} ... is the target memory address
  2828. @item @var{count} ... is the number of elements to process
  2829. @end itemize
  2830. @end deffn
  2831. @deffn Command {$target_name cget} queryparm
  2832. Each configuration parameter accepted by
  2833. @command{$target_name configure}
  2834. can be individually queried, to return its current value.
  2835. The @var{queryparm} is a parameter name
  2836. accepted by that command, such as @code{-work-area-phys}.
  2837. There are a few special cases:
  2838. @itemize @bullet
  2839. @item @code{-event} @var{event_name} -- returns the handler for the
  2840. event named @var{event_name}.
  2841. This is a special case because setting a handler requires
  2842. two parameters.
  2843. @item @code{-type} -- returns the target type.
  2844. This is a special case because this is set using
  2845. @command{target create} and can't be changed
  2846. using @command{$target_name configure}.
  2847. @end itemize
  2848. For example, if you wanted to summarize information about
  2849. all the targets you might use something like this:
  2850. @example
  2851. foreach name [target names] @{
  2852. set y [$name cget -endian]
  2853. set z [$name cget -type]
  2854. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  2855. $x $name $y $z]
  2856. @}
  2857. @end example
  2858. @end deffn
  2859. @anchor{target curstate}
  2860. @deffn Command {$target_name curstate}
  2861. Displays the current target state:
  2862. @code{debug-running},
  2863. @code{halted},
  2864. @code{reset},
  2865. @code{running}, or @code{unknown}.
  2866. (Also, @pxref{Event Polling}.)
  2867. @end deffn
  2868. @deffn Command {$target_name eventlist}
  2869. Displays a table listing all event handlers
  2870. currently associated with this target.
  2871. @xref{Target Events}.
  2872. @end deffn
  2873. @deffn Command {$target_name invoke-event} event_name
  2874. Invokes the handler for the event named @var{event_name}.
  2875. (This is primarily intended for use by OpenOCD framework
  2876. code, for example by the reset code in @file{startup.tcl}.)
  2877. @end deffn
  2878. @deffn Command {$target_name mdw} addr [count]
  2879. @deffnx Command {$target_name mdh} addr [count]
  2880. @deffnx Command {$target_name mdb} addr [count]
  2881. Display contents of address @var{addr}, as
  2882. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  2883. or 8-bit bytes (@command{mdb}).
  2884. If @var{count} is specified, displays that many units.
  2885. (If you want to manipulate the data instead of displaying it,
  2886. see the @code{mem2array} primitives.)
  2887. @end deffn
  2888. @deffn Command {$target_name mww} addr word
  2889. @deffnx Command {$target_name mwh} addr halfword
  2890. @deffnx Command {$target_name mwb} addr byte
  2891. Writes the specified @var{word} (32 bits),
  2892. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  2893. at the specified address @var{addr}.
  2894. @end deffn
  2895. @anchor{Target Events}
  2896. @section Target Events
  2897. @cindex target events
  2898. @cindex events
  2899. At various times, certain things can happen, or you want them to happen.
  2900. For example:
  2901. @itemize @bullet
  2902. @item What should happen when GDB connects? Should your target reset?
  2903. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  2904. @item Is using SRST appropriate (and possible) on your system?
  2905. Or instead of that, do you need to issue JTAG commands to trigger reset?
  2906. SRST usually resets everything on the scan chain, which can be inappropriate.
  2907. @item During reset, do you need to write to certain memory locations
  2908. to set up system clocks or
  2909. to reconfigure the SDRAM?
  2910. How about configuring the watchdog timer, or other peripherals,
  2911. to stop running while you hold the core stopped for debugging?
  2912. @end itemize
  2913. All of the above items can be addressed by target event handlers.
  2914. These are set up by @command{$target_name configure -event} or
  2915. @command{target create ... -event}.
  2916. The programmer's model matches the @code{-command} option used in Tcl/Tk
  2917. buttons and events. The two examples below act the same, but one creates
  2918. and invokes a small procedure while the other inlines it.
  2919. @example
  2920. proc my_attach_proc @{ @} @{
  2921. echo "Reset..."
  2922. reset halt
  2923. @}
  2924. mychip.cpu configure -event gdb-attach my_attach_proc
  2925. mychip.cpu configure -event gdb-attach @{
  2926. echo "Reset..."
  2927. reset halt
  2928. @}
  2929. @end example
  2930. The following target events are defined:
  2931. @itemize @bullet
  2932. @item @b{debug-halted}
  2933. @* The target has halted for debug reasons (i.e.: breakpoint)
  2934. @item @b{debug-resumed}
  2935. @* The target has resumed (i.e.: gdb said run)
  2936. @item @b{early-halted}
  2937. @* Occurs early in the halt process
  2938. @ignore
  2939. @item @b{examine-end}
  2940. @* Currently not used (goal: when JTAG examine completes)
  2941. @item @b{examine-start}
  2942. @* Currently not used (goal: when JTAG examine starts)
  2943. @end ignore
  2944. @item @b{gdb-attach}
  2945. @* When GDB connects
  2946. @item @b{gdb-detach}
  2947. @* When GDB disconnects
  2948. @item @b{gdb-end}
  2949. @* When the target has halted and GDB is not doing anything (see early halt)
  2950. @item @b{gdb-flash-erase-start}
  2951. @* Before the GDB flash process tries to erase the flash
  2952. @item @b{gdb-flash-erase-end}
  2953. @* After the GDB flash process has finished erasing the flash
  2954. @item @b{gdb-flash-write-start}
  2955. @* Before GDB writes to the flash
  2956. @item @b{gdb-flash-write-end}
  2957. @* After GDB writes to the flash
  2958. @item @b{gdb-start}
  2959. @* Before the target steps, gdb is trying to start/resume the target
  2960. @item @b{halted}
  2961. @* The target has halted
  2962. @ignore
  2963. @item @b{old-gdb_program_config}
  2964. @* DO NOT USE THIS: Used internally
  2965. @item @b{old-pre_resume}
  2966. @* DO NOT USE THIS: Used internally
  2967. @end ignore
  2968. @item @b{reset-assert-pre}
  2969. @* Issued as part of @command{reset} processing
  2970. after @command{reset_init} was triggered
  2971. but before either SRST alone is re-asserted on the scan chain,
  2972. or @code{reset-assert} is triggered.
  2973. @item @b{reset-assert}
  2974. @* Issued as part of @command{reset} processing
  2975. after @command{reset-assert-pre} was triggered.
  2976. When such a handler is present, cores which support this event will use
  2977. it instead of asserting SRST.
  2978. This support is essential for debugging with JTAG interfaces which
  2979. don't include an SRST line (JTAG doesn't require SRST), and for
  2980. selective reset on scan chains that have multiple targets.
  2981. @item @b{reset-assert-post}
  2982. @* Issued as part of @command{reset} processing
  2983. after @code{reset-assert} has been triggered.
  2984. or the target asserted SRST on the entire scan chain.
  2985. @item @b{reset-deassert-pre}
  2986. @* Issued as part of @command{reset} processing
  2987. after @code{reset-assert-post} has been triggered.
  2988. @item @b{reset-deassert-post}
  2989. @* Issued as part of @command{reset} processing
  2990. after @code{reset-deassert-pre} has been triggered
  2991. and (if the target is using it) after SRST has been
  2992. released on the scan chain.
  2993. @item @b{reset-end}
  2994. @* Issued as the final step in @command{reset} processing.
  2995. @ignore
  2996. @item @b{reset-halt-post}
  2997. @* Currently not used
  2998. @item @b{reset-halt-pre}
  2999. @* Currently not used
  3000. @end ignore
  3001. @item @b{reset-init}
  3002. @* Used by @b{reset init} command for board-specific initialization.
  3003. This event fires after @emph{reset-deassert-post}.
  3004. This is where you would configure PLLs and clocking, set up DRAM so
  3005. you can download programs that don't fit in on-chip SRAM, set up pin
  3006. multiplexing, and so on.
  3007. (You may be able to switch to a fast JTAG clock rate here, after
  3008. the target clocks are fully set up.)
  3009. @item @b{reset-start}
  3010. @* Issued as part of @command{reset} processing
  3011. before @command{reset_init} is called.
  3012. This is the most robust place to use @command{jtag_rclk}
  3013. or @command{jtag_khz} to switch to a low JTAG clock rate,
  3014. when reset disables PLLs needed to use a fast clock.
  3015. @ignore
  3016. @item @b{reset-wait-pos}
  3017. @* Currently not used
  3018. @item @b{reset-wait-pre}
  3019. @* Currently not used
  3020. @end ignore
  3021. @item @b{resume-start}
  3022. @* Before any target is resumed
  3023. @item @b{resume-end}
  3024. @* After all targets have resumed
  3025. @item @b{resume-ok}
  3026. @* Success
  3027. @item @b{resumed}
  3028. @* Target has resumed
  3029. @end itemize
  3030. @node Flash Commands
  3031. @chapter Flash Commands
  3032. OpenOCD has different commands for NOR and NAND flash;
  3033. the ``flash'' command works with NOR flash, while
  3034. the ``nand'' command works with NAND flash.
  3035. This partially reflects different hardware technologies:
  3036. NOR flash usually supports direct CPU instruction and data bus access,
  3037. while data from a NAND flash must be copied to memory before it can be
  3038. used. (SPI flash must also be copied to memory before use.)
  3039. However, the documentation also uses ``flash'' as a generic term;
  3040. for example, ``Put flash configuration in board-specific files''.
  3041. Flash Steps:
  3042. @enumerate
  3043. @item Configure via the command @command{flash bank}
  3044. @* Do this in a board-specific configuration file,
  3045. passing parameters as needed by the driver.
  3046. @item Operate on the flash via @command{flash subcommand}
  3047. @* Often commands to manipulate the flash are typed by a human, or run
  3048. via a script in some automated way. Common tasks include writing a
  3049. boot loader, operating system, or other data.
  3050. @item GDB Flashing
  3051. @* Flashing via GDB requires the flash be configured via ``flash
  3052. bank'', and the GDB flash features be enabled.
  3053. @xref{GDB Configuration}.
  3054. @end enumerate
  3055. Many CPUs have the ablity to ``boot'' from the first flash bank.
  3056. This means that misprogramming that bank can ``brick'' a system,
  3057. so that it can't boot.
  3058. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  3059. board by (re)installing working boot firmware.
  3060. @anchor{NOR Configuration}
  3061. @section Flash Configuration Commands
  3062. @cindex flash configuration
  3063. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  3064. Configures a flash bank which provides persistent storage
  3065. for addresses from @math{base} to @math{base + size - 1}.
  3066. These banks will often be visible to GDB through the target's memory map.
  3067. In some cases, configuring a flash bank will activate extra commands;
  3068. see the driver-specific documentation.
  3069. @itemize @bullet
  3070. @item @var{name} ... may be used to reference the flash bank
  3071. in other flash commands.
  3072. @item @var{driver} ... identifies the controller driver
  3073. associated with the flash bank being declared.
  3074. This is usually @code{cfi} for external flash, or else
  3075. the name of a microcontroller with embedded flash memory.
  3076. @xref{Flash Driver List}.
  3077. @item @var{base} ... Base address of the flash chip.
  3078. @item @var{size} ... Size of the chip, in bytes.
  3079. For some drivers, this value is detected from the hardware.
  3080. @item @var{chip_width} ... Width of the flash chip, in bytes;
  3081. ignored for most microcontroller drivers.
  3082. @item @var{bus_width} ... Width of the data bus used to access the
  3083. chip, in bytes; ignored for most microcontroller drivers.
  3084. @item @var{target} ... Names the target used to issue
  3085. commands to the flash controller.
  3086. @comment Actually, it's currently a controller-specific parameter...
  3087. @item @var{driver_options} ... drivers may support, or require,
  3088. additional parameters. See the driver-specific documentation
  3089. for more information.
  3090. @end itemize
  3091. @quotation Note
  3092. This command is not available after OpenOCD initialization has completed.
  3093. Use it in board specific configuration files, not interactively.
  3094. @end quotation
  3095. @end deffn
  3096. @comment the REAL name for this command is "ocd_flash_banks"
  3097. @comment less confusing would be: "flash list" (like "nand list")
  3098. @deffn Command {flash banks}
  3099. Prints a one-line summary of each device that was
  3100. declared using @command{flash bank}, numbered from zero.
  3101. Note that this is the @emph{plural} form;
  3102. the @emph{singular} form is a very different command.
  3103. @end deffn
  3104. @deffn Command {flash list}
  3105. Retrieves a list of associative arrays for each device that was
  3106. declared using @command{flash bank}, numbered from zero.
  3107. This returned list can be manipulated easily from within scripts.
  3108. @end deffn
  3109. @deffn Command {flash probe} num
  3110. Identify the flash, or validate the parameters of the configured flash. Operation
  3111. depends on the flash type.
  3112. The @var{num} parameter is a value shown by @command{flash banks}.
  3113. Most flash commands will implicitly @emph{autoprobe} the bank;
  3114. flash drivers can distinguish between probing and autoprobing,
  3115. but most don't bother.
  3116. @end deffn
  3117. @section Erasing, Reading, Writing to Flash
  3118. @cindex flash erasing
  3119. @cindex flash reading
  3120. @cindex flash writing
  3121. @cindex flash programming
  3122. One feature distinguishing NOR flash from NAND or serial flash technologies
  3123. is that for read access, it acts exactly like any other addressible memory.
  3124. This means you can use normal memory read commands like @command{mdw} or
  3125. @command{dump_image} with it, with no special @command{flash} subcommands.
  3126. @xref{Memory access}, and @ref{Image access}.
  3127. Write access works differently. Flash memory normally needs to be erased
  3128. before it's written. Erasing a sector turns all of its bits to ones, and
  3129. writing can turn ones into zeroes. This is why there are special commands
  3130. for interactive erasing and writing, and why GDB needs to know which parts
  3131. of the address space hold NOR flash memory.
  3132. @quotation Note
  3133. Most of these erase and write commands leverage the fact that NOR flash
  3134. chips consume target address space. They implicitly refer to the current
  3135. JTAG target, and map from an address in that target's address space
  3136. back to a flash bank.
  3137. @comment In May 2009, those mappings may fail if any bank associated
  3138. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  3139. A few commands use abstract addressing based on bank and sector numbers,
  3140. and don't depend on searching the current target and its address space.
  3141. Avoid confusing the two command models.
  3142. @end quotation
  3143. Some flash chips implement software protection against accidental writes,
  3144. since such buggy writes could in some cases ``brick'' a system.
  3145. For such systems, erasing and writing may require sector protection to be
  3146. disabled first.
  3147. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  3148. and AT91SAM7 on-chip flash.
  3149. @xref{flash protect}.
  3150. @anchor{flash erase_sector}
  3151. @deffn Command {flash erase_sector} num first last
  3152. Erase sectors in bank @var{num}, starting at sector @var{first}
  3153. up to and including @var{last}.
  3154. Sector numbering starts at 0.
  3155. Providing a @var{last} sector of @option{last}
  3156. specifies "to the end of the flash bank".
  3157. The @var{num} parameter is a value shown by @command{flash banks}.
  3158. @end deffn
  3159. @deffn Command {flash erase_address} address length
  3160. Erase sectors starting at @var{address} for @var{length} bytes.
  3161. The flash bank to use is inferred from the @var{address}, and
  3162. the specified length must stay within that bank.
  3163. As a special case, when @var{length} is zero and @var{address} is
  3164. the start of the bank, the whole flash is erased.
  3165. @end deffn
  3166. @deffn Command {flash fillw} address word length
  3167. @deffnx Command {flash fillh} address halfword length
  3168. @deffnx Command {flash fillb} address byte length
  3169. Fills flash memory with the specified @var{word} (32 bits),
  3170. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3171. starting at @var{address} and continuing
  3172. for @var{length} units (word/halfword/byte).
  3173. No erasure is done before writing; when needed, that must be done
  3174. before issuing this command.
  3175. Writes are done in blocks of up to 1024 bytes, and each write is
  3176. verified by reading back the data and comparing it to what was written.
  3177. The flash bank to use is inferred from the @var{address} of
  3178. each block, and the specified length must stay within that bank.
  3179. @end deffn
  3180. @comment no current checks for errors if fill blocks touch multiple banks!
  3181. @anchor{flash write_bank}
  3182. @deffn Command {flash write_bank} num filename offset
  3183. Write the binary @file{filename} to flash bank @var{num},
  3184. starting at @var{offset} bytes from the beginning of the bank.
  3185. The @var{num} parameter is a value shown by @command{flash banks}.
  3186. @end deffn
  3187. @anchor{flash write_image}
  3188. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  3189. Write the image @file{filename} to the current target's flash bank(s).
  3190. A relocation @var{offset} may be specified, in which case it is added
  3191. to the base address for each section in the image.
  3192. The file [@var{type}] can be specified
  3193. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  3194. @option{elf} (ELF file), @option{s19} (Motorola s19).
  3195. @option{mem}, or @option{builder}.
  3196. The relevant flash sectors will be erased prior to programming
  3197. if the @option{erase} parameter is given. If @option{unlock} is
  3198. provided, then the flash banks are unlocked before erase and
  3199. program. The flash bank to use is inferred from the @var{address} of
  3200. each image segment.
  3201. @end deffn
  3202. @section Other Flash commands
  3203. @cindex flash protection
  3204. @deffn Command {flash erase_check} num
  3205. Check erase state of sectors in flash bank @var{num},
  3206. and display that status.
  3207. The @var{num} parameter is a value shown by @command{flash banks}.
  3208. This is the only operation that
  3209. updates the erase state information displayed by @option{flash info}. That means you have
  3210. to issue a @command{flash erase_check} command after erasing or programming the device
  3211. to get updated information.
  3212. (Code execution may have invalidated any state records kept by OpenOCD.)
  3213. @end deffn
  3214. @deffn Command {flash info} num
  3215. Print info about flash bank @var{num}
  3216. The @var{num} parameter is a value shown by @command{flash banks}.
  3217. The information includes per-sector protect status.
  3218. @end deffn
  3219. @anchor{flash protect}
  3220. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  3221. Enable (@option{on}) or disable (@option{off}) protection of flash sectors
  3222. in flash bank @var{num}, starting at sector @var{first}
  3223. and continuing up to and including @var{last}.
  3224. Providing a @var{last} sector of @option{last}
  3225. specifies "to the end of the flash bank".
  3226. The @var{num} parameter is a value shown by @command{flash banks}.
  3227. @end deffn
  3228. @deffn Command {flash protect_check} num
  3229. Check protection state of sectors in flash bank @var{num}.
  3230. The @var{num} parameter is a value shown by @command{flash banks}.
  3231. @comment @option{flash erase_sector} using the same syntax.
  3232. @end deffn
  3233. @anchor{Flash Driver List}
  3234. @section Flash Driver List
  3235. As noted above, the @command{flash bank} command requires a driver name,
  3236. and allows driver-specific options and behaviors.
  3237. Some drivers also activate driver-specific commands.
  3238. @subsection External Flash
  3239. @deffn {Flash Driver} cfi
  3240. @cindex Common Flash Interface
  3241. @cindex CFI
  3242. The ``Common Flash Interface'' (CFI) is the main standard for
  3243. external NOR flash chips, each of which connects to a
  3244. specific external chip select on the CPU.
  3245. Frequently the first such chip is used to boot the system.
  3246. Your board's @code{reset-init} handler might need to
  3247. configure additional chip selects using other commands (like: @command{mww} to
  3248. configure a bus and its timings), or
  3249. perhaps configure a GPIO pin that controls the ``write protect'' pin
  3250. on the flash chip.
  3251. The CFI driver can use a target-specific working area to significantly
  3252. speed up operation.
  3253. The CFI driver can accept the following optional parameters, in any order:
  3254. @itemize
  3255. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  3256. like AM29LV010 and similar types.
  3257. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  3258. @end itemize
  3259. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  3260. wide on a sixteen bit bus:
  3261. @example
  3262. flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  3263. flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  3264. @end example
  3265. To configure one bank of 32 MBytes
  3266. built from two sixteen bit (two byte) wide parts wired in parallel
  3267. to create a thirty-two bit (four byte) bus with doubled throughput:
  3268. @example
  3269. flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  3270. @end example
  3271. @c "cfi part_id" disabled
  3272. @end deffn
  3273. @subsection Internal Flash (Microcontrollers)
  3274. @deffn {Flash Driver} aduc702x
  3275. The ADUC702x analog microcontrollers from Analog Devices
  3276. include internal flash and use ARM7TDMI cores.
  3277. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  3278. The setup command only requires the @var{target} argument
  3279. since all devices in this family have the same memory layout.
  3280. @example
  3281. flash bank aduc702x 0 0 0 0 $_TARGETNAME
  3282. @end example
  3283. @end deffn
  3284. @deffn {Flash Driver} at91sam3
  3285. @cindex at91sam3
  3286. All members of the AT91SAM3 microcontroller family from
  3287. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  3288. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  3289. that the driver was orginaly developed and tested using the
  3290. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  3291. the family was cribbed from the data sheet. @emph{Note to future
  3292. readers/updaters: Please remove this worrysome comment after other
  3293. chips are confirmed.}
  3294. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  3295. have one flash bank. In all cases the flash banks are at
  3296. the following fixed locations:
  3297. @example
  3298. # Flash bank 0 - all chips
  3299. flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
  3300. # Flash bank 1 - only 256K chips
  3301. flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
  3302. @end example
  3303. Internally, the AT91SAM3 flash memory is organized as follows.
  3304. Unlike the AT91SAM7 chips, these are not used as parameters
  3305. to the @command{flash bank} command:
  3306. @itemize
  3307. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  3308. @item @emph{Bank Size:} 128K/64K Per flash bank
  3309. @item @emph{Sectors:} 16 or 8 per bank
  3310. @item @emph{SectorSize:} 8K Per Sector
  3311. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  3312. @end itemize
  3313. The AT91SAM3 driver adds some additional commands:
  3314. @deffn Command {at91sam3 gpnvm}
  3315. @deffnx Command {at91sam3 gpnvm clear} number
  3316. @deffnx Command {at91sam3 gpnvm set} number
  3317. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  3318. With no parameters, @command{show} or @command{show all},
  3319. shows the status of all GPNVM bits.
  3320. With @command{show} @var{number}, displays that bit.
  3321. With @command{set} @var{number} or @command{clear} @var{number},
  3322. modifies that GPNVM bit.
  3323. @end deffn
  3324. @deffn Command {at91sam3 info}
  3325. This command attempts to display information about the AT91SAM3
  3326. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  3327. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  3328. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  3329. various clock configuration registers and attempts to display how it
  3330. believes the chip is configured. By default, the SLOWCLK is assumed to
  3331. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  3332. @end deffn
  3333. @deffn Command {at91sam3 slowclk} [value]
  3334. This command shows/sets the slow clock frequency used in the
  3335. @command{at91sam3 info} command calculations above.
  3336. @end deffn
  3337. @end deffn
  3338. @deffn {Flash Driver} at91sam7
  3339. All members of the AT91SAM7 microcontroller family from Atmel include
  3340. internal flash and use ARM7TDMI cores. The driver automatically
  3341. recognizes a number of these chips using the chip identification
  3342. register, and autoconfigures itself.
  3343. @example
  3344. flash bank at91sam7 0 0 0 0 $_TARGETNAME
  3345. @end example
  3346. For chips which are not recognized by the controller driver, you must
  3347. provide additional parameters in the following order:
  3348. @itemize
  3349. @item @var{chip_model} ... label used with @command{flash info}
  3350. @item @var{banks}
  3351. @item @var{sectors_per_bank}
  3352. @item @var{pages_per_sector}
  3353. @item @var{pages_size}
  3354. @item @var{num_nvm_bits}
  3355. @item @var{freq_khz} ... required if an external clock is provided,
  3356. optional (but recommended) when the oscillator frequency is known
  3357. @end itemize
  3358. It is recommended that you provide zeroes for all of those values
  3359. except the clock frequency, so that everything except that frequency
  3360. will be autoconfigured.
  3361. Knowing the frequency helps ensure correct timings for flash access.
  3362. The flash controller handles erases automatically on a page (128/256 byte)
  3363. basis, so explicit erase commands are not necessary for flash programming.
  3364. However, there is an ``EraseAll`` command that can erase an entire flash
  3365. plane (of up to 256KB), and it will be used automatically when you issue
  3366. @command{flash erase_sector} or @command{flash erase_address} commands.
  3367. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  3368. Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
  3369. bit for the processor. Each processor has a number of such bits,
  3370. used for controlling features such as brownout detection (so they
  3371. are not truly general purpose).
  3372. @quotation Note
  3373. This assumes that the first flash bank (number 0) is associated with
  3374. the appropriate at91sam7 target.
  3375. @end quotation
  3376. @end deffn
  3377. @end deffn
  3378. @deffn {Flash Driver} avr
  3379. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  3380. @emph{The current implementation is incomplete.}
  3381. @comment - defines mass_erase ... pointless given flash_erase_address
  3382. @end deffn
  3383. @deffn {Flash Driver} ecosflash
  3384. @emph{No idea what this is...}
  3385. The @var{ecosflash} driver defines one mandatory parameter,
  3386. the name of a modules of target code which is downloaded
  3387. and executed.
  3388. @end deffn
  3389. @deffn {Flash Driver} lpc2000
  3390. Most members of the LPC1700 and LPC2000 microcontroller families from NXP
  3391. include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
  3392. @quotation Note
  3393. There are LPC2000 devices which are not supported by the @var{lpc2000}
  3394. driver:
  3395. The LPC2888 is supported by the @var{lpc288x} driver.
  3396. The LPC29xx family is supported by the @var{lpc2900} driver.
  3397. @end quotation
  3398. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  3399. which must appear in the following order:
  3400. @itemize
  3401. @item @var{variant} ... required, may be
  3402. @var{lpc2000_v1} (older LPC21xx and LPC22xx)
  3403. @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  3404. or @var{lpc1700} (LPC175x and LPC176x)
  3405. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  3406. at which the core is running
  3407. @item @var{calc_checksum} ... optional (but you probably want to provide this!),
  3408. telling the driver to calculate a valid checksum for the exception vector table.
  3409. @end itemize
  3410. LPC flashes don't require the chip and bus width to be specified.
  3411. @example
  3412. flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  3413. lpc2000_v2 14765 calc_checksum
  3414. @end example
  3415. @deffn {Command} {lpc2000 part_id} bank
  3416. Displays the four byte part identifier associated with
  3417. the specified flash @var{bank}.
  3418. @end deffn
  3419. @end deffn
  3420. @deffn {Flash Driver} lpc288x
  3421. The LPC2888 microcontroller from NXP needs slightly different flash
  3422. support from its lpc2000 siblings.
  3423. The @var{lpc288x} driver defines one mandatory parameter,
  3424. the programming clock rate in Hz.
  3425. LPC flashes don't require the chip and bus width to be specified.
  3426. @example
  3427. flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
  3428. @end example
  3429. @end deffn
  3430. @deffn {Flash Driver} lpc2900
  3431. This driver supports the LPC29xx ARM968E based microcontroller family
  3432. from NXP.
  3433. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  3434. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  3435. sector layout are auto-configured by the driver.
  3436. The driver has one additional mandatory parameter: The CPU clock rate
  3437. (in kHz) at the time the flash operations will take place. Most of the time this
  3438. will not be the crystal frequency, but a higher PLL frequency. The
  3439. @code{reset-init} event handler in the board script is usually the place where
  3440. you start the PLL.
  3441. The driver rejects flashless devices (currently the LPC2930).
  3442. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  3443. It must be handled much more like NAND flash memory, and will therefore be
  3444. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  3445. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  3446. sector needs to be erased or programmed, it is automatically unprotected.
  3447. What is shown as protection status in the @code{flash info} command, is
  3448. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  3449. sector from ever being erased or programmed again. As this is an irreversible
  3450. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  3451. and not by the standard @code{flash protect} command.
  3452. Example for a 125 MHz clock frequency:
  3453. @example
  3454. flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
  3455. @end example
  3456. Some @code{lpc2900}-specific commands are defined. In the following command list,
  3457. the @var{bank} parameter is the bank number as obtained by the
  3458. @code{flash banks} command.
  3459. @deffn Command {lpc2900 signature} bank
  3460. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  3461. content. This is a hardware feature of the flash block, hence the calculation is
  3462. very fast. You may use this to verify the content of a programmed device against
  3463. a known signature.
  3464. Example:
  3465. @example
  3466. lpc2900 signature 0
  3467. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  3468. @end example
  3469. @end deffn
  3470. @deffn Command {lpc2900 read_custom} bank filename
  3471. Reads the 912 bytes of customer information from the flash index sector, and
  3472. saves it to a file in binary format.
  3473. Example:
  3474. @example
  3475. lpc2900 read_custom 0 /path_to/customer_info.bin
  3476. @end example
  3477. @end deffn
  3478. The index sector of the flash is a @emph{write-only} sector. It cannot be
  3479. erased! In order to guard against unintentional write access, all following
  3480. commands need to be preceeded by a successful call to the @code{password}
  3481. command:
  3482. @deffn Command {lpc2900 password} bank password
  3483. You need to use this command right before each of the following commands:
  3484. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  3485. @code{lpc2900 secure_jtag}.
  3486. The password string is fixed to "I_know_what_I_am_doing".
  3487. Example:
  3488. @example
  3489. lpc2900 password 0 I_know_what_I_am_doing
  3490. Potentially dangerous operation allowed in next command!
  3491. @end example
  3492. @end deffn
  3493. @deffn Command {lpc2900 write_custom} bank filename type
  3494. Writes the content of the file into the customer info space of the flash index
  3495. sector. The filetype can be specified with the @var{type} field. Possible values
  3496. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  3497. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  3498. contain a single section, and the contained data length must be exactly
  3499. 912 bytes.
  3500. @quotation Attention
  3501. This cannot be reverted! Be careful!
  3502. @end quotation
  3503. Example:
  3504. @example
  3505. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  3506. @end example
  3507. @end deffn
  3508. @deffn Command {lpc2900 secure_sector} bank first last
  3509. Secures the sector range from @var{first} to @var{last} (including) against
  3510. further program and erase operations. The sector security will be effective
  3511. after the next power cycle.
  3512. @quotation Attention
  3513. This cannot be reverted! Be careful!
  3514. @end quotation
  3515. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  3516. Example:
  3517. @example
  3518. lpc2900 secure_sector 0 1 1
  3519. flash info 0
  3520. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  3521. # 0: 0x00000000 (0x2000 8kB) not protected
  3522. # 1: 0x00002000 (0x2000 8kB) protected
  3523. # 2: 0x00004000 (0x2000 8kB) not protected
  3524. @end example
  3525. @end deffn
  3526. @deffn Command {lpc2900 secure_jtag} bank
  3527. Irreversibly disable the JTAG port. The new JTAG security setting will be
  3528. effective after the next power cycle.
  3529. @quotation Attention
  3530. This cannot be reverted! Be careful!
  3531. @end quotation
  3532. Examples:
  3533. @example
  3534. lpc2900 secure_jtag 0
  3535. @end example
  3536. @end deffn
  3537. @end deffn
  3538. @deffn {Flash Driver} ocl
  3539. @emph{No idea what this is, other than using some arm7/arm9 core.}
  3540. @example
  3541. flash bank ocl 0 0 0 0 $_TARGETNAME
  3542. @end example
  3543. @end deffn
  3544. @deffn {Flash Driver} pic32mx
  3545. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  3546. and integrate flash memory.
  3547. @emph{The current implementation is incomplete.}
  3548. @example
  3549. flash bank pix32mx 0 0 0 0 $_TARGETNAME
  3550. @end example
  3551. @comment numerous *disabled* commands are defined:
  3552. @comment - chip_erase ... pointless given flash_erase_address
  3553. @comment - lock, unlock ... pointless given protect on/off (yes?)
  3554. @comment - pgm_word ... shouldn't bank be deduced from address??
  3555. Some pic32mx-specific commands are defined:
  3556. @deffn Command {pic32mx pgm_word} address value bank
  3557. Programs the specified 32-bit @var{value} at the given @var{address}
  3558. in the specified chip @var{bank}.
  3559. @end deffn
  3560. @end deffn
  3561. @deffn {Flash Driver} stellaris
  3562. All members of the Stellaris LM3Sxxx microcontroller family from
  3563. Texas Instruments
  3564. include internal flash and use ARM Cortex M3 cores.
  3565. The driver automatically recognizes a number of these chips using
  3566. the chip identification register, and autoconfigures itself.
  3567. @footnote{Currently there is a @command{stellaris mass_erase} command.
  3568. That seems pointless since the same effect can be had using the
  3569. standard @command{flash erase_address} command.}
  3570. @example
  3571. flash bank stellaris 0 0 0 0 $_TARGETNAME
  3572. @end example
  3573. @end deffn
  3574. @deffn {Flash Driver} stm32x
  3575. All members of the STM32 microcontroller family from ST Microelectronics
  3576. include internal flash and use ARM Cortex M3 cores.
  3577. The driver automatically recognizes a number of these chips using
  3578. the chip identification register, and autoconfigures itself.
  3579. @example
  3580. flash bank stm32x 0 0 0 0 $_TARGETNAME
  3581. @end example
  3582. Some stm32x-specific commands
  3583. @footnote{Currently there is a @command{stm32x mass_erase} command.
  3584. That seems pointless since the same effect can be had using the
  3585. standard @command{flash erase_address} command.}
  3586. are defined:
  3587. @deffn Command {stm32x lock} num
  3588. Locks the entire stm32 device.
  3589. The @var{num} parameter is a value shown by @command{flash banks}.
  3590. @end deffn
  3591. @deffn Command {stm32x unlock} num
  3592. Unlocks the entire stm32 device.
  3593. The @var{num} parameter is a value shown by @command{flash banks}.
  3594. @end deffn
  3595. @deffn Command {stm32x options_read} num
  3596. Read and display the stm32 option bytes written by
  3597. the @command{stm32x options_write} command.
  3598. The @var{num} parameter is a value shown by @command{flash banks}.
  3599. @end deffn
  3600. @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  3601. Writes the stm32 option byte with the specified values.
  3602. The @var{num} parameter is a value shown by @command{flash banks}.
  3603. @end deffn
  3604. @end deffn
  3605. @deffn {Flash Driver} str7x
  3606. All members of the STR7 microcontroller family from ST Microelectronics
  3607. include internal flash and use ARM7TDMI cores.
  3608. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  3609. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  3610. @example
  3611. flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  3612. @end example
  3613. @deffn Command {str7x disable_jtag} bank
  3614. Activate the Debug/Readout protection mechanism
  3615. for the specified flash bank.
  3616. @end deffn
  3617. @end deffn
  3618. @deffn {Flash Driver} str9x
  3619. Most members of the STR9 microcontroller family from ST Microelectronics
  3620. include internal flash and use ARM966E cores.
  3621. The str9 needs the flash controller to be configured using
  3622. the @command{str9x flash_config} command prior to Flash programming.
  3623. @example
  3624. flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  3625. str9x flash_config 0 4 2 0 0x80000
  3626. @end example
  3627. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  3628. Configures the str9 flash controller.
  3629. The @var{num} parameter is a value shown by @command{flash banks}.
  3630. @itemize @bullet
  3631. @item @var{bbsr} - Boot Bank Size register
  3632. @item @var{nbbsr} - Non Boot Bank Size register
  3633. @item @var{bbadr} - Boot Bank Start Address register
  3634. @item @var{nbbadr} - Boot Bank Start Address register
  3635. @end itemize
  3636. @end deffn
  3637. @end deffn
  3638. @deffn {Flash Driver} tms470
  3639. Most members of the TMS470 microcontroller family from Texas Instruments
  3640. include internal flash and use ARM7TDMI cores.
  3641. This driver doesn't require the chip and bus width to be specified.
  3642. Some tms470-specific commands are defined:
  3643. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  3644. Saves programming keys in a register, to enable flash erase and write commands.
  3645. @end deffn
  3646. @deffn Command {tms470 osc_mhz} clock_mhz
  3647. Reports the clock speed, which is used to calculate timings.
  3648. @end deffn
  3649. @deffn Command {tms470 plldis} (0|1)
  3650. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  3651. the flash clock.
  3652. @end deffn
  3653. @end deffn
  3654. @subsection str9xpec driver
  3655. @cindex str9xpec
  3656. Here is some background info to help
  3657. you better understand how this driver works. OpenOCD has two flash drivers for
  3658. the str9:
  3659. @enumerate
  3660. @item
  3661. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  3662. flash programming as it is faster than the @option{str9xpec} driver.
  3663. @item
  3664. Direct programming @option{str9xpec} using the flash controller. This is an
  3665. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  3666. core does not need to be running to program using this flash driver. Typical use
  3667. for this driver is locking/unlocking the target and programming the option bytes.
  3668. @end enumerate
  3669. Before we run any commands using the @option{str9xpec} driver we must first disable
  3670. the str9 core. This example assumes the @option{str9xpec} driver has been
  3671. configured for flash bank 0.
  3672. @example
  3673. # assert srst, we do not want core running
  3674. # while accessing str9xpec flash driver
  3675. jtag_reset 0 1
  3676. # turn off target polling
  3677. poll off
  3678. # disable str9 core
  3679. str9xpec enable_turbo 0
  3680. # read option bytes
  3681. str9xpec options_read 0
  3682. # re-enable str9 core
  3683. str9xpec disable_turbo 0
  3684. poll on
  3685. reset halt
  3686. @end example
  3687. The above example will read the str9 option bytes.
  3688. When performing a unlock remember that you will not be able to halt the str9 - it
  3689. has been locked. Halting the core is not required for the @option{str9xpec} driver
  3690. as mentioned above, just issue the commands above manually or from a telnet prompt.
  3691. @deffn {Flash Driver} str9xpec
  3692. Only use this driver for locking/unlocking the device or configuring the option bytes.
  3693. Use the standard str9 driver for programming.
  3694. Before using the flash commands the turbo mode must be enabled using the
  3695. @command{str9xpec enable_turbo} command.
  3696. Several str9xpec-specific commands are defined:
  3697. @deffn Command {str9xpec disable_turbo} num
  3698. Restore the str9 into JTAG chain.
  3699. @end deffn
  3700. @deffn Command {str9xpec enable_turbo} num
  3701. Enable turbo mode, will simply remove the str9 from the chain and talk
  3702. directly to the embedded flash controller.
  3703. @end deffn
  3704. @deffn Command {str9xpec lock} num
  3705. Lock str9 device. The str9 will only respond to an unlock command that will
  3706. erase the device.
  3707. @end deffn
  3708. @deffn Command {str9xpec part_id} num
  3709. Prints the part identifier for bank @var{num}.
  3710. @end deffn
  3711. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  3712. Configure str9 boot bank.
  3713. @end deffn
  3714. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  3715. Configure str9 lvd source.
  3716. @end deffn
  3717. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  3718. Configure str9 lvd threshold.
  3719. @end deffn
  3720. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  3721. Configure str9 lvd reset warning source.
  3722. @end deffn
  3723. @deffn Command {str9xpec options_read} num
  3724. Read str9 option bytes.
  3725. @end deffn
  3726. @deffn Command {str9xpec options_write} num
  3727. Write str9 option bytes.
  3728. @end deffn
  3729. @deffn Command {str9xpec unlock} num
  3730. unlock str9 device.
  3731. @end deffn
  3732. @end deffn
  3733. @section mFlash
  3734. @subsection mFlash Configuration
  3735. @cindex mFlash Configuration
  3736. @deffn {Config Command} {mflash bank} soc base RST_pin target
  3737. Configures a mflash for @var{soc} host bank at
  3738. address @var{base}.
  3739. The pin number format depends on the host GPIO naming convention.
  3740. Currently, the mflash driver supports s3c2440 and pxa270.
  3741. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  3742. @example
  3743. mflash bank s3c2440 0x10000000 1b 0
  3744. @end example
  3745. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  3746. @example
  3747. mflash bank pxa270 0x08000000 43 0
  3748. @end example
  3749. @end deffn
  3750. @subsection mFlash commands
  3751. @cindex mFlash commands
  3752. @deffn Command {mflash config pll} frequency
  3753. Configure mflash PLL.
  3754. The @var{frequency} is the mflash input frequency, in Hz.
  3755. Issuing this command will erase mflash's whole internal nand and write new pll.
  3756. After this command, mflash needs power-on-reset for normal operation.
  3757. If pll was newly configured, storage and boot(optional) info also need to be update.
  3758. @end deffn
  3759. @deffn Command {mflash config boot}
  3760. Configure bootable option.
  3761. If bootable option is set, mflash offer the first 8 sectors
  3762. (4kB) for boot.
  3763. @end deffn
  3764. @deffn Command {mflash config storage}
  3765. Configure storage information.
  3766. For the normal storage operation, this information must be
  3767. written.
  3768. @end deffn
  3769. @deffn Command {mflash dump} num filename offset size
  3770. Dump @var{size} bytes, starting at @var{offset} bytes from the
  3771. beginning of the bank @var{num}, to the file named @var{filename}.
  3772. @end deffn
  3773. @deffn Command {mflash probe}
  3774. Probe mflash.
  3775. @end deffn
  3776. @deffn Command {mflash write} num filename offset
  3777. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  3778. @var{offset} bytes from the beginning of the bank.
  3779. @end deffn
  3780. @node NAND Flash Commands
  3781. @chapter NAND Flash Commands
  3782. @cindex NAND
  3783. Compared to NOR or SPI flash, NAND devices are inexpensive
  3784. and high density. Today's NAND chips, and multi-chip modules,
  3785. commonly hold multiple GigaBytes of data.
  3786. NAND chips consist of a number of ``erase blocks'' of a given
  3787. size (such as 128 KBytes), each of which is divided into a
  3788. number of pages (of perhaps 512 or 2048 bytes each). Each
  3789. page of a NAND flash has an ``out of band'' (OOB) area to hold
  3790. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  3791. of OOB for every 512 bytes of page data.
  3792. One key characteristic of NAND flash is that its error rate
  3793. is higher than that of NOR flash. In normal operation, that
  3794. ECC is used to correct and detect errors. However, NAND
  3795. blocks can also wear out and become unusable; those blocks
  3796. are then marked "bad". NAND chips are even shipped from the
  3797. manufacturer with a few bad blocks. The highest density chips
  3798. use a technology (MLC) that wears out more quickly, so ECC
  3799. support is increasingly important as a way to detect blocks
  3800. that have begun to fail, and help to preserve data integrity
  3801. with techniques such as wear leveling.
  3802. Software is used to manage the ECC. Some controllers don't
  3803. support ECC directly; in those cases, software ECC is used.
  3804. Other controllers speed up the ECC calculations with hardware.
  3805. Single-bit error correction hardware is routine. Controllers
  3806. geared for newer MLC chips may correct 4 or more errors for
  3807. every 512 bytes of data.
  3808. You will need to make sure that any data you write using
  3809. OpenOCD includes the apppropriate kind of ECC. For example,
  3810. that may mean passing the @code{oob_softecc} flag when
  3811. writing NAND data, or ensuring that the correct hardware
  3812. ECC mode is used.
  3813. The basic steps for using NAND devices include:
  3814. @enumerate
  3815. @item Declare via the command @command{nand device}
  3816. @* Do this in a board-specific configuration file,
  3817. passing parameters as needed by the controller.
  3818. @item Configure each device using @command{nand probe}.
  3819. @* Do this only after the associated target is set up,
  3820. such as in its reset-init script or in procures defined
  3821. to access that device.
  3822. @item Operate on the flash via @command{nand subcommand}
  3823. @* Often commands to manipulate the flash are typed by a human, or run
  3824. via a script in some automated way. Common task include writing a
  3825. boot loader, operating system, or other data needed to initialize or
  3826. de-brick a board.
  3827. @end enumerate
  3828. @b{NOTE:} At the time this text was written, the largest NAND
  3829. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  3830. This is because the variables used to hold offsets and lengths
  3831. are only 32 bits wide.
  3832. (Larger chips may work in some cases, unless an offset or length
  3833. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  3834. Some larger devices will work, since they are actually multi-chip
  3835. modules with two smaller chips and individual chipselect lines.
  3836. @anchor{NAND Configuration}
  3837. @section NAND Configuration Commands
  3838. @cindex NAND configuration
  3839. NAND chips must be declared in configuration scripts,
  3840. plus some additional configuration that's done after
  3841. OpenOCD has initialized.
  3842. @deffn {Config Command} {nand device} name controller target [configparams...]
  3843. Declares a NAND device, which can be read and written to
  3844. after it has been configured through @command{nand probe}.
  3845. In OpenOCD, devices are single chips; this is unlike some
  3846. operating systems, which may manage multiple chips as if
  3847. they were a single (larger) device.
  3848. In some cases, configuring a device will activate extra
  3849. commands; see the controller-specific documentation.
  3850. @b{NOTE:} This command is not available after OpenOCD
  3851. initialization has completed. Use it in board specific
  3852. configuration files, not interactively.
  3853. @itemize @bullet
  3854. @item @var{name} ... may be used to reference the NAND bank
  3855. in other commands.
  3856. @item @var{controller} ... identifies the controller driver
  3857. associated with the NAND device being declared.
  3858. @xref{NAND Driver List}.
  3859. @item @var{target} ... names the target used when issuing
  3860. commands to the NAND controller.
  3861. @comment Actually, it's currently a controller-specific parameter...
  3862. @item @var{configparams} ... controllers may support, or require,
  3863. additional parameters. See the controller-specific documentation
  3864. for more information.
  3865. @end itemize
  3866. @end deffn
  3867. @deffn Command {nand list}
  3868. Prints a summary of each device declared
  3869. using @command{nand device}, numbered from zero.
  3870. Note that un-probed devices show no details.
  3871. @example
  3872. > nand list
  3873. #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  3874. blocksize: 131072, blocks: 8192
  3875. #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  3876. blocksize: 131072, blocks: 8192
  3877. >
  3878. @end example
  3879. @end deffn
  3880. @deffn Command {nand probe} num
  3881. Probes the specified device to determine key characteristics
  3882. like its page and block sizes, and how many blocks it has.
  3883. The @var{num} parameter is the value shown by @command{nand list}.
  3884. You must (successfully) probe a device before you can use
  3885. it with most other NAND commands.
  3886. @end deffn
  3887. @section Erasing, Reading, Writing to NAND Flash
  3888. @deffn Command {nand dump} num filename offset length [oob_option]
  3889. @cindex NAND reading
  3890. Reads binary data from the NAND device and writes it to the file,
  3891. starting at the specified offset.
  3892. The @var{num} parameter is the value shown by @command{nand list}.
  3893. Use a complete path name for @var{filename}, so you don't depend
  3894. on the directory used to start the OpenOCD server.
  3895. The @var{offset} and @var{length} must be exact multiples of the
  3896. device's page size. They describe a data region; the OOB data
  3897. associated with each such page may also be accessed.
  3898. @b{NOTE:} At the time this text was written, no error correction
  3899. was done on the data that's read, unless raw access was disabled
  3900. and the underlying NAND controller driver had a @code{read_page}
  3901. method which handled that error correction.
  3902. By default, only page data is saved to the specified file.
  3903. Use an @var{oob_option} parameter to save OOB data:
  3904. @itemize @bullet
  3905. @item no oob_* parameter
  3906. @*Output file holds only page data; OOB is discarded.
  3907. @item @code{oob_raw}
  3908. @*Output file interleaves page data and OOB data;
  3909. the file will be longer than "length" by the size of the
  3910. spare areas associated with each data page.
  3911. Note that this kind of "raw" access is different from
  3912. what's implied by @command{nand raw_access}, which just
  3913. controls whether a hardware-aware access method is used.
  3914. @item @code{oob_only}
  3915. @*Output file has only raw OOB data, and will
  3916. be smaller than "length" since it will contain only the
  3917. spare areas associated with each data page.
  3918. @end itemize
  3919. @end deffn
  3920. @deffn Command {nand erase} num [offset length]
  3921. @cindex NAND erasing
  3922. @cindex NAND programming
  3923. Erases blocks on the specified NAND device, starting at the
  3924. specified @var{offset} and continuing for @var{length} bytes.
  3925. Both of those values must be exact multiples of the device's
  3926. block size, and the region they specify must fit entirely in the chip.
  3927. If those parameters are not specified,
  3928. the whole NAND chip will be erased.
  3929. The @var{num} parameter is the value shown by @command{nand list}.
  3930. @b{NOTE:} This command will try to erase bad blocks, when told
  3931. to do so, which will probably invalidate the manufacturer's bad
  3932. block marker.
  3933. For the remainder of the current server session, @command{nand info}
  3934. will still report that the block ``is'' bad.
  3935. @end deffn
  3936. @deffn Command {nand write} num filename offset [option...]
  3937. @cindex NAND writing
  3938. @cindex NAND programming
  3939. Writes binary data from the file into the specified NAND device,
  3940. starting at the specified offset. Those pages should already
  3941. have been erased; you can't change zero bits to one bits.
  3942. The @var{num} parameter is the value shown by @command{nand list}.
  3943. Use a complete path name for @var{filename}, so you don't depend
  3944. on the directory used to start the OpenOCD server.
  3945. The @var{offset} must be an exact multiple of the device's page size.
  3946. All data in the file will be written, assuming it doesn't run
  3947. past the end of the device.
  3948. Only full pages are written, and any extra space in the last
  3949. page will be filled with 0xff bytes. (That includes OOB data,
  3950. if that's being written.)
  3951. @b{NOTE:} At the time this text was written, bad blocks are
  3952. ignored. That is, this routine will not skip bad blocks,
  3953. but will instead try to write them. This can cause problems.
  3954. Provide at most one @var{option} parameter. With some
  3955. NAND drivers, the meanings of these parameters may change
  3956. if @command{nand raw_access} was used to disable hardware ECC.
  3957. @itemize @bullet
  3958. @item no oob_* parameter
  3959. @*File has only page data, which is written.
  3960. If raw acccess is in use, the OOB area will not be written.
  3961. Otherwise, if the underlying NAND controller driver has
  3962. a @code{write_page} routine, that routine may write the OOB
  3963. with hardware-computed ECC data.
  3964. @item @code{oob_only}
  3965. @*File has only raw OOB data, which is written to the OOB area.
  3966. Each page's data area stays untouched. @i{This can be a dangerous
  3967. option}, since it can invalidate the ECC data.
  3968. You may need to force raw access to use this mode.
  3969. @item @code{oob_raw}
  3970. @*File interleaves data and OOB data, both of which are written
  3971. If raw access is enabled, the data is written first, then the
  3972. un-altered OOB.
  3973. Otherwise, if the underlying NAND controller driver has
  3974. a @code{write_page} routine, that routine may modify the OOB
  3975. before it's written, to include hardware-computed ECC data.
  3976. @item @code{oob_softecc}
  3977. @*File has only page data, which is written.
  3978. The OOB area is filled with 0xff, except for a standard 1-bit
  3979. software ECC code stored in conventional locations.
  3980. You might need to force raw access to use this mode, to prevent
  3981. the underlying driver from applying hardware ECC.
  3982. @item @code{oob_softecc_kw}
  3983. @*File has only page data, which is written.
  3984. The OOB area is filled with 0xff, except for a 4-bit software ECC
  3985. specific to the boot ROM in Marvell Kirkwood SoCs.
  3986. You might need to force raw access to use this mode, to prevent
  3987. the underlying driver from applying hardware ECC.
  3988. @end itemize
  3989. @end deffn
  3990. @deffn Command {nand verify} num filename offset [option...]
  3991. @cindex NAND verification
  3992. @cindex NAND programming
  3993. Verify the binary data in the file has been programmed to the
  3994. specified NAND device, starting at the specified offset.
  3995. The @var{num} parameter is the value shown by @command{nand list}.
  3996. Use a complete path name for @var{filename}, so you don't depend
  3997. on the directory used to start the OpenOCD server.
  3998. The @var{offset} must be an exact multiple of the device's page size.
  3999. All data in the file will be read and compared to the contents of the
  4000. flash, assuming it doesn't run past the end of the device.
  4001. As with @command{nand write}, only full pages are verified, so any extra
  4002. space in the last page will be filled with 0xff bytes.
  4003. The same @var{options} accepted by @command{nand write},
  4004. and the file will be processed similarly to produce the buffers that
  4005. can be compared against the contents produced from @command{nand dump}.
  4006. @b{NOTE:} This will not work when the underlying NAND controller
  4007. driver's @code{write_page} routine must update the OOB with a
  4008. hardward-computed ECC before the data is written. This limitation may
  4009. be removed in a future release.
  4010. @end deffn
  4011. @section Other NAND commands
  4012. @cindex NAND other commands
  4013. @deffn Command {nand check_bad_blocks} [offset length]
  4014. Checks for manufacturer bad block markers on the specified NAND
  4015. device. If no parameters are provided, checks the whole
  4016. device; otherwise, starts at the specified @var{offset} and
  4017. continues for @var{length} bytes.
  4018. Both of those values must be exact multiples of the device's
  4019. block size, and the region they specify must fit entirely in the chip.
  4020. The @var{num} parameter is the value shown by @command{nand list}.
  4021. @b{NOTE:} Before using this command you should force raw access
  4022. with @command{nand raw_access enable} to ensure that the underlying
  4023. driver will not try to apply hardware ECC.
  4024. @end deffn
  4025. @deffn Command {nand info} num
  4026. The @var{num} parameter is the value shown by @command{nand list}.
  4027. This prints the one-line summary from "nand list", plus for
  4028. devices which have been probed this also prints any known
  4029. status for each block.
  4030. @end deffn
  4031. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  4032. Sets or clears an flag affecting how page I/O is done.
  4033. The @var{num} parameter is the value shown by @command{nand list}.
  4034. This flag is cleared (disabled) by default, but changing that
  4035. value won't affect all NAND devices. The key factor is whether
  4036. the underlying driver provides @code{read_page} or @code{write_page}
  4037. methods. If it doesn't provide those methods, the setting of
  4038. this flag is irrelevant; all access is effectively ``raw''.
  4039. When those methods exist, they are normally used when reading
  4040. data (@command{nand dump} or reading bad block markers) or
  4041. writing it (@command{nand write}). However, enabling
  4042. raw access (setting the flag) prevents use of those methods,
  4043. bypassing hardware ECC logic.
  4044. @i{This can be a dangerous option}, since writing blocks
  4045. with the wrong ECC data can cause them to be marked as bad.
  4046. @end deffn
  4047. @anchor{NAND Driver List}
  4048. @section NAND Driver List
  4049. As noted above, the @command{nand device} command allows
  4050. driver-specific options and behaviors.
  4051. Some controllers also activate controller-specific commands.
  4052. @deffn {NAND Driver} davinci
  4053. This driver handles the NAND controllers found on DaVinci family
  4054. chips from Texas Instruments.
  4055. It takes three extra parameters:
  4056. address of the NAND chip;
  4057. hardware ECC mode to use (@option{hwecc1},
  4058. @option{hwecc4}, @option{hwecc4_infix});
  4059. address of the AEMIF controller on this processor.
  4060. @example
  4061. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  4062. @end example
  4063. All DaVinci processors support the single-bit ECC hardware,
  4064. and newer ones also support the four-bit ECC hardware.
  4065. The @code{write_page} and @code{read_page} methods are used
  4066. to implement those ECC modes, unless they are disabled using
  4067. the @command{nand raw_access} command.
  4068. @end deffn
  4069. @deffn {NAND Driver} lpc3180
  4070. These controllers require an extra @command{nand device}
  4071. parameter: the clock rate used by the controller.
  4072. @deffn Command {lpc3180 select} num [mlc|slc]
  4073. Configures use of the MLC or SLC controller mode.
  4074. MLC implies use of hardware ECC.
  4075. The @var{num} parameter is the value shown by @command{nand list}.
  4076. @end deffn
  4077. At this writing, this driver includes @code{write_page}
  4078. and @code{read_page} methods. Using @command{nand raw_access}
  4079. to disable those methods will prevent use of hardware ECC
  4080. in the MLC controller mode, but won't change SLC behavior.
  4081. @end deffn
  4082. @comment current lpc3180 code won't issue 5-byte address cycles
  4083. @deffn {NAND Driver} orion
  4084. These controllers require an extra @command{nand device}
  4085. parameter: the address of the controller.
  4086. @example
  4087. nand device orion 0xd8000000
  4088. @end example
  4089. These controllers don't define any specialized commands.
  4090. At this writing, their drivers don't include @code{write_page}
  4091. or @code{read_page} methods, so @command{nand raw_access} won't
  4092. change any behavior.
  4093. @end deffn
  4094. @deffn {NAND Driver} s3c2410
  4095. @deffnx {NAND Driver} s3c2412
  4096. @deffnx {NAND Driver} s3c2440
  4097. @deffnx {NAND Driver} s3c2443
  4098. These S3C24xx family controllers don't have any special
  4099. @command{nand device} options, and don't define any
  4100. specialized commands.
  4101. At this writing, their drivers don't include @code{write_page}
  4102. or @code{read_page} methods, so @command{nand raw_access} won't
  4103. change any behavior.
  4104. @end deffn
  4105. @node PLD/FPGA Commands
  4106. @chapter PLD/FPGA Commands
  4107. @cindex PLD
  4108. @cindex FPGA
  4109. Programmable Logic Devices (PLDs) and the more flexible
  4110. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  4111. OpenOCD can support programming them.
  4112. Although PLDs are generally restrictive (cells are less functional, and
  4113. there are no special purpose cells for memory or computational tasks),
  4114. they share the same OpenOCD infrastructure.
  4115. Accordingly, both are called PLDs here.
  4116. @section PLD/FPGA Configuration and Commands
  4117. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  4118. OpenOCD maintains a list of PLDs available for use in various commands.
  4119. Also, each such PLD requires a driver.
  4120. They are referenced by the number shown by the @command{pld devices} command,
  4121. and new PLDs are defined by @command{pld device driver_name}.
  4122. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  4123. Defines a new PLD device, supported by driver @var{driver_name},
  4124. using the TAP named @var{tap_name}.
  4125. The driver may make use of any @var{driver_options} to configure its
  4126. behavior.
  4127. @end deffn
  4128. @deffn {Command} {pld devices}
  4129. Lists the PLDs and their numbers.
  4130. @end deffn
  4131. @deffn {Command} {pld load} num filename
  4132. Loads the file @file{filename} into the PLD identified by @var{num}.
  4133. The file format must be inferred by the driver.
  4134. @end deffn
  4135. @section PLD/FPGA Drivers, Options, and Commands
  4136. Drivers may support PLD-specific options to the @command{pld device}
  4137. definition command, and may also define commands usable only with
  4138. that particular type of PLD.
  4139. @deffn {FPGA Driver} virtex2
  4140. Virtex-II is a family of FPGAs sold by Xilinx.
  4141. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  4142. No driver-specific PLD definition options are used,
  4143. and one driver-specific command is defined.
  4144. @deffn {Command} {virtex2 read_stat} num
  4145. Reads and displays the Virtex-II status register (STAT)
  4146. for FPGA @var{num}.
  4147. @end deffn
  4148. @end deffn
  4149. @node General Commands
  4150. @chapter General Commands
  4151. @cindex commands
  4152. The commands documented in this chapter here are common commands that
  4153. you, as a human, may want to type and see the output of. Configuration type
  4154. commands are documented elsewhere.
  4155. Intent:
  4156. @itemize @bullet
  4157. @item @b{Source Of Commands}
  4158. @* OpenOCD commands can occur in a configuration script (discussed
  4159. elsewhere) or typed manually by a human or supplied programatically,
  4160. or via one of several TCP/IP Ports.
  4161. @item @b{From the human}
  4162. @* A human should interact with the telnet interface (default port: 4444)
  4163. or via GDB (default port 3333).
  4164. To issue commands from within a GDB session, use the @option{monitor}
  4165. command, e.g. use @option{monitor poll} to issue the @option{poll}
  4166. command. All output is relayed through the GDB session.
  4167. @item @b{Machine Interface}
  4168. The Tcl interface's intent is to be a machine interface. The default Tcl
  4169. port is 5555.
  4170. @end itemize
  4171. @section Daemon Commands
  4172. @deffn {Command} exit
  4173. Exits the current telnet session.
  4174. @end deffn
  4175. @c note EXTREMELY ANNOYING word wrap at column 75
  4176. @c even when lines are e.g. 100+ columns ...
  4177. @c coded in startup.tcl
  4178. @deffn {Command} help [string]
  4179. With no parameters, prints help text for all commands.
  4180. Otherwise, prints each helptext containing @var{string}.
  4181. Not every command provides helptext.
  4182. @end deffn
  4183. @deffn Command sleep msec [@option{busy}]
  4184. Wait for at least @var{msec} milliseconds before resuming.
  4185. If @option{busy} is passed, busy-wait instead of sleeping.
  4186. (This option is strongly discouraged.)
  4187. Useful in connection with script files
  4188. (@command{script} command and @command{target_name} configuration).
  4189. @end deffn
  4190. @deffn Command shutdown
  4191. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
  4192. @end deffn
  4193. @anchor{debug_level}
  4194. @deffn Command debug_level [n]
  4195. @cindex message level
  4196. Display debug level.
  4197. If @var{n} (from 0..3) is provided, then set it to that level.
  4198. This affects the kind of messages sent to the server log.
  4199. Level 0 is error messages only;
  4200. level 1 adds warnings;
  4201. level 2 adds informational messages;
  4202. and level 3 adds debugging messages.
  4203. The default is level 2, but that can be overridden on
  4204. the command line along with the location of that log
  4205. file (which is normally the server's standard output).
  4206. @xref{Running}.
  4207. @end deffn
  4208. @deffn Command fast (@option{enable}|@option{disable})
  4209. Default disabled.
  4210. Set default behaviour of OpenOCD to be "fast and dangerous".
  4211. At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
  4212. fast memory access, and DCC downloads. Those parameters may still be
  4213. individually overridden.
  4214. The target specific "dangerous" optimisation tweaking options may come and go
  4215. as more robust and user friendly ways are found to ensure maximum throughput
  4216. and robustness with a minimum of configuration.
  4217. Typically the "fast enable" is specified first on the command line:
  4218. @example
  4219. openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
  4220. @end example
  4221. @end deffn
  4222. @deffn Command echo message
  4223. Logs a message at "user" priority.
  4224. Output @var{message} to stdout.
  4225. @example
  4226. echo "Downloading kernel -- please wait"
  4227. @end example
  4228. @end deffn
  4229. @deffn Command log_output [filename]
  4230. Redirect logging to @var{filename};
  4231. the initial log output channel is stderr.
  4232. @end deffn
  4233. @anchor{Target State handling}
  4234. @section Target State handling
  4235. @cindex reset
  4236. @cindex halt
  4237. @cindex target initialization
  4238. In this section ``target'' refers to a CPU configured as
  4239. shown earlier (@pxref{CPU Configuration}).
  4240. These commands, like many, implicitly refer to
  4241. a current target which is used to perform the
  4242. various operations. The current target may be changed
  4243. by using @command{targets} command with the name of the
  4244. target which should become current.
  4245. @deffn Command reg [(number|name) [value]]
  4246. Access a single register by @var{number} or by its @var{name}.
  4247. The target must generally be halted before access to CPU core
  4248. registers is allowed. Depending on the hardware, some other
  4249. registers may be accessible while the target is running.
  4250. @emph{With no arguments}:
  4251. list all available registers for the current target,
  4252. showing number, name, size, value, and cache status.
  4253. For valid entries, a value is shown; valid entries
  4254. which are also dirty (and will be written back later)
  4255. are flagged as such.
  4256. @emph{With number/name}: display that register's value.
  4257. @emph{With both number/name and value}: set register's value.
  4258. Writes may be held in a writeback cache internal to OpenOCD,
  4259. so that setting the value marks the register as dirty instead
  4260. of immediately flushing that value. Resuming CPU execution
  4261. (including by single stepping) or otherwise activating the
  4262. relevant module will flush such values.
  4263. Cores may have surprisingly many registers in their
  4264. Debug and trace infrastructure:
  4265. @example
  4266. > reg
  4267. ===== ARM registers
  4268. (0) r0 (/32): 0x0000D3C2 (dirty)
  4269. (1) r1 (/32): 0xFD61F31C
  4270. (2) r2 (/32)
  4271. ...
  4272. (164) ETM_contextid_comparator_mask (/32)
  4273. >
  4274. @end example
  4275. @end deffn
  4276. @deffn Command halt [ms]
  4277. @deffnx Command wait_halt [ms]
  4278. The @command{halt} command first sends a halt request to the target,
  4279. which @command{wait_halt} doesn't.
  4280. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  4281. or 5 seconds if there is no parameter, for the target to halt
  4282. (and enter debug mode).
  4283. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  4284. @quotation Warning
  4285. On ARM cores, software using the @emph{wait for interrupt} operation
  4286. often blocks the JTAG access needed by a @command{halt} command.
  4287. This is because that operation also puts the core into a low
  4288. power mode by gating the core clock;
  4289. but the core clock is needed to detect JTAG clock transitions.
  4290. One partial workaround uses adaptive clocking: when the core is
  4291. interrupted the operation completes, then JTAG clocks are accepted
  4292. at least until the interrupt handler completes.
  4293. However, this workaround is often unusable since the processor, board,
  4294. and JTAG adapter must all support adaptive JTAG clocking.
  4295. Also, it can't work until an interrupt is issued.
  4296. A more complete workaround is to not use that operation while you
  4297. work with a JTAG debugger.
  4298. Tasking environments generaly have idle loops where the body is the
  4299. @emph{wait for interrupt} operation.
  4300. (On older cores, it is a coprocessor action;
  4301. newer cores have a @option{wfi} instruction.)
  4302. Such loops can just remove that operation, at the cost of higher
  4303. power consumption (because the CPU is needlessly clocked).
  4304. @end quotation
  4305. @end deffn
  4306. @deffn Command resume [address]
  4307. Resume the target at its current code position,
  4308. or the optional @var{address} if it is provided.
  4309. OpenOCD will wait 5 seconds for the target to resume.
  4310. @end deffn
  4311. @deffn Command step [address]
  4312. Single-step the target at its current code position,
  4313. or the optional @var{address} if it is provided.
  4314. @end deffn
  4315. @anchor{Reset Command}
  4316. @deffn Command reset
  4317. @deffnx Command {reset run}
  4318. @deffnx Command {reset halt}
  4319. @deffnx Command {reset init}
  4320. Perform as hard a reset as possible, using SRST if possible.
  4321. @emph{All defined targets will be reset, and target
  4322. events will fire during the reset sequence.}
  4323. The optional parameter specifies what should
  4324. happen after the reset.
  4325. If there is no parameter, a @command{reset run} is executed.
  4326. The other options will not work on all systems.
  4327. @xref{Reset Configuration}.
  4328. @itemize @minus
  4329. @item @b{run} Let the target run
  4330. @item @b{halt} Immediately halt the target
  4331. @item @b{init} Immediately halt the target, and execute the reset-init script
  4332. @end itemize
  4333. @end deffn
  4334. @deffn Command soft_reset_halt
  4335. Requesting target halt and executing a soft reset. This is often used
  4336. when a target cannot be reset and halted. The target, after reset is
  4337. released begins to execute code. OpenOCD attempts to stop the CPU and
  4338. then sets the program counter back to the reset vector. Unfortunately
  4339. the code that was executed may have left the hardware in an unknown
  4340. state.
  4341. @end deffn
  4342. @section I/O Utilities
  4343. These commands are available when
  4344. OpenOCD is built with @option{--enable-ioutil}.
  4345. They are mainly useful on embedded targets,
  4346. notably the ZY1000.
  4347. Hosts with operating systems have complementary tools.
  4348. @emph{Note:} there are several more such commands.
  4349. @deffn Command append_file filename [string]*
  4350. Appends the @var{string} parameters to
  4351. the text file @file{filename}.
  4352. Each string except the last one is followed by one space.
  4353. The last string is followed by a newline.
  4354. @end deffn
  4355. @deffn Command cat filename
  4356. Reads and displays the text file @file{filename}.
  4357. @end deffn
  4358. @deffn Command cp src_filename dest_filename
  4359. Copies contents from the file @file{src_filename}
  4360. into @file{dest_filename}.
  4361. @end deffn
  4362. @deffn Command ip
  4363. @emph{No description provided.}
  4364. @end deffn
  4365. @deffn Command ls
  4366. @emph{No description provided.}
  4367. @end deffn
  4368. @deffn Command mac
  4369. @emph{No description provided.}
  4370. @end deffn
  4371. @deffn Command meminfo
  4372. Display available RAM memory on OpenOCD host.
  4373. Used in OpenOCD regression testing scripts.
  4374. @end deffn
  4375. @deffn Command peek
  4376. @emph{No description provided.}
  4377. @end deffn
  4378. @deffn Command poke
  4379. @emph{No description provided.}
  4380. @end deffn
  4381. @deffn Command rm filename
  4382. @c "rm" has both normal and Jim-level versions??
  4383. Unlinks the file @file{filename}.
  4384. @end deffn
  4385. @deffn Command trunc filename
  4386. Removes all data in the file @file{filename}.
  4387. @end deffn
  4388. @anchor{Memory access}
  4389. @section Memory access commands
  4390. @cindex memory access
  4391. These commands allow accesses of a specific size to the memory
  4392. system. Often these are used to configure the current target in some
  4393. special way. For example - one may need to write certain values to the
  4394. SDRAM controller to enable SDRAM.
  4395. @enumerate
  4396. @item Use the @command{targets} (plural) command
  4397. to change the current target.
  4398. @item In system level scripts these commands are deprecated.
  4399. Please use their TARGET object siblings to avoid making assumptions
  4400. about what TAP is the current target, or about MMU configuration.
  4401. @end enumerate
  4402. @deffn Command mdw [phys] addr [count]
  4403. @deffnx Command mdh [phys] addr [count]
  4404. @deffnx Command mdb [phys] addr [count]
  4405. Display contents of address @var{addr}, as
  4406. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  4407. or 8-bit bytes (@command{mdb}).
  4408. When the current target has an MMU which is present and active,
  4409. @var{addr} is interpreted as a virtual address.
  4410. Otherwise, or if the optional @var{phys} flag is specified,
  4411. @var{addr} is interpreted as a physical address.
  4412. If @var{count} is specified, displays that many units.
  4413. (If you want to manipulate the data instead of displaying it,
  4414. see the @code{mem2array} primitives.)
  4415. @end deffn
  4416. @deffn Command mww [phys] addr word
  4417. @deffnx Command mwh [phys] addr halfword
  4418. @deffnx Command mwb [phys] addr byte
  4419. Writes the specified @var{word} (32 bits),
  4420. @var{halfword} (16 bits), or @var{byte} (8-bit) value,
  4421. at the specified address @var{addr}.
  4422. When the current target has an MMU which is present and active,
  4423. @var{addr} is interpreted as a virtual address.
  4424. Otherwise, or if the optional @var{phys} flag is specified,
  4425. @var{addr} is interpreted as a physical address.
  4426. @end deffn
  4427. @anchor{Image access}
  4428. @section Image loading commands
  4429. @cindex image loading
  4430. @cindex image dumping
  4431. @anchor{dump_image}
  4432. @deffn Command {dump_image} filename address size
  4433. Dump @var{size} bytes of target memory starting at @var{address} to the
  4434. binary file named @var{filename}.
  4435. @end deffn
  4436. @deffn Command {fast_load}
  4437. Loads an image stored in memory by @command{fast_load_image} to the
  4438. current target. Must be preceeded by fast_load_image.
  4439. @end deffn
  4440. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4441. Normally you should be using @command{load_image} or GDB load. However, for
  4442. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  4443. host), storing the image in memory and uploading the image to the target
  4444. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  4445. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  4446. memory, i.e. does not affect target. This approach is also useful when profiling
  4447. target programming performance as I/O and target programming can easily be profiled
  4448. separately.
  4449. @end deffn
  4450. @anchor{load_image}
  4451. @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4452. Load image from file @var{filename} to target memory at @var{address}.
  4453. The file format may optionally be specified
  4454. (@option{bin}, @option{ihex}, or @option{elf})
  4455. @end deffn
  4456. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  4457. Displays image section sizes and addresses
  4458. as if @var{filename} were loaded into target memory
  4459. starting at @var{address} (defaults to zero).
  4460. The file format may optionally be specified
  4461. (@option{bin}, @option{ihex}, or @option{elf})
  4462. @end deffn
  4463. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4464. Verify @var{filename} against target memory starting at @var{address}.
  4465. The file format may optionally be specified
  4466. (@option{bin}, @option{ihex}, or @option{elf})
  4467. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  4468. @end deffn
  4469. @section Breakpoint and Watchpoint commands
  4470. @cindex breakpoint
  4471. @cindex watchpoint
  4472. CPUs often make debug modules accessible through JTAG, with
  4473. hardware support for a handful of code breakpoints and data
  4474. watchpoints.
  4475. In addition, CPUs almost always support software breakpoints.
  4476. @deffn Command {bp} [address len [@option{hw}]]
  4477. With no parameters, lists all active breakpoints.
  4478. Else sets a breakpoint on code execution starting
  4479. at @var{address} for @var{length} bytes.
  4480. This is a software breakpoint, unless @option{hw} is specified
  4481. in which case it will be a hardware breakpoint.
  4482. (@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
  4483. for similar mechanisms that do not consume hardware breakpoints.)
  4484. @end deffn
  4485. @deffn Command {rbp} address
  4486. Remove the breakpoint at @var{address}.
  4487. @end deffn
  4488. @deffn Command {rwp} address
  4489. Remove data watchpoint on @var{address}
  4490. @end deffn
  4491. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  4492. With no parameters, lists all active watchpoints.
  4493. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  4494. The watch point is an "access" watchpoint unless
  4495. the @option{r} or @option{w} parameter is provided,
  4496. defining it as respectively a read or write watchpoint.
  4497. If a @var{value} is provided, that value is used when determining if
  4498. the watchpoint should trigger. The value may be first be masked
  4499. using @var{mask} to mark ``don't care'' fields.
  4500. @end deffn
  4501. @section Misc Commands
  4502. @cindex profiling
  4503. @deffn Command {profile} seconds filename
  4504. Profiling samples the CPU's program counter as quickly as possible,
  4505. which is useful for non-intrusive stochastic profiling.
  4506. Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
  4507. @end deffn
  4508. @deffn Command {version}
  4509. Displays a string identifying the version of this OpenOCD server.
  4510. @end deffn
  4511. @deffn Command {virt2phys} virtual_address
  4512. Requests the current target to map the specified @var{virtual_address}
  4513. to its corresponding physical address, and displays the result.
  4514. @end deffn
  4515. @node Architecture and Core Commands
  4516. @chapter Architecture and Core Commands
  4517. @cindex Architecture Specific Commands
  4518. @cindex Core Specific Commands
  4519. Most CPUs have specialized JTAG operations to support debugging.
  4520. OpenOCD packages most such operations in its standard command framework.
  4521. Some of those operations don't fit well in that framework, so they are
  4522. exposed here as architecture or implementation (core) specific commands.
  4523. @anchor{ARM Hardware Tracing}
  4524. @section ARM Hardware Tracing
  4525. @cindex tracing
  4526. @cindex ETM
  4527. @cindex ETB
  4528. CPUs based on ARM cores may include standard tracing interfaces,
  4529. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  4530. address and data bus trace records to a ``Trace Port''.
  4531. @itemize
  4532. @item
  4533. Development-oriented boards will sometimes provide a high speed
  4534. trace connector for collecting that data, when the particular CPU
  4535. supports such an interface.
  4536. (The standard connector is a 38-pin Mictor, with both JTAG
  4537. and trace port support.)
  4538. Those trace connectors are supported by higher end JTAG adapters
  4539. and some logic analyzer modules; frequently those modules can
  4540. buffer several megabytes of trace data.
  4541. Configuring an ETM coupled to such an external trace port belongs
  4542. in the board-specific configuration file.
  4543. @item
  4544. If the CPU doesn't provide an external interface, it probably
  4545. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  4546. dedicated SRAM. 4KBytes is one common ETB size.
  4547. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  4548. (target) configuration file, since it works the same on all boards.
  4549. @end itemize
  4550. ETM support in OpenOCD doesn't seem to be widely used yet.
  4551. @quotation Issues
  4552. ETM support may be buggy, and at least some @command{etm config}
  4553. parameters should be detected by asking the ETM for them.
  4554. ETM trigger events could also implement a kind of complex
  4555. hardware breakpoint, much more powerful than the simple
  4556. watchpoint hardware exported by EmbeddedICE modules.
  4557. @emph{Such breakpoints can be triggered even when using the
  4558. dummy trace port driver}.
  4559. It seems like a GDB hookup should be possible,
  4560. as well as tracing only during specific states
  4561. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  4562. There should be GUI tools to manipulate saved trace data and help
  4563. analyse it in conjunction with the source code.
  4564. It's unclear how much of a common interface is shared
  4565. with the current XScale trace support, or should be
  4566. shared with eventual Nexus-style trace module support.
  4567. At this writing (November 2009) only ARM7, ARM9, and ARM11 support
  4568. for ETM modules is available. The code should be able to
  4569. work with some newer cores; but not all of them support
  4570. this original style of JTAG access.
  4571. @end quotation
  4572. @subsection ETM Configuration
  4573. ETM setup is coupled with the trace port driver configuration.
  4574. @deffn {Config Command} {etm config} target width mode clocking driver
  4575. Declares the ETM associated with @var{target}, and associates it
  4576. with a given trace port @var{driver}. @xref{Trace Port Drivers}.
  4577. Several of the parameters must reflect the trace port capabilities,
  4578. which are a function of silicon capabilties (exposed later
  4579. using @command{etm info}) and of what hardware is connected to
  4580. that port (such as an external pod, or ETB).
  4581. The @var{width} must be either 4, 8, or 16,
  4582. except with ETMv3.0 and newer modules which may also
  4583. support 1, 2, 24, 32, 48, and 64 bit widths.
  4584. (With those versions, @command{etm info} also shows whether
  4585. the selected port width and mode are supported.)
  4586. The @var{mode} must be @option{normal}, @option{multiplexed},
  4587. or @option{demultiplexed}.
  4588. The @var{clocking} must be @option{half} or @option{full}.
  4589. @quotation Warning
  4590. With ETMv3.0 and newer, the bits set with the @var{mode} and
  4591. @var{clocking} parameters both control the mode.
  4592. This modified mode does not map to the values supported by
  4593. previous ETM modules, so this syntax is subject to change.
  4594. @end quotation
  4595. @quotation Note
  4596. You can see the ETM registers using the @command{reg} command.
  4597. Not all possible registers are present in every ETM.
  4598. Most of the registers are write-only, and are used to configure
  4599. what CPU activities are traced.
  4600. @end quotation
  4601. @end deffn
  4602. @deffn Command {etm info}
  4603. Displays information about the current target's ETM.
  4604. This includes resource counts from the @code{ETM_CONFIG} register,
  4605. as well as silicon capabilities (except on rather old modules).
  4606. from the @code{ETM_SYS_CONFIG} register.
  4607. @end deffn
  4608. @deffn Command {etm status}
  4609. Displays status of the current target's ETM and trace port driver:
  4610. is the ETM idle, or is it collecting data?
  4611. Did trace data overflow?
  4612. Was it triggered?
  4613. @end deffn
  4614. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  4615. Displays what data that ETM will collect.
  4616. If arguments are provided, first configures that data.
  4617. When the configuration changes, tracing is stopped
  4618. and any buffered trace data is invalidated.
  4619. @itemize
  4620. @item @var{type} ... describing how data accesses are traced,
  4621. when they pass any ViewData filtering that that was set up.
  4622. The value is one of
  4623. @option{none} (save nothing),
  4624. @option{data} (save data),
  4625. @option{address} (save addresses),
  4626. @option{all} (save data and addresses)
  4627. @item @var{context_id_bits} ... 0, 8, 16, or 32
  4628. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  4629. cycle-accurate instruction tracing.
  4630. Before ETMv3, enabling this causes much extra data to be recorded.
  4631. @item @var{branch_output} ... @option{enable} or @option{disable}.
  4632. Disable this unless you need to try reconstructing the instruction
  4633. trace stream without an image of the code.
  4634. @end itemize
  4635. @end deffn
  4636. @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
  4637. Displays whether ETM triggering debug entry (like a breakpoint) is
  4638. enabled or disabled, after optionally modifying that configuration.
  4639. The default behaviour is @option{disable}.
  4640. Any change takes effect after the next @command{etm start}.
  4641. By using script commands to configure ETM registers, you can make the
  4642. processor enter debug state automatically when certain conditions,
  4643. more complex than supported by the breakpoint hardware, happen.
  4644. @end deffn
  4645. @subsection ETM Trace Operation
  4646. After setting up the ETM, you can use it to collect data.
  4647. That data can be exported to files for later analysis.
  4648. It can also be parsed with OpenOCD, for basic sanity checking.
  4649. To configure what is being traced, you will need to write
  4650. various trace registers using @command{reg ETM_*} commands.
  4651. For the definitions of these registers, read ARM publication
  4652. @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
  4653. Be aware that most of the relevant registers are write-only,
  4654. and that ETM resources are limited. There are only a handful
  4655. of address comparators, data comparators, counters, and so on.
  4656. Examples of scenarios you might arrange to trace include:
  4657. @itemize
  4658. @item Code flow within a function, @emph{excluding} subroutines
  4659. it calls. Use address range comparators to enable tracing
  4660. for instruction access within that function's body.
  4661. @item Code flow within a function, @emph{including} subroutines
  4662. it calls. Use the sequencer and address comparators to activate
  4663. tracing on an ``entered function'' state, then deactivate it by
  4664. exiting that state when the function's exit code is invoked.
  4665. @item Code flow starting at the fifth invocation of a function,
  4666. combining one of the above models with a counter.
  4667. @item CPU data accesses to the registers for a particular device,
  4668. using address range comparators and the ViewData logic.
  4669. @item Such data accesses only during IRQ handling, combining the above
  4670. model with sequencer triggers which on entry and exit to the IRQ handler.
  4671. @item @emph{... more}
  4672. @end itemize
  4673. At this writing, September 2009, there are no Tcl utility
  4674. procedures to help set up any common tracing scenarios.
  4675. @deffn Command {etm analyze}
  4676. Reads trace data into memory, if it wasn't already present.
  4677. Decodes and prints the data that was collected.
  4678. @end deffn
  4679. @deffn Command {etm dump} filename
  4680. Stores the captured trace data in @file{filename}.
  4681. @end deffn
  4682. @deffn Command {etm image} filename [base_address] [type]
  4683. Opens an image file.
  4684. @end deffn
  4685. @deffn Command {etm load} filename
  4686. Loads captured trace data from @file{filename}.
  4687. @end deffn
  4688. @deffn Command {etm start}
  4689. Starts trace data collection.
  4690. @end deffn
  4691. @deffn Command {etm stop}
  4692. Stops trace data collection.
  4693. @end deffn
  4694. @anchor{Trace Port Drivers}
  4695. @subsection Trace Port Drivers
  4696. To use an ETM trace port it must be associated with a driver.
  4697. @deffn {Trace Port Driver} dummy
  4698. Use the @option{dummy} driver if you are configuring an ETM that's
  4699. not connected to anything (on-chip ETB or off-chip trace connector).
  4700. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  4701. any trace data collection.}
  4702. @deffn {Config Command} {etm_dummy config} target
  4703. Associates the ETM for @var{target} with a dummy driver.
  4704. @end deffn
  4705. @end deffn
  4706. @deffn {Trace Port Driver} etb
  4707. Use the @option{etb} driver if you are configuring an ETM
  4708. to use on-chip ETB memory.
  4709. @deffn {Config Command} {etb config} target etb_tap
  4710. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  4711. You can see the ETB registers using the @command{reg} command.
  4712. @end deffn
  4713. @deffn Command {etb trigger_percent} [percent]
  4714. This displays, or optionally changes, ETB behavior after the
  4715. ETM's configured @emph{trigger} event fires.
  4716. It controls how much more trace data is saved after the (single)
  4717. trace trigger becomes active.
  4718. @itemize
  4719. @item The default corresponds to @emph{trace around} usage,
  4720. recording 50 percent data before the event and the rest
  4721. afterwards.
  4722. @item The minimum value of @var{percent} is 2 percent,
  4723. recording almost exclusively data before the trigger.
  4724. Such extreme @emph{trace before} usage can help figure out
  4725. what caused that event to happen.
  4726. @item The maximum value of @var{percent} is 100 percent,
  4727. recording data almost exclusively after the event.
  4728. This extreme @emph{trace after} usage might help sort out
  4729. how the event caused trouble.
  4730. @end itemize
  4731. @c REVISIT allow "break" too -- enter debug mode.
  4732. @end deffn
  4733. @end deffn
  4734. @deffn {Trace Port Driver} oocd_trace
  4735. This driver isn't available unless OpenOCD was explicitly configured
  4736. with the @option{--enable-oocd_trace} option. You probably don't want
  4737. to configure it unless you've built the appropriate prototype hardware;
  4738. it's @emph{proof-of-concept} software.
  4739. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  4740. connected to an off-chip trace connector.
  4741. @deffn {Config Command} {oocd_trace config} target tty
  4742. Associates the ETM for @var{target} with a trace driver which
  4743. collects data through the serial port @var{tty}.
  4744. @end deffn
  4745. @deffn Command {oocd_trace resync}
  4746. Re-synchronizes with the capture clock.
  4747. @end deffn
  4748. @deffn Command {oocd_trace status}
  4749. Reports whether the capture clock is locked or not.
  4750. @end deffn
  4751. @end deffn
  4752. @section Generic ARM
  4753. @cindex ARM
  4754. These commands should be available on all ARM processors.
  4755. They are available in addition to other core-specific
  4756. commands that may be available.
  4757. @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
  4758. Displays the core_state, optionally changing it to process
  4759. either @option{arm} or @option{thumb} instructions.
  4760. The target may later be resumed in the currently set core_state.
  4761. (Processors may also support the Jazelle state, but
  4762. that is not currently supported in OpenOCD.)
  4763. @end deffn
  4764. @deffn Command {arm disassemble} address [count [@option{thumb}]]
  4765. @cindex disassemble
  4766. Disassembles @var{count} instructions starting at @var{address}.
  4767. If @var{count} is not specified, a single instruction is disassembled.
  4768. If @option{thumb} is specified, or the low bit of the address is set,
  4769. Thumb2 (mixed 16/32-bit) instructions are used;
  4770. else ARM (32-bit) instructions are used.
  4771. (Processors may also support the Jazelle state, but
  4772. those instructions are not currently understood by OpenOCD.)
  4773. Note that all Thumb instructions are Thumb2 instructions,
  4774. so older processors (without Thumb2 support) will still
  4775. see correct disassembly of Thumb code.
  4776. Also, ThumbEE opcodes are the same as Thumb2,
  4777. with a handful of exceptions.
  4778. ThumbEE disassembly currently has no explicit support.
  4779. @end deffn
  4780. @deffn Command {arm mcr} pX op1 CRn CRm op2 value
  4781. Write @var{value} to a coprocessor @var{pX} register
  4782. passing parameters @var{CRn},
  4783. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  4784. and using the MCR instruction.
  4785. (Parameter sequence matches the ARM instruction, but omits
  4786. an ARM register.)
  4787. @end deffn
  4788. @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
  4789. Read a coprocessor @var{pX} register passing parameters @var{CRn},
  4790. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  4791. and the MRC instruction.
  4792. Returns the result so it can be manipulated by Jim scripts.
  4793. (Parameter sequence matches the ARM instruction, but omits
  4794. an ARM register.)
  4795. @end deffn
  4796. @deffn Command {arm reg}
  4797. Display a table of all banked core registers, fetching the current value from every
  4798. core mode if necessary.
  4799. @end deffn
  4800. @section ARMv4 and ARMv5 Architecture
  4801. @cindex ARMv4
  4802. @cindex ARMv5
  4803. The ARMv4 and ARMv5 architectures are widely used in embedded systems,
  4804. and introduced core parts of the instruction set in use today.
  4805. That includes the Thumb instruction set, introduced in the ARMv4T
  4806. variant.
  4807. @subsection ARM7 and ARM9 specific commands
  4808. @cindex ARM7
  4809. @cindex ARM9
  4810. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  4811. ARM9TDMI, ARM920T or ARM926EJ-S.
  4812. They are available in addition to the ARM commands,
  4813. and any other core-specific commands that may be available.
  4814. @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
  4815. Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
  4816. instead of breakpoints. This should be
  4817. safe for all but ARM7TDMI--S cores (like Philips LPC).
  4818. This feature is enabled by default on most ARM9 cores,
  4819. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  4820. @end deffn
  4821. @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
  4822. @cindex DCC
  4823. Control the use of the debug communications channel (DCC) to write larger (>128 byte)
  4824. amounts of memory. DCC downloads offer a huge speed increase, but might be
  4825. unsafe, especially with targets running at very low speeds. This command was introduced
  4826. with OpenOCD rev. 60, and requires a few bytes of working area.
  4827. @end deffn
  4828. @anchor{arm7_9 fast_memory_access}
  4829. @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
  4830. Enable or disable memory writes and reads that don't check completion of
  4831. the operation. This provides a huge speed increase, especially with USB JTAG
  4832. cables (FT2232), but might be unsafe if used with targets running at very low
  4833. speeds, like the 32kHz startup clock of an AT91RM9200.
  4834. @end deffn
  4835. @deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
  4836. @cindex ARM semihosting
  4837. Display status of semihosting, after optionally changing that status.
  4838. Semihosting allows for code executing on an ARM target to use the
  4839. I/O facilities on the host computer i.e. the system where OpenOCD
  4840. is running. The target application must be linked against a library
  4841. implementing the ARM semihosting convention that forwards operation
  4842. requests by using a special SVC instruction that is trapped at the
  4843. Supervisor Call vector by OpenOCD.
  4844. @end deffn
  4845. @subsection ARM720T specific commands
  4846. @cindex ARM720T
  4847. These commands are available to ARM720T based CPUs,
  4848. which are implementations of the ARMv4T architecture
  4849. based on the ARM7TDMI-S integer core.
  4850. They are available in addition to the ARM and ARM7/ARM9 commands.
  4851. @deffn Command {arm720t cp15} regnum [value]
  4852. Display cp15 register @var{regnum};
  4853. else if a @var{value} is provided, that value is written to that register.
  4854. @end deffn
  4855. @subsection ARM9 specific commands
  4856. @cindex ARM9
  4857. ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
  4858. integer processors.
  4859. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  4860. @c 9-june-2009: tried this on arm920t, it didn't work.
  4861. @c no-params always lists nothing caught, and that's how it acts.
  4862. @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
  4863. @c versions have different rules about when they commit writes.
  4864. @anchor{arm9 vector_catch}
  4865. @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
  4866. @cindex vector_catch
  4867. Vector Catch hardware provides a sort of dedicated breakpoint
  4868. for hardware events such as reset, interrupt, and abort.
  4869. You can use this to conserve normal breakpoint resources,
  4870. so long as you're not concerned with code that branches directly
  4871. to those hardware vectors.
  4872. This always finishes by listing the current configuration.
  4873. If parameters are provided, it first reconfigures the
  4874. vector catch hardware to intercept
  4875. @option{all} of the hardware vectors,
  4876. @option{none} of them,
  4877. or a list with one or more of the following:
  4878. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
  4879. @option{irq} @option{fiq}.
  4880. @end deffn
  4881. @subsection ARM920T specific commands
  4882. @cindex ARM920T
  4883. These commands are available to ARM920T based CPUs,
  4884. which are implementations of the ARMv4T architecture
  4885. built using the ARM9TDMI integer core.
  4886. They are available in addition to the ARM, ARM7/ARM9,
  4887. and ARM9 commands.
  4888. @deffn Command {arm920t cache_info}
  4889. Print information about the caches found. This allows to see whether your target
  4890. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  4891. @end deffn
  4892. @deffn Command {arm920t cp15} regnum [value]
  4893. Display cp15 register @var{regnum};
  4894. else if a @var{value} is provided, that value is written to that register.
  4895. @end deffn
  4896. @deffn Command {arm920t cp15i} opcode [value [address]]
  4897. Interpreted access using cp15 @var{opcode}.
  4898. If no @var{value} is provided, the result is displayed.
  4899. Else if that value is written using the specified @var{address},
  4900. or using zero if no other address is not provided.
  4901. @end deffn
  4902. @deffn Command {arm920t read_cache} filename
  4903. Dump the content of ICache and DCache to a file named @file{filename}.
  4904. @end deffn
  4905. @deffn Command {arm920t read_mmu} filename
  4906. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  4907. @end deffn
  4908. @subsection ARM926ej-s specific commands
  4909. @cindex ARM926ej-s
  4910. These commands are available to ARM926ej-s based CPUs,
  4911. which are implementations of the ARMv5TEJ architecture
  4912. based on the ARM9EJ-S integer core.
  4913. They are available in addition to the ARM, ARM7/ARM9,
  4914. and ARM9 commands.
  4915. The Feroceon cores also support these commands, although
  4916. they are not built from ARM926ej-s designs.
  4917. @deffn Command {arm926ejs cache_info}
  4918. Print information about the caches found.
  4919. @end deffn
  4920. @subsection ARM966E specific commands
  4921. @cindex ARM966E
  4922. These commands are available to ARM966 based CPUs,
  4923. which are implementations of the ARMv5TE architecture.
  4924. They are available in addition to the ARM, ARM7/ARM9,
  4925. and ARM9 commands.
  4926. @deffn Command {arm966e cp15} regnum [value]
  4927. Display cp15 register @var{regnum};
  4928. else if a @var{value} is provided, that value is written to that register.
  4929. @end deffn
  4930. @subsection XScale specific commands
  4931. @cindex XScale
  4932. Some notes about the debug implementation on the XScale CPUs:
  4933. The XScale CPU provides a special debug-only mini-instruction cache
  4934. (mini-IC) in which exception vectors and target-resident debug handler
  4935. code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
  4936. must point vector 0 (the reset vector) to the entry of the debug
  4937. handler. However, this means that the complete first cacheline in the
  4938. mini-IC is marked valid, which makes the CPU fetch all exception
  4939. handlers from the mini-IC, ignoring the code in RAM.
  4940. OpenOCD currently does not sync the mini-IC entries with the RAM
  4941. contents (which would fail anyway while the target is running), so
  4942. the user must provide appropriate values using the @code{xscale
  4943. vector_table} command.
  4944. It is recommended to place a pc-relative indirect branch in the vector
  4945. table, and put the branch destination somewhere in memory. Doing so
  4946. makes sure the code in the vector table stays constant regardless of
  4947. code layout in memory:
  4948. @example
  4949. _vectors:
  4950. ldr pc,[pc,#0x100-8]
  4951. ldr pc,[pc,#0x100-8]
  4952. ldr pc,[pc,#0x100-8]
  4953. ldr pc,[pc,#0x100-8]
  4954. ldr pc,[pc,#0x100-8]
  4955. ldr pc,[pc,#0x100-8]
  4956. ldr pc,[pc,#0x100-8]
  4957. ldr pc,[pc,#0x100-8]
  4958. .org 0x100
  4959. .long real_reset_vector
  4960. .long real_ui_handler
  4961. .long real_swi_handler
  4962. .long real_pf_abort
  4963. .long real_data_abort
  4964. .long 0 /* unused */
  4965. .long real_irq_handler
  4966. .long real_fiq_handler
  4967. @end example
  4968. The debug handler must be placed somewhere in the address space using
  4969. the @code{xscale debug_handler} command. The allowed locations for the
  4970. debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
  4971. 0xfffff800). The default value is 0xfe000800.
  4972. These commands are available to XScale based CPUs,
  4973. which are implementations of the ARMv5TE architecture.
  4974. @deffn Command {xscale analyze_trace}
  4975. Displays the contents of the trace buffer.
  4976. @end deffn
  4977. @deffn Command {xscale cache_clean_address} address
  4978. Changes the address used when cleaning the data cache.
  4979. @end deffn
  4980. @deffn Command {xscale cache_info}
  4981. Displays information about the CPU caches.
  4982. @end deffn
  4983. @deffn Command {xscale cp15} regnum [value]
  4984. Display cp15 register @var{regnum};
  4985. else if a @var{value} is provided, that value is written to that register.
  4986. @end deffn
  4987. @deffn Command {xscale debug_handler} target address
  4988. Changes the address used for the specified target's debug handler.
  4989. @end deffn
  4990. @deffn Command {xscale dcache} (@option{enable}|@option{disable})
  4991. Enables or disable the CPU's data cache.
  4992. @end deffn
  4993. @deffn Command {xscale dump_trace} filename
  4994. Dumps the raw contents of the trace buffer to @file{filename}.
  4995. @end deffn
  4996. @deffn Command {xscale icache} (@option{enable}|@option{disable})
  4997. Enables or disable the CPU's instruction cache.
  4998. @end deffn
  4999. @deffn Command {xscale mmu} (@option{enable}|@option{disable})
  5000. Enables or disable the CPU's memory management unit.
  5001. @end deffn
  5002. @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
  5003. Enables or disables the trace buffer,
  5004. and controls how it is emptied.
  5005. @end deffn
  5006. @deffn Command {xscale trace_image} filename [offset [type]]
  5007. Opens a trace image from @file{filename}, optionally rebasing
  5008. its segment addresses by @var{offset}.
  5009. The image @var{type} may be one of
  5010. @option{bin} (binary), @option{ihex} (Intel hex),
  5011. @option{elf} (ELF file), @option{s19} (Motorola s19),
  5012. @option{mem}, or @option{builder}.
  5013. @end deffn
  5014. @anchor{xscale vector_catch}
  5015. @deffn Command {xscale vector_catch} [mask]
  5016. @cindex vector_catch
  5017. Display a bitmask showing the hardware vectors to catch.
  5018. If the optional parameter is provided, first set the bitmask to that value.
  5019. The mask bits correspond with bit 16..23 in the DCSR:
  5020. @example
  5021. 0x01 Trap Reset
  5022. 0x02 Trap Undefined Instructions
  5023. 0x04 Trap Software Interrupt
  5024. 0x08 Trap Prefetch Abort
  5025. 0x10 Trap Data Abort
  5026. 0x20 reserved
  5027. 0x40 Trap IRQ
  5028. 0x80 Trap FIQ
  5029. @end example
  5030. @end deffn
  5031. @anchor{xscale vector_table}
  5032. @deffn Command {xscale vector_table} [<low|high> <index> <value>]
  5033. @cindex vector_table
  5034. Set an entry in the mini-IC vector table. There are two tables: one for
  5035. low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
  5036. holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
  5037. points to the debug handler entry and can not be overwritten.
  5038. @var{value} holds the 32-bit opcode that is placed in the mini-IC.
  5039. Without arguments, the current settings are displayed.
  5040. @end deffn
  5041. @section ARMv6 Architecture
  5042. @cindex ARMv6
  5043. @subsection ARM11 specific commands
  5044. @cindex ARM11
  5045. @deffn Command {arm11 memwrite burst} [value]
  5046. Displays the value of the memwrite burst-enable flag,
  5047. which is enabled by default. Burst writes are only used
  5048. for memory writes larger than 1 word. Single word writes
  5049. are likely to be from reset init scripts and those writes
  5050. are often to non-memory locations which could easily have
  5051. many wait states, which could easily break burst writes.
  5052. If @var{value} is defined, first assigns that.
  5053. @end deffn
  5054. @deffn Command {arm11 memwrite error_fatal} [value]
  5055. Displays the value of the memwrite error_fatal flag,
  5056. which is enabled by default.
  5057. If @var{value} is defined, first assigns that.
  5058. @end deffn
  5059. @deffn Command {arm11 step_irq_enable} [value]
  5060. Displays the value of the flag controlling whether
  5061. IRQs are enabled during single stepping;
  5062. they are disabled by default.
  5063. If @var{value} is defined, first assigns that.
  5064. @end deffn
  5065. @deffn Command {arm11 vcr} [value]
  5066. @cindex vector_catch
  5067. Displays the value of the @emph{Vector Catch Register (VCR)},
  5068. coprocessor 14 register 7.
  5069. If @var{value} is defined, first assigns that.
  5070. Vector Catch hardware provides dedicated breakpoints
  5071. for certain hardware events.
  5072. The specific bit values are core-specific (as in fact is using
  5073. coprocessor 14 register 7 itself) but all current ARM11
  5074. cores @emph{except the ARM1176} use the same six bits.
  5075. @end deffn
  5076. @section ARMv7 Architecture
  5077. @cindex ARMv7
  5078. @subsection ARMv7 Debug Access Port (DAP) specific commands
  5079. @cindex Debug Access Port
  5080. @cindex DAP
  5081. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  5082. included on Cortex-M3 and Cortex-A8 systems.
  5083. They are available in addition to other core-specific commands that may be available.
  5084. @deffn Command {dap info} [num]
  5085. Displays dap info for ap @var{num}, defaulting to the currently selected AP.
  5086. @end deffn
  5087. @deffn Command {dap apsel} [num]
  5088. Select AP @var{num}, defaulting to 0.
  5089. @end deffn
  5090. @deffn Command {dap apid} [num]
  5091. Displays id register from AP @var{num},
  5092. defaulting to the currently selected AP.
  5093. @end deffn
  5094. @deffn Command {dap baseaddr} [num]
  5095. Displays debug base address from AP @var{num},
  5096. defaulting to the currently selected AP.
  5097. @end deffn
  5098. @deffn Command {dap memaccess} [value]
  5099. Displays the number of extra tck for mem-ap memory bus access [0-255].
  5100. If @var{value} is defined, first assigns that.
  5101. @end deffn
  5102. @subsection Cortex-M3 specific commands
  5103. @cindex Cortex-M3
  5104. @deffn Command {cortex_m3 disassemble} address [count]
  5105. @cindex disassemble
  5106. Disassembles @var{count} Thumb2 instructions starting at @var{address}.
  5107. If @var{count} is not specified, a single instruction is disassembled.
  5108. @end deffn
  5109. @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
  5110. Control masking (disabling) interrupts during target step/resume.
  5111. @end deffn
  5112. @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
  5113. @cindex vector_catch
  5114. Vector Catch hardware provides dedicated breakpoints
  5115. for certain hardware events.
  5116. Parameters request interception of
  5117. @option{all} of these hardware event vectors,
  5118. @option{none} of them,
  5119. or one or more of the following:
  5120. @option{hard_err} for a HardFault exception;
  5121. @option{mm_err} for a MemManage exception;
  5122. @option{bus_err} for a BusFault exception;
  5123. @option{irq_err},
  5124. @option{state_err},
  5125. @option{chk_err}, or
  5126. @option{nocp_err} for various UsageFault exceptions; or
  5127. @option{reset}.
  5128. If NVIC setup code does not enable them,
  5129. MemManage, BusFault, and UsageFault exceptions
  5130. are mapped to HardFault.
  5131. UsageFault checks for
  5132. divide-by-zero and unaligned access
  5133. must also be explicitly enabled.
  5134. This finishes by listing the current vector catch configuration.
  5135. @end deffn
  5136. @anchor{Software Debug Messages and Tracing}
  5137. @section Software Debug Messages and Tracing
  5138. @cindex Linux-ARM DCC support
  5139. @cindex tracing
  5140. @cindex libdcc
  5141. @cindex DCC
  5142. OpenOCD can process certain requests from target software, when
  5143. the target uses appropriate libraries.
  5144. The most powerful mechanism is semihosting, but there is also
  5145. a lighter weight mechanism using only the DCC channel.
  5146. Currently @command{target_request debugmsgs}
  5147. is supported only for @option{arm7_9} and @option{cortex_m3} cores.
  5148. These messages are received as part of target polling, so
  5149. you need to have @command{poll on} active to receive them.
  5150. They are intrusive in that they will affect program execution
  5151. times. If that is a problem, @pxref{ARM Hardware Tracing}.
  5152. See @file{libdcc} in the contrib dir for more details.
  5153. In addition to sending strings, characters, and
  5154. arrays of various size integers from the target,
  5155. @file{libdcc} also exports a software trace point mechanism.
  5156. The target being debugged may
  5157. issue trace messages which include a 24-bit @dfn{trace point} number.
  5158. Trace point support includes two distinct mechanisms,
  5159. each supported by a command:
  5160. @itemize
  5161. @item @emph{History} ... A circular buffer of trace points
  5162. can be set up, and then displayed at any time.
  5163. This tracks where code has been, which can be invaluable in
  5164. finding out how some fault was triggered.
  5165. The buffer may overflow, since it collects records continuously.
  5166. It may be useful to use some of the 24 bits to represent a
  5167. particular event, and other bits to hold data.
  5168. @item @emph{Counting} ... An array of counters can be set up,
  5169. and then displayed at any time.
  5170. This can help establish code coverage and identify hot spots.
  5171. The array of counters is directly indexed by the trace point
  5172. number, so trace points with higher numbers are not counted.
  5173. @end itemize
  5174. Linux-ARM kernels have a ``Kernel low-level debugging
  5175. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  5176. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  5177. deliver messages before a serial console can be activated.
  5178. This is not the same format used by @file{libdcc}.
  5179. Other software, such as the U-Boot boot loader, sometimes
  5180. does the same thing.
  5181. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  5182. Displays current handling of target DCC message requests.
  5183. These messages may be sent to the debugger while the target is running.
  5184. The optional @option{enable} and @option{charmsg} parameters
  5185. both enable the messages, while @option{disable} disables them.
  5186. With @option{charmsg} the DCC words each contain one character,
  5187. as used by Linux with CONFIG_DEBUG_ICEDCC;
  5188. otherwise the libdcc format is used.
  5189. @end deffn
  5190. @deffn Command {trace history} [@option{clear}|count]
  5191. With no parameter, displays all the trace points that have triggered
  5192. in the order they triggered.
  5193. With the parameter @option{clear}, erases all current trace history records.
  5194. With a @var{count} parameter, allocates space for that many
  5195. history records.
  5196. @end deffn
  5197. @deffn Command {trace point} [@option{clear}|identifier]
  5198. With no parameter, displays all trace point identifiers and how many times
  5199. they have been triggered.
  5200. With the parameter @option{clear}, erases all current trace point counters.
  5201. With a numeric @var{identifier} parameter, creates a new a trace point counter
  5202. and associates it with that identifier.
  5203. @emph{Important:} The identifier and the trace point number
  5204. are not related except by this command.
  5205. These trace point numbers always start at zero (from server startup,
  5206. or after @command{trace point clear}) and count up from there.
  5207. @end deffn
  5208. @node JTAG Commands
  5209. @chapter JTAG Commands
  5210. @cindex JTAG Commands
  5211. Most general purpose JTAG commands have been presented earlier.
  5212. (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  5213. Lower level JTAG commands, as presented here,
  5214. may be needed to work with targets which require special
  5215. attention during operations such as reset or initialization.
  5216. To use these commands you will need to understand some
  5217. of the basics of JTAG, including:
  5218. @itemize @bullet
  5219. @item A JTAG scan chain consists of a sequence of individual TAP
  5220. devices such as a CPUs.
  5221. @item Control operations involve moving each TAP through the same
  5222. standard state machine (in parallel)
  5223. using their shared TMS and clock signals.
  5224. @item Data transfer involves shifting data through the chain of
  5225. instruction or data registers of each TAP, writing new register values
  5226. while the reading previous ones.
  5227. @item Data register sizes are a function of the instruction active in
  5228. a given TAP, while instruction register sizes are fixed for each TAP.
  5229. All TAPs support a BYPASS instruction with a single bit data register.
  5230. @item The way OpenOCD differentiates between TAP devices is by
  5231. shifting different instructions into (and out of) their instruction
  5232. registers.
  5233. @end itemize
  5234. @section Low Level JTAG Commands
  5235. These commands are used by developers who need to access
  5236. JTAG instruction or data registers, possibly controlling
  5237. the order of TAP state transitions.
  5238. If you're not debugging OpenOCD internals, or bringing up a
  5239. new JTAG adapter or a new type of TAP device (like a CPU or
  5240. JTAG router), you probably won't need to use these commands.
  5241. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  5242. Loads the data register of @var{tap} with a series of bit fields
  5243. that specify the entire register.
  5244. Each field is @var{numbits} bits long with
  5245. a numeric @var{value} (hexadecimal encouraged).
  5246. The return value holds the original value of each
  5247. of those fields.
  5248. For example, a 38 bit number might be specified as one
  5249. field of 32 bits then one of 6 bits.
  5250. @emph{For portability, never pass fields which are more
  5251. than 32 bits long. Many OpenOCD implementations do not
  5252. support 64-bit (or larger) integer values.}
  5253. All TAPs other than @var{tap} must be in BYPASS mode.
  5254. The single bit in their data registers does not matter.
  5255. When @var{tap_state} is specified, the JTAG state machine is left
  5256. in that state.
  5257. For example @sc{drpause} might be specified, so that more
  5258. instructions can be issued before re-entering the @sc{run/idle} state.
  5259. If the end state is not specified, the @sc{run/idle} state is entered.
  5260. @quotation Warning
  5261. OpenOCD does not record information about data register lengths,
  5262. so @emph{it is important that you get the bit field lengths right}.
  5263. Remember that different JTAG instructions refer to different
  5264. data registers, which may have different lengths.
  5265. Moreover, those lengths may not be fixed;
  5266. the SCAN_N instruction can change the length of
  5267. the register accessed by the INTEST instruction
  5268. (by connecting a different scan chain).
  5269. @end quotation
  5270. @end deffn
  5271. @deffn Command {flush_count}
  5272. Returns the number of times the JTAG queue has been flushed.
  5273. This may be used for performance tuning.
  5274. For example, flushing a queue over USB involves a
  5275. minimum latency, often several milliseconds, which does
  5276. not change with the amount of data which is written.
  5277. You may be able to identify performance problems by finding
  5278. tasks which waste bandwidth by flushing small transfers too often,
  5279. instead of batching them into larger operations.
  5280. @end deffn
  5281. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  5282. For each @var{tap} listed, loads the instruction register
  5283. with its associated numeric @var{instruction}.
  5284. (The number of bits in that instruction may be displayed
  5285. using the @command{scan_chain} command.)
  5286. For other TAPs, a BYPASS instruction is loaded.
  5287. When @var{tap_state} is specified, the JTAG state machine is left
  5288. in that state.
  5289. For example @sc{irpause} might be specified, so the data register
  5290. can be loaded before re-entering the @sc{run/idle} state.
  5291. If the end state is not specified, the @sc{run/idle} state is entered.
  5292. @quotation Note
  5293. OpenOCD currently supports only a single field for instruction
  5294. register values, unlike data register values.
  5295. For TAPs where the instruction register length is more than 32 bits,
  5296. portable scripts currently must issue only BYPASS instructions.
  5297. @end quotation
  5298. @end deffn
  5299. @deffn Command {jtag_reset} trst srst
  5300. Set values of reset signals.
  5301. The @var{trst} and @var{srst} parameter values may be
  5302. @option{0}, indicating that reset is inactive (pulled or driven high),
  5303. or @option{1}, indicating it is active (pulled or driven low).
  5304. The @command{reset_config} command should already have been used
  5305. to configure how the board and JTAG adapter treat these two
  5306. signals, and to say if either signal is even present.
  5307. @xref{Reset Configuration}.
  5308. Note that TRST is specially handled.
  5309. It actually signifies JTAG's @sc{reset} state.
  5310. So if the board doesn't support the optional TRST signal,
  5311. or it doesn't support it along with the specified SRST value,
  5312. JTAG reset is triggered with TMS and TCK signals
  5313. instead of the TRST signal.
  5314. And no matter how that JTAG reset is triggered, once
  5315. the scan chain enters @sc{reset} with TRST inactive,
  5316. TAP @code{post-reset} events are delivered to all TAPs
  5317. with handlers for that event.
  5318. @end deffn
  5319. @deffn Command {pathmove} start_state [next_state ...]
  5320. Start by moving to @var{start_state}, which
  5321. must be one of the @emph{stable} states.
  5322. Unless it is the only state given, this will often be the
  5323. current state, so that no TCK transitions are needed.
  5324. Then, in a series of single state transitions
  5325. (conforming to the JTAG state machine) shift to
  5326. each @var{next_state} in sequence, one per TCK cycle.
  5327. The final state must also be stable.
  5328. @end deffn
  5329. @deffn Command {runtest} @var{num_cycles}
  5330. Move to the @sc{run/idle} state, and execute at least
  5331. @var{num_cycles} of the JTAG clock (TCK).
  5332. Instructions often need some time
  5333. to execute before they take effect.
  5334. @end deffn
  5335. @c tms_sequence (short|long)
  5336. @c ... temporary, debug-only, other than USBprog bug workaround...
  5337. @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
  5338. Verify values captured during @sc{ircapture} and returned
  5339. during IR scans. Default is enabled, but this can be
  5340. overridden by @command{verify_jtag}.
  5341. This flag is ignored when validating JTAG chain configuration.
  5342. @end deffn
  5343. @deffn Command {verify_jtag} (@option{enable}|@option{disable})
  5344. Enables verification of DR and IR scans, to help detect
  5345. programming errors. For IR scans, @command{verify_ircapture}
  5346. must also be enabled.
  5347. Default is enabled.
  5348. @end deffn
  5349. @section TAP state names
  5350. @cindex TAP state names
  5351. The @var{tap_state} names used by OpenOCD in the @command{drscan},
  5352. @command{irscan}, and @command{pathmove} commands are the same
  5353. as those used in SVF boundary scan documents, except that
  5354. SVF uses @sc{idle} instead of @sc{run/idle}.
  5355. @itemize @bullet
  5356. @item @b{RESET} ... @emph{stable} (with TMS high);
  5357. acts as if TRST were pulsed
  5358. @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
  5359. @item @b{DRSELECT}
  5360. @item @b{DRCAPTURE}
  5361. @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
  5362. through the data register
  5363. @item @b{DREXIT1}
  5364. @item @b{DRPAUSE} ... @emph{stable}; data register ready
  5365. for update or more shifting
  5366. @item @b{DREXIT2}
  5367. @item @b{DRUPDATE}
  5368. @item @b{IRSELECT}
  5369. @item @b{IRCAPTURE}
  5370. @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
  5371. through the instruction register
  5372. @item @b{IREXIT1}
  5373. @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
  5374. for update or more shifting
  5375. @item @b{IREXIT2}
  5376. @item @b{IRUPDATE}
  5377. @end itemize
  5378. Note that only six of those states are fully ``stable'' in the
  5379. face of TMS fixed (low except for @sc{reset})
  5380. and a free-running JTAG clock. For all the
  5381. others, the next TCK transition changes to a new state.
  5382. @itemize @bullet
  5383. @item From @sc{drshift} and @sc{irshift}, clock transitions will
  5384. produce side effects by changing register contents. The values
  5385. to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
  5386. may not be as expected.
  5387. @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
  5388. choices after @command{drscan} or @command{irscan} commands,
  5389. since they are free of JTAG side effects.
  5390. @item @sc{run/idle} may have side effects that appear at non-JTAG
  5391. levels, such as advancing the ARM9E-S instruction pipeline.
  5392. Consult the documentation for the TAP(s) you are working with.
  5393. @end itemize
  5394. @node Boundary Scan Commands
  5395. @chapter Boundary Scan Commands
  5396. One of the original purposes of JTAG was to support
  5397. boundary scan based hardware testing.
  5398. Although its primary focus is to support On-Chip Debugging,
  5399. OpenOCD also includes some boundary scan commands.
  5400. @section SVF: Serial Vector Format
  5401. @cindex Serial Vector Format
  5402. @cindex SVF
  5403. The Serial Vector Format, better known as @dfn{SVF}, is a
  5404. way to represent JTAG test patterns in text files.
  5405. OpenOCD supports running such test files.
  5406. @deffn Command {svf} filename [@option{quiet}]
  5407. This issues a JTAG reset (Test-Logic-Reset) and then
  5408. runs the SVF script from @file{filename}.
  5409. Unless the @option{quiet} option is specified,
  5410. each command is logged before it is executed.
  5411. @end deffn
  5412. @section XSVF: Xilinx Serial Vector Format
  5413. @cindex Xilinx Serial Vector Format
  5414. @cindex XSVF
  5415. The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
  5416. binary representation of SVF which is optimized for use with
  5417. Xilinx devices.
  5418. OpenOCD supports running such test files.
  5419. @quotation Important
  5420. Not all XSVF commands are supported.
  5421. @end quotation
  5422. @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
  5423. This issues a JTAG reset (Test-Logic-Reset) and then
  5424. runs the XSVF script from @file{filename}.
  5425. When a @var{tapname} is specified, the commands are directed at
  5426. that TAP.
  5427. When @option{virt2} is specified, the @sc{xruntest} command counts
  5428. are interpreted as TCK cycles instead of microseconds.
  5429. Unless the @option{quiet} option is specified,
  5430. messages are logged for comments and some retries.
  5431. @end deffn
  5432. The OpenOCD sources also include two utility scripts
  5433. for working with XSVF; they are not currently installed
  5434. after building the software.
  5435. You may find them useful:
  5436. @itemize
  5437. @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
  5438. syntax understood by the @command{xsvf} command; see notes below.
  5439. @item @emph{xsvfdump} ... converts XSVF files into a text output format;
  5440. understands the OpenOCD extensions.
  5441. @end itemize
  5442. The input format accepts a handful of non-standard extensions.
  5443. These include three opcodes corresponding to SVF extensions
  5444. from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
  5445. two opcodes supporting a more accurate translation of SVF
  5447. If @emph{xsvfdump} shows a file is using those opcodes, it
  5448. probably will not be usable with other XSVF tools.
  5449. @node TFTP
  5450. @chapter TFTP
  5451. @cindex TFTP
  5452. If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
  5453. be used to access files on PCs (either the developer's PC or some other PC).
  5454. The way this works on the ZY1000 is to prefix a filename by
  5455. "/tftp/ip/" and append the TFTP path on the TFTP
  5456. server (tftpd). For example,
  5457. @example
  5458. load_image /tftp/\temp\abc.elf
  5459. @end example
  5460. will load c:\temp\abc.elf from the developer pc ( into memory as
  5461. if the file was hosted on the embedded host.
  5462. In order to achieve decent performance, you must choose a TFTP server
  5463. that supports a packet size bigger than the default packet size (512 bytes). There
  5464. are numerous TFTP servers out there (free and commercial) and you will have to do
  5465. a bit of googling to find something that fits your requirements.
  5466. @node GDB and OpenOCD
  5467. @chapter GDB and OpenOCD
  5468. @cindex GDB
  5469. OpenOCD complies with the remote gdbserver protocol, and as such can be used
  5470. to debug remote targets.
  5471. Setting up GDB to work with OpenOCD can involve several components:
  5472. @itemize
  5473. @item OpenOCD itself may need to be configured. @xref{GDB Configuration}.
  5474. @item GDB itself may need configuration, as shown in this chapter.
  5475. @item If you have a GUI environment like Eclipse,
  5476. that also will probably need to be configured.
  5477. @end itemize
  5478. Of course, the version of GDB you use will need to be one which has
  5479. been built to know about the target CPU you're using. It's probably
  5480. part of the tool chain you're using. For example, if you are doing
  5481. cross-development for ARM on an x86 PC, instead of using the native
  5482. x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
  5483. if that's the tool chain used to compile your code.
  5484. @anchor{Connecting to GDB}
  5485. @section Connecting to GDB
  5486. @cindex Connecting to GDB
  5487. Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
  5488. instance GDB 6.3 has a known bug that produces bogus memory access
  5489. errors, which has since been fixed: look up 1836 in
  5490. @url{}
  5491. OpenOCD can communicate with GDB in two ways:
  5492. @enumerate
  5493. @item
  5494. A socket (TCP/IP) connection is typically started as follows:
  5495. @example
  5496. target remote localhost:3333
  5497. @end example
  5498. This would cause GDB to connect to the gdbserver on the local pc using port 3333.
  5499. @item
  5500. A pipe connection is typically started as follows:
  5501. @example
  5502. target remote | openocd --pipe
  5503. @end example
  5504. This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
  5505. Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
  5506. session.
  5507. @end enumerate
  5508. To list the available OpenOCD commands type @command{monitor help} on the
  5509. GDB command line.
  5510. @section Configuring GDB for OpenOCD
  5511. OpenOCD supports the gdb @option{qSupported} packet, this enables information
  5512. to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
  5513. packet size and the device's memory map.
  5514. You do not need to configure the packet size by hand,
  5515. and the relevant parts of the memory map should be automatically
  5516. set up when you declare (NOR) flash banks.
  5517. However, there are other things which GDB can't currently query.
  5518. You may need to set those up by hand.
  5519. As OpenOCD starts up, you will often see a line reporting
  5520. something like:
  5521. @example
  5522. Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
  5523. @end example
  5524. You can pass that information to GDB with these commands:
  5525. @example
  5526. set remote hardware-breakpoint-limit 6
  5527. set remote hardware-watchpoint-limit 4
  5528. @end example
  5529. With that particular hardware (Cortex-M3) the hardware breakpoints
  5530. only work for code running from flash memory. Most other ARM systems
  5531. do not have such restrictions.
  5532. @section Programming using GDB
  5533. @cindex Programming using GDB
  5534. By default the target memory map is sent to GDB. This can be disabled by
  5535. the following OpenOCD configuration option:
  5536. @example
  5537. gdb_memory_map disable
  5538. @end example
  5539. For this to function correctly a valid flash configuration must also be set
  5540. in OpenOCD. For faster performance you should also configure a valid
  5541. working area.
  5542. Informing GDB of the memory map of the target will enable GDB to protect any
  5543. flash areas of the target and use hardware breakpoints by default. This means
  5544. that the OpenOCD option @command{gdb_breakpoint_override} is not required when
  5545. using a memory map. @xref{gdb_breakpoint_override}.
  5546. To view the configured memory map in GDB, use the GDB command @option{info mem}
  5547. All other unassigned addresses within GDB are treated as RAM.
  5548. GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
  5549. This can be changed to the old behaviour by using the following GDB command
  5550. @example
  5551. set mem inaccessible-by-default off
  5552. @end example
  5553. If @command{gdb_flash_program enable} is also used, GDB will be able to
  5554. program any flash memory using the vFlash interface.
  5555. GDB will look at the target memory map when a load command is given, if any
  5556. areas to be programmed lie within the target flash area the vFlash packets
  5557. will be used.
  5558. If the target needs configuring before GDB programming, an event
  5559. script can be executed:
  5560. @example
  5561. $_TARGETNAME configure -event EVENTNAME BODY
  5562. @end example
  5563. To verify any flash programming the GDB command @option{compare-sections}
  5564. can be used.
  5565. @node Tcl Scripting API
  5566. @chapter Tcl Scripting API
  5567. @cindex Tcl Scripting API
  5568. @cindex Tcl scripts
  5569. @section API rules
  5570. The commands are stateless. E.g. the telnet command line has a concept
  5571. of currently active target, the Tcl API proc's take this sort of state
  5572. information as an argument to each proc.
  5573. There are three main types of return values: single value, name value
  5574. pair list and lists.
  5575. Name value pair. The proc 'foo' below returns a name/value pair
  5576. list.
  5577. @verbatim
  5578. > set foo(me) Duane
  5579. > set foo(you) Oyvind
  5580. > set foo(mouse) Micky
  5581. > set foo(duck) Donald
  5582. If one does this:
  5583. > set foo
  5584. The result is:
  5585. me Duane you Oyvind mouse Micky duck Donald
  5586. Thus, to get the names of the associative array is easy:
  5587. foreach { name value } [set foo] {
  5588. puts "Name: $name, Value: $value"
  5589. }
  5590. @end verbatim
  5591. Lists returned must be relatively small. Otherwise a range
  5592. should be passed in to the proc in question.
  5593. @section Internal low-level Commands
  5594. By low-level, the intent is a human would not directly use these commands.
  5595. Low-level commands are (should be) prefixed with "ocd_", e.g.
  5596. @command{ocd_flash_banks}
  5597. is the low level API upon which @command{flash banks} is implemented.
  5598. @itemize @bullet
  5599. @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  5600. Read memory and return as a Tcl array for script processing
  5601. @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  5602. Convert a Tcl array to memory locations and write the values
  5603. @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
  5604. Return information about the flash banks
  5605. @end itemize
  5606. OpenOCD commands can consist of two words, e.g. "flash banks". The
  5607. @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
  5608. called "flash_banks".
  5609. @section OpenOCD specific Global Variables
  5610. Real Tcl has ::tcl_platform(), and platform::identify, and many other
  5611. variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
  5612. holds one of the following values:
  5613. @itemize @bullet
  5614. @item @b{winxx} Built using Microsoft Visual Studio
  5615. @item @b{linux} Linux is the underlying operating sytem
  5616. @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
  5617. @item @b{cygwin} Running under Cygwin
  5618. @item @b{mingw32} Running under MingW32
  5619. @item @b{other} Unknown, none of the above.
  5620. @end itemize
  5621. Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
  5622. @quotation Note
  5623. We should add support for a variable like Tcl variable
  5624. @code{tcl_platform(platform)}, it should be called
  5625. @code{jim_platform} (because it
  5626. is jim, not real tcl).
  5627. @end quotation
  5628. @node FAQ
  5629. @chapter FAQ
  5630. @cindex faq
  5631. @enumerate
  5632. @anchor{FAQ RTCK}
  5633. @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
  5634. @cindex RTCK
  5635. @cindex adaptive clocking
  5636. @*
  5637. In digital circuit design it is often refered to as ``clock
  5638. synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
  5639. operating at some speed, your target is operating at another. The two
  5640. clocks are not synchronised, they are ``asynchronous''
  5641. In order for the two to work together they must be synchronised. Otherwise
  5642. the two systems will get out of sync with each other and nothing will
  5643. work. There are 2 basic options:
  5644. @enumerate
  5645. @item
  5646. Use a special circuit.
  5647. @item
  5648. One clock must be some multiple slower than the other.
  5649. @end enumerate
  5650. @b{Does this really matter?} For some chips and some situations, this
  5651. is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
  5652. Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
  5653. program/enable the oscillators and eventually the main clock. It is in
  5654. those critical times you must slow the JTAG clock to sometimes 1 to
  5655. 4kHz.
  5656. Imagine debugging a 500MHz ARM926 hand held battery powered device
  5657. that ``deep sleeps'' at 32kHz between every keystroke. It can be
  5658. painful.
  5659. @b{Solution #1 - A special circuit}
  5660. In order to make use of this, your JTAG dongle must support the RTCK
  5661. feature. Not all dongles support this - keep reading!
  5662. The RTCK signal often found in some ARM chips is used to help with
  5663. this problem. ARM has a good description of the problem described at
  5664. this link: @url{} [checked
  5665. 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
  5666. work? / how does adaptive clocking work?''.
  5667. The nice thing about adaptive clocking is that ``battery powered hand
  5668. held device example'' - the adaptiveness works perfectly all the
  5669. time. One can set a break point or halt the system in the deep power
  5670. down code, slow step out until the system speeds up.
  5671. Note that adaptive clocking may also need to work at the board level,
  5672. when a board-level scan chain has multiple chips.
  5673. Parallel clock voting schemes are good way to implement this,
  5674. both within and between chips, and can easily be implemented
  5675. with a CPLD.
  5676. It's not difficult to have logic fan a module's input TCK signal out
  5677. to each TAP in the scan chain, and then wait until each TAP's RTCK comes
  5678. back with the right polarity before changing the output RTCK signal.
  5679. Texas Instruments makes some clock voting logic available
  5680. for free (with no support) in VHDL form; see
  5681. @url{}
  5682. @b{Solution #2 - Always works - but may be slower}
  5683. Often this is a perfectly acceptable solution.
  5684. In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
  5685. the target clock speed. But what that ``magic division'' is varies
  5686. depending on the chips on your board.
  5687. @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
  5688. ARM11 cores use an 8:1 division.
  5689. @b{Xilinx rule of thumb} is 1/12 the clock speed.
  5690. Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
  5691. You can still debug the 'low power' situations - you just need to
  5692. manually adjust the clock speed at every step. While painful and
  5693. tedious, it is not always practical.
  5694. It is however easy to ``code your way around it'' - i.e.: Cheat a little,
  5695. have a special debug mode in your application that does a ``high power
  5696. sleep''. If you are careful - 98% of your problems can be debugged
  5697. this way.
  5698. Note that on ARM you may need to avoid using the @emph{wait for interrupt}
  5699. operation in your idle loops even if you don't otherwise change the CPU
  5700. clock rate.
  5701. That operation gates the CPU clock, and thus the JTAG clock; which
  5702. prevents JTAG access. One consequence is not being able to @command{halt}
  5703. cores which are executing that @emph{wait for interrupt} operation.
  5704. To set the JTAG frequency use the command:
  5705. @example
  5706. # Example: 1.234MHz
  5707. jtag_khz 1234
  5708. @end example
  5709. @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
  5710. OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
  5711. around Windows filenames.
  5712. @example
  5713. > echo \a
  5714. > echo @{\a@}
  5715. \a
  5716. > echo "\a"
  5717. >
  5718. @end example
  5719. @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
  5720. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  5721. claims to come with all the necessary DLLs. When using Cygwin, try launching
  5722. OpenOCD from the Cygwin shell.
  5723. @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  5724. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  5725. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  5726. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  5727. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
  5728. software breakpoints consume one of the two available hardware breakpoints.
  5729. @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
  5730. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  5731. clock at the time you're programming the flash. If you've specified the crystal's
  5732. frequency, make sure the PLL is disabled. If you've specified the full core speed
  5733. (e.g. 60MHz), make sure the PLL is enabled.
  5734. @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  5735. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  5736. out while waiting for end of scan, rtck was disabled".
  5737. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  5738. settings in your PC BIOS (ECP, EPP, and different versions of those).
  5739. @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  5740. I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
  5741. memory read caused data abort".
  5742. The errors are non-fatal, and are the result of GDB trying to trace stack frames
  5743. beyond the last valid frame. It might be possible to prevent this by setting up
  5744. a proper "initial" stack frame, if you happen to know what exactly has to
  5745. be done, feel free to add this here.
  5746. @b{Simple:} In your startup code - push 8 registers of zeros onto the
  5747. stack before calling main(). What GDB is doing is ``climbing'' the run
  5748. time stack by reading various values on the stack using the standard
  5749. call frame for the target. GDB keeps going - until one of 2 things
  5750. happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
  5751. stackframes have been processed. By pushing zeros on the stack, GDB
  5752. gracefully stops.
  5753. @b{Debugging Interrupt Service Routines} - In your ISR before you call
  5754. your C code, do the same - artifically push some zeros onto the stack,
  5755. remember to pop them off when the ISR is done.
  5756. @b{Also note:} If you have a multi-threaded operating system, they
  5757. often do not @b{in the intrest of saving memory} waste these few
  5758. bytes. Painful...
  5759. @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
  5760. "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
  5761. This warning doesn't indicate any serious problem, as long as you don't want to
  5762. debug your core right out of reset. Your .cfg file specified @option{jtag_reset
  5763. trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
  5764. your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
  5765. independently. With this setup, it's not possible to halt the core right out of
  5766. reset, everything else should work fine.
  5767. @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
  5768. toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
  5769. unstable. When single-stepping over large blocks of code, GDB and OpenOCD
  5770. quit with an error message. Is there a stability issue with OpenOCD?
  5771. No, this is not a stability issue concerning OpenOCD. Most users have solved
  5772. this issue by simply using a self-powered USB hub, which they connect their
  5773. Amontec JTAGkey to. Apparently, some computers do not provide a USB power
  5774. supply stable enough for the Amontec JTAGkey to be operated.
  5775. @b{Laptops running on battery have this problem too...}
  5776. @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
  5777. following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
  5778. 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
  5779. What does that mean and what might be the reason for this?
  5780. First of all, the reason might be the USB power supply. Try using a self-powered
  5781. hub instead of a direct connection to your computer. Secondly, the error code 4
  5782. corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
  5783. chip ran into some sort of error - this points us to a USB problem.
  5784. @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
  5785. error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
  5786. What does that mean and what might be the reason for this?
  5787. Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
  5788. has closed the connection to OpenOCD. This might be a GDB issue.
  5789. @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
  5790. are described, there is a parameter for specifying the clock frequency
  5791. for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
  5792. 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
  5793. specified in kilohertz. However, I do have a quartz crystal of a
  5794. frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
  5795. i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
  5796. clock frequency?
  5797. No. The clock frequency specified here must be given as an integral number.
  5798. However, this clock frequency is used by the In-Application-Programming (IAP)
  5799. routines of the LPC2000 family only, which seems to be very tolerant concerning
  5800. the given clock frequency, so a slight difference between the specified clock
  5801. frequency and the actual clock frequency will not cause any trouble.
  5802. @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
  5803. Well, yes and no. Commands can be given in arbitrary order, yet the
  5804. devices listed for the JTAG scan chain must be given in the right
  5805. order (jtag newdevice), with the device closest to the TDO-Pin being
  5806. listed first. In general, whenever objects of the same type exist
  5807. which require an index number, then these objects must be given in the
  5808. right order (jtag newtap, targets and flash banks - a target
  5809. references a jtag newtap and a flash bank references a target).
  5810. You can use the ``scan_chain'' command to verify and display the tap order.
  5811. Also, some commands can't execute until after @command{init} has been
  5812. processed. Such commands include @command{nand probe} and everything
  5813. else that needs to write to controller registers, perhaps for setting
  5814. up DRAM and loading it with code.
  5815. @anchor{FAQ TAP Order}
  5816. @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
  5817. particular order?
  5818. Yes; whenever you have more than one, you must declare them in
  5819. the same order used by the hardware.
  5820. Many newer devices have multiple JTAG TAPs. For example: ST
  5821. Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
  5822. ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
  5823. RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
  5824. connected to the boundary scan TAP, which then connects to the
  5825. Cortex-M3 TAP, which then connects to the TDO pin.
  5826. Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
  5827. (2) The boundary scan TAP. If your board includes an additional JTAG
  5828. chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
  5829. place it before or after the STM32 chip in the chain. For example:
  5830. @itemize @bullet
  5831. @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
  5832. @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
  5833. @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
  5834. @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
  5835. @item Xilinx TDO Pin -> OpenOCD TDO (input)
  5836. @end itemize
  5837. The ``jtag device'' commands would thus be in the order shown below. Note:
  5838. @itemize @bullet
  5839. @item jtag newtap Xilinx tap -irlen ...
  5840. @item jtag newtap stm32 cpu -irlen ...
  5841. @item jtag newtap stm32 bs -irlen ...
  5842. @item # Create the debug target and say where it is
  5843. @item target create stm32.cpu -chain-position stm32.cpu ...
  5844. @end itemize
  5845. @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
  5846. log file, I can see these error messages: Error: arm7_9_common.c:561
  5847. arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
  5848. TODO.
  5849. @end enumerate
  5850. @node Tcl Crash Course
  5851. @chapter Tcl Crash Course
  5852. @cindex Tcl
  5853. Not everyone knows Tcl - this is not intended to be a replacement for
  5854. learning Tcl, the intent of this chapter is to give you some idea of
  5855. how the Tcl scripts work.
  5856. This chapter is written with two audiences in mind. (1) OpenOCD users
  5857. who need to understand a bit more of how JIM-Tcl works so they can do
  5858. something useful, and (2) those that want to add a new command to
  5859. OpenOCD.
  5860. @section Tcl Rule #1
  5861. There is a famous joke, it goes like this:
  5862. @enumerate
  5863. @item Rule #1: The wife is always correct
  5864. @item Rule #2: If you think otherwise, See Rule #1
  5865. @end enumerate
  5866. The Tcl equal is this:
  5867. @enumerate
  5868. @item Rule #1: Everything is a string
  5869. @item Rule #2: If you think otherwise, See Rule #1
  5870. @end enumerate
  5871. As in the famous joke, the consequences of Rule #1 are profound. Once
  5872. you understand Rule #1, you will understand Tcl.
  5873. @section Tcl Rule #1b
  5874. There is a second pair of rules.
  5875. @enumerate
  5876. @item Rule #1: Control flow does not exist. Only commands
  5877. @* For example: the classic FOR loop or IF statement is not a control
  5878. flow item, they are commands, there is no such thing as control flow
  5879. in Tcl.
  5880. @item Rule #2: If you think otherwise, See Rule #1
  5881. @* Actually what happens is this: There are commands that by
  5882. convention, act like control flow key words in other languages. One of
  5883. those commands is the word ``for'', another command is ``if''.
  5884. @end enumerate
  5885. @section Per Rule #1 - All Results are strings
  5886. Every Tcl command results in a string. The word ``result'' is used
  5887. deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
  5888. Everything is a string}
  5889. @section Tcl Quoting Operators
  5890. In life of a Tcl script, there are two important periods of time, the
  5891. difference is subtle.
  5892. @enumerate
  5893. @item Parse Time
  5894. @item Evaluation Time
  5895. @end enumerate
  5896. The two key items here are how ``quoted things'' work in Tcl. Tcl has
  5897. three primary quoting constructs, the [square-brackets] the
  5898. @{curly-braces@} and ``double-quotes''
  5899. By now you should know $VARIABLES always start with a $DOLLAR
  5900. sign. BTW: To set a variable, you actually use the command ``set'', as
  5901. in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
  5902. = 1'' statement, but without the equal sign.
  5903. @itemize @bullet
  5904. @item @b{[square-brackets]}
  5905. @* @b{[square-brackets]} are command substitutions. It operates much
  5906. like Unix Shell `back-ticks`. The result of a [square-bracket]
  5907. operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
  5908. string}. These two statements are roughly identical:
  5909. @example
  5910. # bash example
  5911. X=`date`
  5912. echo "The Date is: $X"
  5913. # Tcl example
  5914. set X [date]
  5915. puts "The Date is: $X"
  5916. @end example
  5917. @item @b{``double-quoted-things''}
  5918. @* @b{``double-quoted-things''} are just simply quoted
  5919. text. $VARIABLES and [square-brackets] are expanded in place - the
  5920. result however is exactly 1 string. @i{Remember Rule #1 - Everything
  5921. is a string}
  5922. @example
  5923. set x "Dinner"
  5924. puts "It is now \"[date]\", $x is in 1 hour"
  5925. @end example
  5926. @item @b{@{Curly-Braces@}}
  5927. @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
  5928. parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
  5929. 'single-quote' operators in BASH shell scripts, with the added
  5930. feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
  5931. nested 3 times@}@}@} NOTE: [date] is a bad example;
  5932. at this writing, Jim/OpenOCD does not have a date command.
  5933. @end itemize
  5934. @section Consequences of Rule 1/2/3/4
  5935. The consequences of Rule 1 are profound.
  5936. @subsection Tokenisation & Execution.
  5937. Of course, whitespace, blank lines and #comment lines are handled in
  5938. the normal way.
  5939. As a script is parsed, each (multi) line in the script file is
  5940. tokenised and according to the quoting rules. After tokenisation, that
  5941. line is immedatly executed.
  5942. Multi line statements end with one or more ``still-open''
  5943. @{curly-braces@} which - eventually - closes a few lines later.
  5944. @subsection Command Execution
  5945. Remember earlier: There are no ``control flow''
  5946. statements in Tcl. Instead there are COMMANDS that simply act like
  5947. control flow operators.
  5948. Commands are executed like this:
  5949. @enumerate
  5950. @item Parse the next line into (argc) and (argv[]).
  5951. @item Look up (argv[0]) in a table and call its function.
  5952. @item Repeat until End Of File.
  5953. @end enumerate
  5954. It sort of works like this:
  5955. @example
  5956. for(;;)@{
  5957. ReadAndParse( &argc, &argv );
  5958. cmdPtr = LookupCommand( argv[0] );
  5959. (*cmdPtr->Execute)( argc, argv );
  5960. @}
  5961. @end example
  5962. When the command ``proc'' is parsed (which creates a procedure
  5963. function) it gets 3 parameters on the command line. @b{1} the name of
  5964. the proc (function), @b{2} the list of parameters, and @b{3} the body
  5965. of the function. Not the choice of words: LIST and BODY. The PROC
  5966. command stores these items in a table somewhere so it can be found by
  5967. ``LookupCommand()''
  5968. @subsection The FOR command
  5969. The most interesting command to look at is the FOR command. In Tcl,
  5970. the FOR command is normally implemented in C. Remember, FOR is a
  5971. command just like any other command.
  5972. When the ascii text containing the FOR command is parsed, the parser
  5973. produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
  5974. are:
  5975. @enumerate 0
  5976. @item The ascii text 'for'
  5977. @item The start text
  5978. @item The test expression
  5979. @item The next text
  5980. @item The body text
  5981. @end enumerate
  5982. Sort of reminds you of ``main( int argc, char **argv )'' does it not?
  5983. Remember @i{Rule #1 - Everything is a string.} The key point is this:
  5984. Often many of those parameters are in @{curly-braces@} - thus the
  5985. variables inside are not expanded or replaced until later.
  5986. Remember that every Tcl command looks like the classic ``main( argc,
  5987. argv )'' function in C. In JimTCL - they actually look like this:
  5988. @example
  5989. int
  5990. MyCommand( Jim_Interp *interp,
  5991. int *argc,
  5992. Jim_Obj * const *argvs );
  5993. @end example
  5994. Real Tcl is nearly identical. Although the newer versions have
  5995. introduced a byte-code parser and intepreter, but at the core, it
  5996. still operates in the same basic way.
  5997. @subsection FOR command implementation
  5998. To understand Tcl it is perhaps most helpful to see the FOR
  5999. command. Remember, it is a COMMAND not a control flow structure.
  6000. In Tcl there are two underlying C helper functions.
  6001. Remember Rule #1 - You are a string.
  6002. The @b{first} helper parses and executes commands found in an ascii
  6003. string. Commands can be seperated by semicolons, or newlines. While
  6004. parsing, variables are expanded via the quoting rules.
  6005. The @b{second} helper evaluates an ascii string as a numerical
  6006. expression and returns a value.
  6007. Here is an example of how the @b{FOR} command could be
  6008. implemented. The pseudo code below does not show error handling.
  6009. @example
  6010. void Execute_AsciiString( void *interp, const char *string );
  6011. int Evaluate_AsciiExpression( void *interp, const char *string );
  6012. int
  6013. MyForCommand( void *interp,
  6014. int argc,
  6015. char **argv )
  6016. @{
  6017. if( argc != 5 )@{
  6018. SetResult( interp, "WRONG number of parameters");
  6019. return ERROR;
  6020. @}
  6021. // argv[0] = the ascii string just like C
  6022. // Execute the start statement.
  6023. Execute_AsciiString( interp, argv[1] );
  6024. // Top of loop test
  6025. for(;;)@{
  6026. i = Evaluate_AsciiExpression(interp, argv[2]);
  6027. if( i == 0 )
  6028. break;
  6029. // Execute the body
  6030. Execute_AsciiString( interp, argv[3] );
  6031. // Execute the LOOP part
  6032. Execute_AsciiString( interp, argv[4] );
  6033. @}
  6034. // Return no error
  6035. SetResult( interp, "" );
  6036. return SUCCESS;
  6037. @}
  6038. @end example
  6039. Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
  6040. in the same basic way.
  6041. @section OpenOCD Tcl Usage
  6042. @subsection source and find commands
  6043. @b{Where:} In many configuration files
  6044. @* Example: @b{ source [find FILENAME] }
  6045. @*Remember the parsing rules
  6046. @enumerate
  6047. @item The FIND command is in square brackets.
  6048. @* The FIND command is executed with the parameter FILENAME. It should
  6049. find the full path to the named file. The RESULT is a string, which is
  6050. substituted on the orginal command line.
  6051. @item The command source is executed with the resulting filename.
  6052. @* SOURCE reads a file and executes as a script.
  6053. @end enumerate
  6054. @subsection format command
  6055. @b{Where:} Generally occurs in numerous places.
  6056. @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
  6057. @b{sprintf()}.
  6058. @b{Example}
  6059. @example
  6060. set x 6
  6061. set y 7
  6062. puts [format "The answer: %d" [expr $x * $y]]
  6063. @end example
  6064. @enumerate
  6065. @item The SET command creates 2 variables, X and Y.
  6066. @item The double [nested] EXPR command performs math
  6067. @* The EXPR command produces numerical result as a string.
  6068. @* Refer to Rule #1
  6069. @item The format command is executed, producing a single string
  6070. @* Refer to Rule #1.
  6071. @item The PUTS command outputs the text.
  6072. @end enumerate
  6073. @subsection Body or Inlined Text
  6074. @b{Where:} Various TARGET scripts.
  6075. @example
  6076. #1 Good
  6077. proc someproc @{@} @{
  6078. ... multiple lines of stuff ...
  6079. @}
  6080. $_TARGETNAME configure -event FOO someproc
  6081. #2 Good - no variables
  6082. $_TARGETNAME confgure -event foo "this ; that;"
  6083. #3 Good Curly Braces
  6084. $_TARGETNAME configure -event FOO @{
  6085. puts "Time: [date]"
  6086. @}
  6088. $_TARGETNAME configure -event foo "puts \"Time: [date]\""
  6089. @end example
  6090. @enumerate
  6091. @item The $_TARGETNAME is an OpenOCD variable convention.
  6092. @*@b{$_TARGETNAME} represents the last target created, the value changes
  6093. each time a new target is created. Remember the parsing rules. When
  6094. the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
  6095. the name of the target which happens to be a TARGET (object)
  6096. command.
  6097. @item The 2nd parameter to the @option{-event} parameter is a TCBODY
  6098. @*There are 4 examples:
  6099. @enumerate
  6100. @item The TCLBODY is a simple string that happens to be a proc name
  6101. @item The TCLBODY is several simple commands seperated by semicolons
  6102. @item The TCLBODY is a multi-line @{curly-brace@} quoted string
  6103. @item The TCLBODY is a string with variables that get expanded.
  6104. @end enumerate
  6105. In the end, when the target event FOO occurs the TCLBODY is
  6106. evaluated. Method @b{#1} and @b{#2} are functionally identical. For
  6107. Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
  6108. Remember the parsing rules. In case #3, @{curly-braces@} mean the
  6109. $VARS and [square-brackets] are expanded later, when the EVENT occurs,
  6110. and the text is evaluated. In case #4, they are replaced before the
  6111. ``Target Object Command'' is executed. This occurs at the same time
  6112. $_TARGETNAME is replaced. In case #4 the date will never
  6113. change. @{BTW: [date] is a bad example; at this writing,
  6114. Jim/OpenOCD does not have a date command@}
  6115. @end enumerate
  6116. @subsection Global Variables
  6117. @b{Where:} You might discover this when writing your own procs @* In
  6118. simple terms: Inside a PROC, if you need to access a global variable
  6119. you must say so. See also ``upvar''. Example:
  6120. @example
  6121. proc myproc @{ @} @{
  6122. set y 0 #Local variable Y
  6123. global x #Global variable X
  6124. puts [format "X=%d, Y=%d" $x $y]
  6125. @}
  6126. @end example
  6127. @section Other Tcl Hacks
  6128. @b{Dynamic variable creation}
  6129. @example
  6130. # Dynamically create a bunch of variables.
  6131. for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
  6132. # Create var name
  6133. set vn [format "BIT%d" $x]
  6134. # Make it a global
  6135. global $vn
  6136. # Set it.
  6137. set $vn [expr (1 << $x)]
  6138. @}
  6139. @end example
  6140. @b{Dynamic proc/command creation}
  6141. @example
  6142. # One "X" function - 5 uart functions.
  6143. foreach who @{A B C D E@}
  6144. proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
  6145. @}
  6146. @end example
  6147. @include fdl.texi
  6148. @node OpenOCD Concept Index
  6149. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  6150. @comment case issue with ``Index.html'' and ``index.html''
  6151. @comment Occurs when creating ``--html --no-split'' output
  6152. @comment This fix is based on:
  6153. @unnumbered OpenOCD Concept Index
  6154. @printindex cp
  6155. @node Command and Driver Index
  6156. @unnumbered Command and Driver Index
  6157. @printindex fn
  6158. @bye