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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "breakpoints.h"
  28. #include "mips32.h"
  29. #include "mips_m4k.h"
  30. #include "mips32_dmaacc.h"
  31. #include "target_type.h"
  32. #include "register.h"
  33. static void mips_m4k_enable_breakpoints(struct target *target);
  34. static void mips_m4k_enable_watchpoints(struct target *target);
  35. static int mips_m4k_set_breakpoint(struct target *target,
  36. struct breakpoint *breakpoint);
  37. static int mips_m4k_unset_breakpoint(struct target *target,
  38. struct breakpoint *breakpoint);
  39. static int mips_m4k_examine_debug_reason(struct target *target)
  40. {
  41. uint32_t break_status;
  42. int retval;
  43. if ((target->debug_reason != DBG_REASON_DBGRQ)
  44. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  45. {
  46. /* get info about inst breakpoint support */
  47. if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
  48. return retval;
  49. if (break_status & 0x1f)
  50. {
  51. /* we have halted on a breakpoint */
  52. if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
  53. return retval;
  54. target->debug_reason = DBG_REASON_BREAKPOINT;
  55. }
  56. /* get info about data breakpoint support */
  57. if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
  58. return retval;
  59. if (break_status & 0x1f)
  60. {
  61. /* we have halted on a breakpoint */
  62. if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
  63. return retval;
  64. target->debug_reason = DBG_REASON_WATCHPOINT;
  65. }
  66. }
  67. return ERROR_OK;
  68. }
  69. static int mips_m4k_debug_entry(struct target *target)
  70. {
  71. struct mips32_common *mips32 = target_to_mips32(target);
  72. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  73. uint32_t debug_reg;
  74. /* read debug register */
  75. mips_ejtag_read_debug(ejtag_info, &debug_reg);
  76. /* make sure break unit configured */
  77. mips32_configure_break_unit(target);
  78. /* attempt to find halt reason */
  79. mips_m4k_examine_debug_reason(target);
  80. /* clear single step if active */
  81. if (debug_reg & EJTAG_DEBUG_DSS)
  82. {
  83. /* stopped due to single step - clear step bit */
  84. mips_ejtag_config_step(ejtag_info, 0);
  85. }
  86. mips32_save_context(target);
  87. /* default to mips32 isa, it will be changed below if required */
  88. mips32->isa_mode = MIPS32_ISA_MIPS32;
  89. if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
  90. mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
  91. }
  92. LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
  93. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
  94. target_state_name(target));
  95. return ERROR_OK;
  96. }
  97. static int mips_m4k_poll(struct target *target)
  98. {
  99. int retval;
  100. struct mips32_common *mips32 = target_to_mips32(target);
  101. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  102. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
  103. /* read ejtag control reg */
  104. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  105. retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  106. if (retval != ERROR_OK)
  107. return retval;
  108. /* clear this bit before handling polling
  109. * as after reset registers will read zero */
  110. if (ejtag_ctrl & EJTAG_CTRL_ROCC)
  111. {
  112. /* we have detected a reset, clear flag
  113. * otherwise ejtag will not work */
  114. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
  115. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  116. retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  117. if (retval != ERROR_OK)
  118. return retval;
  119. LOG_DEBUG("Reset Detected");
  120. }
  121. /* check for processor halted */
  122. if (ejtag_ctrl & EJTAG_CTRL_BRKST)
  123. {
  124. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
  125. {
  126. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
  127. target->state = TARGET_HALTED;
  128. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  129. return retval;
  130. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  131. }
  132. else if (target->state == TARGET_DEBUG_RUNNING)
  133. {
  134. target->state = TARGET_HALTED;
  135. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  136. return retval;
  137. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  138. }
  139. }
  140. else
  141. {
  142. target->state = TARGET_RUNNING;
  143. }
  144. // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
  145. return ERROR_OK;
  146. }
  147. static int mips_m4k_halt(struct target *target)
  148. {
  149. struct mips32_common *mips32 = target_to_mips32(target);
  150. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  151. LOG_DEBUG("target->state: %s",
  152. target_state_name(target));
  153. if (target->state == TARGET_HALTED)
  154. {
  155. LOG_DEBUG("target was already halted");
  156. return ERROR_OK;
  157. }
  158. if (target->state == TARGET_UNKNOWN)
  159. {
  160. LOG_WARNING("target was in unknown state when halt was requested");
  161. }
  162. if (target->state == TARGET_RESET)
  163. {
  164. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  165. {
  166. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  167. return ERROR_TARGET_FAILURE;
  168. }
  169. else
  170. {
  171. /* we came here in a reset_halt or reset_init sequence
  172. * debug entry was already prepared in mips32_prepare_reset_halt()
  173. */
  174. target->debug_reason = DBG_REASON_DBGRQ;
  175. return ERROR_OK;
  176. }
  177. }
  178. /* break processor */
  179. mips_ejtag_enter_debug(ejtag_info);
  180. target->debug_reason = DBG_REASON_DBGRQ;
  181. return ERROR_OK;
  182. }
  183. static int mips_m4k_assert_reset(struct target *target)
  184. {
  185. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  186. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  187. int assert_srst = 1;
  188. LOG_DEBUG("target->state: %s",
  189. target_state_name(target));
  190. enum reset_types jtag_reset_config = jtag_get_reset_config();
  191. if (!(jtag_reset_config & RESET_HAS_SRST))
  192. assert_srst = 0;
  193. if (target->reset_halt)
  194. {
  195. /* use hardware to catch reset */
  196. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
  197. }
  198. else
  199. {
  200. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
  201. }
  202. if (assert_srst)
  203. {
  204. /* here we should issue a srst only, but we may have to assert trst as well */
  205. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  206. {
  207. jtag_add_reset(1, 1);
  208. }
  209. else
  210. {
  211. jtag_add_reset(0, 1);
  212. }
  213. }
  214. else
  215. {
  216. if (mips_m4k->is_pic32mx)
  217. {
  218. LOG_DEBUG("Using MTAP reset to reset processor...");
  219. /* use microchip specific MTAP reset */
  220. mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
  221. mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
  222. mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
  223. mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
  224. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  225. }
  226. else
  227. {
  228. /* use ejtag reset - not supported by all cores */
  229. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
  230. LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
  231. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  232. mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
  233. }
  234. }
  235. target->state = TARGET_RESET;
  236. jtag_add_sleep(50000);
  237. register_cache_invalidate(mips_m4k->mips32.core_cache);
  238. if (target->reset_halt)
  239. {
  240. int retval;
  241. if ((retval = target_halt(target)) != ERROR_OK)
  242. return retval;
  243. }
  244. return ERROR_OK;
  245. }
  246. static int mips_m4k_deassert_reset(struct target *target)
  247. {
  248. LOG_DEBUG("target->state: %s",
  249. target_state_name(target));
  250. /* deassert reset lines */
  251. jtag_add_reset(0, 0);
  252. return ERROR_OK;
  253. }
  254. static int mips_m4k_soft_reset_halt(struct target *target)
  255. {
  256. /* TODO */
  257. return ERROR_OK;
  258. }
  259. static int mips_m4k_single_step_core(struct target *target)
  260. {
  261. struct mips32_common *mips32 = target_to_mips32(target);
  262. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  263. /* configure single step mode */
  264. mips_ejtag_config_step(ejtag_info, 1);
  265. /* disable interrupts while stepping */
  266. mips32_enable_interrupts(target, 0);
  267. /* exit debug mode */
  268. mips_ejtag_exit_debug(ejtag_info);
  269. mips_m4k_debug_entry(target);
  270. return ERROR_OK;
  271. }
  272. static int mips_m4k_resume(struct target *target, int current,
  273. uint32_t address, int handle_breakpoints, int debug_execution)
  274. {
  275. struct mips32_common *mips32 = target_to_mips32(target);
  276. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  277. struct breakpoint *breakpoint = NULL;
  278. uint32_t resume_pc;
  279. if (target->state != TARGET_HALTED)
  280. {
  281. LOG_WARNING("target not halted");
  282. return ERROR_TARGET_NOT_HALTED;
  283. }
  284. if (!debug_execution)
  285. {
  286. target_free_all_working_areas(target);
  287. mips_m4k_enable_breakpoints(target);
  288. mips_m4k_enable_watchpoints(target);
  289. }
  290. /* current = 1: continue on current pc, otherwise continue at <address> */
  291. if (!current)
  292. {
  293. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  294. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  295. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  296. }
  297. if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
  298. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
  299. }
  300. resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
  301. mips32_restore_context(target);
  302. /* the front-end may request us not to handle breakpoints */
  303. if (handle_breakpoints)
  304. {
  305. /* Single step past breakpoint at current address */
  306. if ((breakpoint = breakpoint_find(target, resume_pc)))
  307. {
  308. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  309. mips_m4k_unset_breakpoint(target, breakpoint);
  310. mips_m4k_single_step_core(target);
  311. mips_m4k_set_breakpoint(target, breakpoint);
  312. }
  313. }
  314. /* enable interrupts if we are running */
  315. mips32_enable_interrupts(target, !debug_execution);
  316. /* exit debug mode */
  317. mips_ejtag_exit_debug(ejtag_info);
  318. target->debug_reason = DBG_REASON_NOTHALTED;
  319. /* registers are now invalid */
  320. register_cache_invalidate(mips32->core_cache);
  321. if (!debug_execution)
  322. {
  323. target->state = TARGET_RUNNING;
  324. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  325. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  326. }
  327. else
  328. {
  329. target->state = TARGET_DEBUG_RUNNING;
  330. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  331. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  332. }
  333. return ERROR_OK;
  334. }
  335. static int mips_m4k_step(struct target *target, int current,
  336. uint32_t address, int handle_breakpoints)
  337. {
  338. /* get pointers to arch-specific information */
  339. struct mips32_common *mips32 = target_to_mips32(target);
  340. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  341. struct breakpoint *breakpoint = NULL;
  342. if (target->state != TARGET_HALTED)
  343. {
  344. LOG_WARNING("target not halted");
  345. return ERROR_TARGET_NOT_HALTED;
  346. }
  347. /* current = 1: continue on current pc, otherwise continue at <address> */
  348. if (!current)
  349. {
  350. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  351. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  352. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  353. }
  354. /* the front-end may request us not to handle breakpoints */
  355. if (handle_breakpoints) {
  356. breakpoint = breakpoint_find(target,
  357. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
  358. if (breakpoint)
  359. mips_m4k_unset_breakpoint(target, breakpoint);
  360. }
  361. /* restore context */
  362. mips32_restore_context(target);
  363. /* configure single step mode */
  364. mips_ejtag_config_step(ejtag_info, 1);
  365. target->debug_reason = DBG_REASON_SINGLESTEP;
  366. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  367. /* disable interrupts while stepping */
  368. mips32_enable_interrupts(target, 0);
  369. /* exit debug mode */
  370. mips_ejtag_exit_debug(ejtag_info);
  371. /* registers are now invalid */
  372. register_cache_invalidate(mips32->core_cache);
  373. if (breakpoint)
  374. mips_m4k_set_breakpoint(target, breakpoint);
  375. LOG_DEBUG("target stepped ");
  376. mips_m4k_debug_entry(target);
  377. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  378. return ERROR_OK;
  379. }
  380. static void mips_m4k_enable_breakpoints(struct target *target)
  381. {
  382. struct breakpoint *breakpoint = target->breakpoints;
  383. /* set any pending breakpoints */
  384. while (breakpoint)
  385. {
  386. if (breakpoint->set == 0)
  387. mips_m4k_set_breakpoint(target, breakpoint);
  388. breakpoint = breakpoint->next;
  389. }
  390. }
  391. static int mips_m4k_set_breakpoint(struct target *target,
  392. struct breakpoint *breakpoint)
  393. {
  394. struct mips32_common *mips32 = target_to_mips32(target);
  395. struct mips32_comparator * comparator_list = mips32->inst_break_list;
  396. int retval;
  397. if (breakpoint->set)
  398. {
  399. LOG_WARNING("breakpoint already set");
  400. return ERROR_OK;
  401. }
  402. if (breakpoint->type == BKPT_HARD)
  403. {
  404. int bp_num = 0;
  405. while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
  406. bp_num++;
  407. if (bp_num >= mips32->num_inst_bpoints)
  408. {
  409. LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
  410. breakpoint->unique_id );
  411. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  412. }
  413. breakpoint->set = bp_num + 1;
  414. comparator_list[bp_num].used = 1;
  415. comparator_list[bp_num].bp_value = breakpoint->address;
  416. target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
  417. target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
  418. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
  419. LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
  420. breakpoint->unique_id,
  421. bp_num, comparator_list[bp_num].bp_value);
  422. }
  423. else if (breakpoint->type == BKPT_SOFT)
  424. {
  425. LOG_DEBUG("bpid: %d", breakpoint->unique_id );
  426. if (breakpoint->length == 4)
  427. {
  428. uint32_t verify = 0xffffffff;
  429. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
  430. breakpoint->orig_instr)) != ERROR_OK)
  431. {
  432. return retval;
  433. }
  434. if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
  435. {
  436. return retval;
  437. }
  438. if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
  439. {
  440. return retval;
  441. }
  442. if (verify != MIPS32_SDBBP)
  443. {
  444. LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  445. return ERROR_OK;
  446. }
  447. }
  448. else
  449. {
  450. uint16_t verify = 0xffff;
  451. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
  452. breakpoint->orig_instr)) != ERROR_OK)
  453. {
  454. return retval;
  455. }
  456. if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
  457. {
  458. return retval;
  459. }
  460. if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
  461. {
  462. return retval;
  463. }
  464. if (verify != MIPS16_SDBBP)
  465. {
  466. LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  467. return ERROR_OK;
  468. }
  469. }
  470. breakpoint->set = 20; /* Any nice value but 0 */
  471. }
  472. return ERROR_OK;
  473. }
  474. static int mips_m4k_unset_breakpoint(struct target *target,
  475. struct breakpoint *breakpoint)
  476. {
  477. /* get pointers to arch-specific information */
  478. struct mips32_common *mips32 = target_to_mips32(target);
  479. struct mips32_comparator *comparator_list = mips32->inst_break_list;
  480. int retval;
  481. if (!breakpoint->set)
  482. {
  483. LOG_WARNING("breakpoint not set");
  484. return ERROR_OK;
  485. }
  486. if (breakpoint->type == BKPT_HARD)
  487. {
  488. int bp_num = breakpoint->set - 1;
  489. if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
  490. {
  491. LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
  492. breakpoint->unique_id);
  493. return ERROR_OK;
  494. }
  495. LOG_DEBUG("bpid: %d - releasing hw: %d",
  496. breakpoint->unique_id,
  497. bp_num );
  498. comparator_list[bp_num].used = 0;
  499. comparator_list[bp_num].bp_value = 0;
  500. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
  501. }
  502. else
  503. {
  504. /* restore original instruction (kept in target endianness) */
  505. LOG_DEBUG("bpid: %d", breakpoint->unique_id);
  506. if (breakpoint->length == 4)
  507. {
  508. uint32_t current_instr;
  509. /* check that user program has not modified breakpoint instruction */
  510. if ((retval = target_read_memory(target, breakpoint->address, 4, 1,
  511. (uint8_t*)&current_instr)) != ERROR_OK)
  512. {
  513. return retval;
  514. }
  515. /**
  516. * target_read_memory() gets us data in _target_ endianess.
  517. * If we want to use this data on the host for comparisons with some macros
  518. * we must first transform it to _host_ endianess using target_buffer_get_u32().
  519. */
  520. current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
  521. if (current_instr == MIPS32_SDBBP)
  522. {
  523. if ((retval = target_write_memory(target, breakpoint->address, 4, 1,
  524. breakpoint->orig_instr)) != ERROR_OK)
  525. {
  526. return retval;
  527. }
  528. }
  529. }
  530. else
  531. {
  532. uint16_t current_instr;
  533. /* check that user program has not modified breakpoint instruction */
  534. if ((retval = target_read_memory(target, breakpoint->address, 2, 1,
  535. (uint8_t*)&current_instr)) != ERROR_OK)
  536. {
  537. return retval;
  538. }
  539. current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
  540. if (current_instr == MIPS16_SDBBP)
  541. {
  542. if ((retval = target_write_memory(target, breakpoint->address, 2, 1,
  543. breakpoint->orig_instr)) != ERROR_OK)
  544. {
  545. return retval;
  546. }
  547. }
  548. }
  549. }
  550. breakpoint->set = 0;
  551. return ERROR_OK;
  552. }
  553. static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  554. {
  555. struct mips32_common *mips32 = target_to_mips32(target);
  556. if (breakpoint->type == BKPT_HARD)
  557. {
  558. if (mips32->num_inst_bpoints_avail < 1)
  559. {
  560. LOG_INFO("no hardware breakpoint available");
  561. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  562. }
  563. mips32->num_inst_bpoints_avail--;
  564. }
  565. return mips_m4k_set_breakpoint(target, breakpoint);
  566. }
  567. static int mips_m4k_remove_breakpoint(struct target *target,
  568. struct breakpoint *breakpoint)
  569. {
  570. /* get pointers to arch-specific information */
  571. struct mips32_common *mips32 = target_to_mips32(target);
  572. if (target->state != TARGET_HALTED)
  573. {
  574. LOG_WARNING("target not halted");
  575. return ERROR_TARGET_NOT_HALTED;
  576. }
  577. if (breakpoint->set)
  578. {
  579. mips_m4k_unset_breakpoint(target, breakpoint);
  580. }
  581. if (breakpoint->type == BKPT_HARD)
  582. mips32->num_inst_bpoints_avail++;
  583. return ERROR_OK;
  584. }
  585. static int mips_m4k_set_watchpoint(struct target *target,
  586. struct watchpoint *watchpoint)
  587. {
  588. struct mips32_common *mips32 = target_to_mips32(target);
  589. struct mips32_comparator *comparator_list = mips32->data_break_list;
  590. int wp_num = 0;
  591. /*
  592. * watchpoint enabled, ignore all byte lanes in value register
  593. * and exclude both load and store accesses from watchpoint
  594. * condition evaluation
  595. */
  596. int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
  597. (0xff << EJTAG_DBCn_BLM_SHIFT);
  598. if (watchpoint->set)
  599. {
  600. LOG_WARNING("watchpoint already set");
  601. return ERROR_OK;
  602. }
  603. while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
  604. wp_num++;
  605. if (wp_num >= mips32->num_data_bpoints)
  606. {
  607. LOG_ERROR("Can not find free FP Comparator");
  608. return ERROR_FAIL;
  609. }
  610. if (watchpoint->length != 4)
  611. {
  612. LOG_ERROR("Only watchpoints of length 4 are supported");
  613. return ERROR_TARGET_UNALIGNED_ACCESS;
  614. }
  615. if (watchpoint->address % 4)
  616. {
  617. LOG_ERROR("Watchpoints address should be word aligned");
  618. return ERROR_TARGET_UNALIGNED_ACCESS;
  619. }
  620. switch (watchpoint->rw)
  621. {
  622. case WPT_READ:
  623. enable &= ~EJTAG_DBCn_NOLB;
  624. break;
  625. case WPT_WRITE:
  626. enable &= ~EJTAG_DBCn_NOSB;
  627. break;
  628. case WPT_ACCESS:
  629. enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
  630. break;
  631. default:
  632. LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
  633. }
  634. watchpoint->set = wp_num + 1;
  635. comparator_list[wp_num].used = 1;
  636. comparator_list[wp_num].bp_value = watchpoint->address;
  637. target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
  638. target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
  639. target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
  640. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
  641. target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
  642. LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
  643. return ERROR_OK;
  644. }
  645. static int mips_m4k_unset_watchpoint(struct target *target,
  646. struct watchpoint *watchpoint)
  647. {
  648. /* get pointers to arch-specific information */
  649. struct mips32_common *mips32 = target_to_mips32(target);
  650. struct mips32_comparator *comparator_list = mips32->data_break_list;
  651. if (!watchpoint->set)
  652. {
  653. LOG_WARNING("watchpoint not set");
  654. return ERROR_OK;
  655. }
  656. int wp_num = watchpoint->set - 1;
  657. if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
  658. {
  659. LOG_DEBUG("Invalid FP Comparator number in watchpoint");
  660. return ERROR_OK;
  661. }
  662. comparator_list[wp_num].used = 0;
  663. comparator_list[wp_num].bp_value = 0;
  664. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
  665. watchpoint->set = 0;
  666. return ERROR_OK;
  667. }
  668. static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  669. {
  670. struct mips32_common *mips32 = target_to_mips32(target);
  671. if (mips32->num_data_bpoints_avail < 1)
  672. {
  673. LOG_INFO("no hardware watchpoints available");
  674. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  675. }
  676. mips32->num_data_bpoints_avail--;
  677. mips_m4k_set_watchpoint(target, watchpoint);
  678. return ERROR_OK;
  679. }
  680. static int mips_m4k_remove_watchpoint(struct target *target,
  681. struct watchpoint *watchpoint)
  682. {
  683. /* get pointers to arch-specific information */
  684. struct mips32_common *mips32 = target_to_mips32(target);
  685. if (target->state != TARGET_HALTED)
  686. {
  687. LOG_WARNING("target not halted");
  688. return ERROR_TARGET_NOT_HALTED;
  689. }
  690. if (watchpoint->set)
  691. {
  692. mips_m4k_unset_watchpoint(target, watchpoint);
  693. }
  694. mips32->num_data_bpoints_avail++;
  695. return ERROR_OK;
  696. }
  697. static void mips_m4k_enable_watchpoints(struct target *target)
  698. {
  699. struct watchpoint *watchpoint = target->watchpoints;
  700. /* set any pending watchpoints */
  701. while (watchpoint)
  702. {
  703. if (watchpoint->set == 0)
  704. mips_m4k_set_watchpoint(target, watchpoint);
  705. watchpoint = watchpoint->next;
  706. }
  707. }
  708. static int mips_m4k_read_memory(struct target *target, uint32_t address,
  709. uint32_t size, uint32_t count, uint8_t *buffer)
  710. {
  711. struct mips32_common *mips32 = target_to_mips32(target);
  712. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  713. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
  714. if (target->state != TARGET_HALTED)
  715. {
  716. LOG_WARNING("target not halted");
  717. return ERROR_TARGET_NOT_HALTED;
  718. }
  719. /* sanitize arguments */
  720. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  721. return ERROR_INVALID_ARGUMENTS;
  722. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  723. return ERROR_TARGET_UNALIGNED_ACCESS;
  724. /* if noDMA off, use DMAACC mode for memory read */
  725. int retval;
  726. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  727. retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  728. else
  729. retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  730. if (ERROR_OK != retval)
  731. return retval;
  732. /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
  733. /* endianness, but byte array should represent target endianness */
  734. uint32_t i, t32;
  735. uint16_t t16;
  736. for(i = 0; i < (count*size); i += size)
  737. {
  738. switch(size)
  739. {
  740. case 4:
  741. t32 = le_to_h_u32(&buffer[i]);
  742. target_buffer_set_u32(target,&buffer[i], t32);
  743. break;
  744. case 2:
  745. t16 = le_to_h_u16(&buffer[i]);
  746. target_buffer_set_u16(target,&buffer[i], t16);
  747. break;
  748. }
  749. }
  750. return ERROR_OK;
  751. }
  752. static int mips_m4k_write_memory(struct target *target, uint32_t address,
  753. uint32_t size, uint32_t count, const uint8_t *buffer)
  754. {
  755. struct mips32_common *mips32 = target_to_mips32(target);
  756. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  757. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
  758. address, size, count);
  759. if (target->state != TARGET_HALTED)
  760. {
  761. LOG_WARNING("target not halted");
  762. return ERROR_TARGET_NOT_HALTED;
  763. }
  764. /* sanitize arguments */
  765. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  766. return ERROR_INVALID_ARGUMENTS;
  767. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  768. return ERROR_TARGET_UNALIGNED_ACCESS;
  769. /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
  770. /* endianness, but byte array represents target endianness */
  771. uint8_t * t = NULL;
  772. t = malloc(count * sizeof(uint32_t));
  773. if (t == NULL)
  774. {
  775. LOG_ERROR("Out of memory");
  776. return ERROR_FAIL;
  777. }
  778. uint32_t i, t32;
  779. uint16_t t16;
  780. for(i = 0; i < (count*size); i += size)
  781. {
  782. switch(size)
  783. {
  784. case 4:
  785. t32 = target_buffer_get_u32(target,&buffer[i]);
  786. h_u32_to_le(&t[i], t32);
  787. break;
  788. case 2:
  789. t16 = target_buffer_get_u16(target,&buffer[i]);
  790. h_u16_to_le(&t[i], t16);
  791. break;
  792. }
  793. }
  794. buffer = t;
  795. /* if noDMA off, use DMAACC mode for memory write */
  796. int retval;
  797. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  798. retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  799. else
  800. retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  801. if (t != NULL)
  802. free(t);
  803. if (ERROR_OK != retval)
  804. return retval;
  805. return ERROR_OK;
  806. }
  807. static int mips_m4k_init_target(struct command_context *cmd_ctx,
  808. struct target *target)
  809. {
  810. mips32_build_reg_cache(target);
  811. return ERROR_OK;
  812. }
  813. static int mips_m4k_init_arch_info(struct target *target,
  814. struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
  815. {
  816. struct mips32_common *mips32 = &mips_m4k->mips32;
  817. mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
  818. /* initialize mips4k specific info */
  819. mips32_init_arch_info(target, mips32, tap);
  820. mips32->arch_info = mips_m4k;
  821. return ERROR_OK;
  822. }
  823. static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
  824. {
  825. struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
  826. mips_m4k_init_arch_info(target, mips_m4k, target->tap);
  827. return ERROR_OK;
  828. }
  829. static int mips_m4k_examine(struct target *target)
  830. {
  831. int retval;
  832. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  833. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  834. uint32_t idcode = 0;
  835. if (!target_was_examined(target))
  836. {
  837. retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
  838. if (retval != ERROR_OK)
  839. return retval;
  840. ejtag_info->idcode = idcode;
  841. if (((idcode >> 1) & 0x7FF) == 0x29)
  842. {
  843. /* we are using a pic32mx so select ejtag port
  844. * as it is not selected by default */
  845. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  846. LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
  847. mips_m4k->is_pic32mx = true;
  848. }
  849. }
  850. /* init rest of ejtag interface */
  851. if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
  852. return retval;
  853. if ((retval = mips32_examine(target)) != ERROR_OK)
  854. return retval;
  855. return ERROR_OK;
  856. }
  857. static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  858. uint32_t count, const uint8_t *buffer)
  859. {
  860. struct mips32_common *mips32 = target_to_mips32(target);
  861. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  862. int retval;
  863. int write_t = 1;
  864. LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
  865. if (target->state != TARGET_HALTED)
  866. {
  867. LOG_WARNING("target not halted");
  868. return ERROR_TARGET_NOT_HALTED;
  869. }
  870. /* check alignment */
  871. if (address & 0x3u)
  872. return ERROR_TARGET_UNALIGNED_ACCESS;
  873. if (mips32->fast_data_area == NULL)
  874. {
  875. /* Get memory for block write handler
  876. * we preserve this area between calls and gain a speed increase
  877. * of about 3kb/sec when writing flash
  878. * this will be released/nulled by the system when the target is resumed or reset */
  879. retval = target_alloc_working_area(target,
  880. MIPS32_FASTDATA_HANDLER_SIZE,
  881. &mips32->fast_data_area);
  882. if (retval != ERROR_OK)
  883. {
  884. LOG_WARNING("No working area available, falling back to non-bulk write");
  885. return mips_m4k_write_memory(target, address, 4, count, buffer);
  886. }
  887. /* reset fastadata state so the algo get reloaded */
  888. ejtag_info->fast_access_save = -1;
  889. }
  890. /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
  891. /* but byte array represents target endianness */
  892. uint8_t * t = NULL;
  893. t = malloc(count * sizeof(uint32_t));
  894. if (t == NULL)
  895. {
  896. LOG_ERROR("Out of memory");
  897. return ERROR_FAIL;
  898. }
  899. uint32_t i, t32;
  900. for(i = 0; i < (count*4); i += 4)
  901. {
  902. t32 = target_buffer_get_u32(target,&buffer[i]);
  903. h_u32_to_le(&t[i], t32);
  904. }
  905. retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
  906. count, (uint32_t*) (void *)t);
  907. if (t != NULL)
  908. free(t);
  909. if (retval != ERROR_OK)
  910. {
  911. /* FASTDATA access failed, try normal memory write */
  912. LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
  913. retval = mips_m4k_write_memory(target, address, 4, count, buffer);
  914. }
  915. return retval;
  916. }
  917. struct target_type mips_m4k_target =
  918. {
  919. .name = "mips_m4k",
  920. .poll = mips_m4k_poll,
  921. .arch_state = mips32_arch_state,
  922. .target_request_data = NULL,
  923. .halt = mips_m4k_halt,
  924. .resume = mips_m4k_resume,
  925. .step = mips_m4k_step,
  926. .assert_reset = mips_m4k_assert_reset,
  927. .deassert_reset = mips_m4k_deassert_reset,
  928. .soft_reset_halt = mips_m4k_soft_reset_halt,
  929. .get_gdb_reg_list = mips32_get_gdb_reg_list,
  930. .read_memory = mips_m4k_read_memory,
  931. .write_memory = mips_m4k_write_memory,
  932. .bulk_write_memory = mips_m4k_bulk_write_memory,
  933. .checksum_memory = mips32_checksum_memory,
  934. .blank_check_memory = mips32_blank_check_memory,
  935. .run_algorithm = mips32_run_algorithm,
  936. .add_breakpoint = mips_m4k_add_breakpoint,
  937. .remove_breakpoint = mips_m4k_remove_breakpoint,
  938. .add_watchpoint = mips_m4k_add_watchpoint,
  939. .remove_watchpoint = mips_m4k_remove_watchpoint,
  940. .target_create = mips_m4k_target_create,
  941. .init_target = mips_m4k_init_target,
  942. .examine = mips_m4k_examine,
  943. };