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  1. /***************************************************************************
  2. * Copyright (C) 2008 by *
  3. * Karl RobinSod <karl.robinsod@gmail.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. /***************************************************************************
  21. * There are some things to notice
  22. *
  23. * You need to unprotect flash sectors each time you connect the OpenOCD
  24. * Dumping 1MB takes about 60 Seconds
  25. * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
  26. * Writing 1MB takes 88 seconds
  27. *
  28. ***************************************************************************/
  29. #ifdef HAVE_CONFIG_H
  30. #include "config.h"
  31. #endif
  32. #include "replacements.h"
  33. #include "lpc288x.h"
  34. #include "flash.h"
  35. #include "target.h"
  36. #include "log.h"
  37. #include "binarybuffer.h"
  38. #include "types.h"
  39. #include <stdlib.h>
  40. #include <string.h>
  41. #include <unistd.h>
  42. #define LOAD_TIMER_ERASE 0
  43. #define LOAD_TIMER_WRITE 1
  44. #define FLASH_PAGE_SIZE 512
  45. /* LPC288X control registers */
  46. #define DBGU_CIDR 0x8000507C
  47. /* LPC288X flash registers */
  48. #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
  49. #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
  50. #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
  51. #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
  52. #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0 */
  53. #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
  54. #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
  55. #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
  56. #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
  57. #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
  58. #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
  59. #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power savings. R/W 1*/
  60. #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from Power Down mode. R/W -*/
  61. /* F_CTRL bits */
  62. #define FC_CS 0x0001
  63. #define FC_FUNC 0x0002
  64. #define FC_WEN 0x0004
  65. #define FC_RD_LATCH 0x0020
  66. #define FC_PROTECT 0x0080
  67. #define FC_SET_DATA 0x0400
  68. #define FC_RSSL 0x0800
  69. #define FC_PROG_REQ 0x1000
  70. #define FC_CLR_BUF 0x4000
  71. #define FC_LOAD_REQ 0x8000
  72. /* F_STAT bits */
  73. #define FS_DONE 0x0001
  74. #define FS_PROGGNT 0x0002
  75. #define FS_RDY 0x0004
  76. #define FS_ERR 0x0020
  77. /* F_PROG_TIME */
  78. #define FPT_TIME_MASK 0x7FFF
  79. #define FPT_ENABLE 0x8000
  80. /* F_WAIT */
  81. #define FW_WAIT_STATES_MASK 0x00FF
  82. #define FW_SET_MASK 0xC000
  83. /* F_CLK_TIME */
  84. #define FCT_CLK_DIV_MASK 0x0FFF
  85. int lpc288x_register_commands(struct command_context_s *cmd_ctx);
  86. int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  87. int lpc288x_erase(struct flash_bank_s *bank, int first, int last);
  88. int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last);
  89. int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  90. int lpc288x_probe(struct flash_bank_s *bank);
  91. int lpc288x_auto_probe(struct flash_bank_s *bank);
  92. int lpc288x_erase_check(struct flash_bank_s *bank);
  93. int lpc288x_protect_check(struct flash_bank_s *bank);
  94. int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  95. void lpc288x_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
  96. u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout);
  97. void lpc288x_load_timer(int erase, struct target_s *target);
  98. void lpc288x_set_flash_clk(struct flash_bank_s *bank);
  99. u32 lpc288x_system_ready(struct flash_bank_s *bank);
  100. int lpc288x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  101. flash_driver_t lpc288x_flash =
  102. {
  103. .name = "lpc288x",
  104. .register_commands = lpc288x_register_commands,
  105. .flash_bank_command = lpc288x_flash_bank_command,
  106. .erase = lpc288x_erase,
  107. .protect = lpc288x_protect,
  108. .write = lpc288x_write,
  109. .probe = lpc288x_probe,
  110. .auto_probe = lpc288x_probe,
  111. .erase_check = lpc288x_erase_check,
  112. .protect_check = lpc288x_protect_check,
  113. .info = lpc288x_info
  114. };
  115. int lpc288x_register_commands(struct command_context_s *cmd_ctx)
  116. {
  117. return ERROR_OK;
  118. }
  119. u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
  120. {
  121. u32 status;
  122. target_t *target = bank->target;
  123. do
  124. {
  125. usleep(1000);
  126. timeout--;
  127. target_read_u32(target, F_STAT, &status);
  128. }while (((status & FS_DONE) == 0) && timeout);
  129. if(timeout == 0)
  130. {
  131. LOG_DEBUG("Timedout!");
  132. return ERROR_FLASH_OPERATION_FAILED;
  133. }
  134. return ERROR_OK;
  135. }
  136. /* Read device id register and fill in driver info structure */
  137. int lpc288x_read_part_info(struct flash_bank_s *bank)
  138. {
  139. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  140. target_t *target = bank->target;
  141. u32 cidr, status;
  142. int sectornum;
  143. int i = 0;
  144. u32 offset;
  145. if (lpc288x_info->cidr == 0x0102100A)
  146. return ERROR_OK; /* already probed, multiple probes may cause memory leak, not allowed */
  147. /* Read and parse chip identification register */
  148. target_read_u32(target, DBGU_CIDR, &cidr);
  149. if (cidr != 0x0102100A)
  150. {
  151. LOG_WARNING("Cannot identify target as an LPC288X (%08X)",cidr);
  152. return ERROR_FLASH_OPERATION_FAILED;
  153. }
  154. lpc288x_info->cidr = cidr;
  155. lpc288x_info->sector_size_break = 0x000F0000;
  156. lpc288x_info->target_name = "LPC288x";
  157. /* setup the sector info... */
  158. offset = bank->base;
  159. bank->num_sectors = 23;
  160. bank->sectors = malloc(sizeof(flash_sector_t) * 23);
  161. for (i = 0; i < 15; i++)
  162. {
  163. bank->sectors[i].offset = offset;
  164. bank->sectors[i].size = 64 * 1024;
  165. offset += bank->sectors[i].size;
  166. bank->sectors[i].is_erased = -1;
  167. bank->sectors[i].is_protected = 1;
  168. }
  169. for (i = 15; i < 23; i++)
  170. {
  171. bank->sectors[i].offset = offset;
  172. bank->sectors[i].size = 8 * 1024;
  173. offset += bank->sectors[i].size;
  174. bank->sectors[i].is_erased = -1;
  175. bank->sectors[i].is_protected = 1;
  176. }
  177. return ERROR_OK;
  178. }
  179. int lpc288x_protect_check(struct flash_bank_s *bank)
  180. {
  181. return ERROR_OK;
  182. }
  183. /* flash_bank LPC288x 0 0 0 0 <target#> <cclk>
  184. */
  185. int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  186. {
  187. lpc288x_flash_bank_t *lpc288x_info;
  188. int i;
  189. if (argc < 6)
  190. {
  191. LOG_WARNING("incomplete flash_bank LPC288x configuration");
  192. return ERROR_FLASH_BANK_INVALID;
  193. }
  194. lpc288x_info = malloc(sizeof(lpc288x_flash_bank_t));
  195. bank->driver_priv = lpc288x_info;
  196. /* part wasn't probed for info yet */
  197. lpc288x_info->cidr = 0;
  198. lpc288x_info->cclk = strtoul(args[6], NULL, 0);
  199. return ERROR_OK;
  200. }
  201. /*
  202. The frequency is the AHB clock frequency divided by (CLK_DIV ×
  203. 3) + 1. This must be programmed such that the Flash
  204. Programming clock frequency is 66 kHz ± 20%.
  205. AHB = 12 MHz ?
  206. 12000000/66000 = 182
  207. CLK_DIV = 60 ?
  208. */
  209. void lpc288x_set_flash_clk(struct flash_bank_s *bank)
  210. {
  211. u32 clk_time;
  212. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  213. clk_time = (lpc288x_info->cclk / 66000) / 3;
  214. target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN );
  215. target_write_u32(bank->target, F_CLK_TIME, clk_time);
  216. }
  217. /*
  218. AHB tcyc (in ns) 83 ns
  219. LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
  220. = 9412 (9500) (AN10548 9375)
  221. LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
  222. = 23 (75) (AN10548 72 - is this wrong?)
  223. TODO: Sort out timing calcs ;)
  224. */
  225. void lpc288x_load_timer(int erase, struct target_s *target)
  226. {
  227. if(erase == LOAD_TIMER_ERASE)
  228. {
  229. target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500);
  230. }
  231. else
  232. {
  233. target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75);
  234. }
  235. }
  236. u32 lpc288x_system_ready(struct flash_bank_s *bank)
  237. {
  238. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  239. if (lpc288x_info->cidr == 0)
  240. {
  241. return ERROR_FLASH_BANK_NOT_PROBED;
  242. }
  243. if (bank->target->state != TARGET_HALTED)
  244. {
  245. return ERROR_TARGET_NOT_HALTED;
  246. }
  247. return ERROR_OK;
  248. }
  249. int lpc288x_erase_check(struct flash_bank_s *bank)
  250. {
  251. u32 buffer, test_bytes;
  252. u32 addr, sector, i, status = lpc288x_system_ready(bank); /* probed? halted? */
  253. if(status != ERROR_OK)
  254. {
  255. LOG_INFO("Processor not halted/not probed");
  256. return status;
  257. }
  258. return ERROR_OK;
  259. }
  260. int lpc288x_erase(struct flash_bank_s *bank, int first, int last)
  261. {
  262. u32 status;
  263. int sector;
  264. target_t *target = bank->target;
  265. status = lpc288x_system_ready(bank); /* probed? halted? */
  266. if(status != ERROR_OK)
  267. {
  268. return status;
  269. }
  270. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  271. {
  272. LOG_INFO("Bad sector range");
  273. return ERROR_FLASH_SECTOR_INVALID;
  274. }
  275. /* Configure the flash controller timing */
  276. lpc288x_set_flash_clk(bank);
  277. for (sector = first; sector <= last; sector++)
  278. {
  279. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  280. {
  281. return ERROR_FLASH_OPERATION_FAILED;
  282. }
  283. lpc288x_load_timer(LOAD_TIMER_ERASE,target);
  284. target_write_u32( target,
  285. bank->sectors[sector].offset,
  286. 0x00);
  287. target_write_u32( target,
  288. F_CTRL,
  289. FC_PROG_REQ |
  290. FC_PROTECT |
  291. FC_CS);
  292. }
  293. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  294. {
  295. return ERROR_FLASH_OPERATION_FAILED;
  296. }
  297. return ERROR_OK;
  298. }
  299. int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
  300. {
  301. u8 page_buffer[FLASH_PAGE_SIZE];
  302. u32 i, status, source_offset,dest_offset;
  303. target_t *target = bank->target;
  304. u32 bytes_remaining = count;
  305. u32 first_sector, last_sector, sector, page;
  306. /* probed? halted? */
  307. status = lpc288x_system_ready(bank);
  308. if(status != ERROR_OK)
  309. {
  310. return status;
  311. }
  312. /* Initialise search indices */
  313. first_sector = last_sector = 0xffffffff;
  314. /* validate the write range... */
  315. for(i = 0; i < bank->num_sectors; i++)
  316. {
  317. if((offset >= bank->sectors[i].offset) &&
  318. (offset < (bank->sectors[i].offset + bank->sectors[i].size)) &&
  319. (first_sector == 0xffffffff))
  320. {
  321. first_sector = i;
  322. /* all writes must start on a sector boundary... */
  323. if (offset % bank->sectors[i].size)
  324. {
  325. LOG_INFO("offset 0x%x breaks required alignment 0x%x", offset, bank->sectors[i].size);
  326. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  327. }
  328. }
  329. if(((offset + count) > bank->sectors[i].offset) &&
  330. ((offset + count) <= (bank->sectors[i].offset + bank->sectors[i].size)) &&
  331. (last_sector == 0xffffffff))
  332. {
  333. last_sector = i;
  334. }
  335. }
  336. /* Range check... */
  337. if (first_sector == 0xffffffff || last_sector == 0xffffffff)
  338. {
  339. LOG_INFO("Range check failed %x %x", offset, count);
  340. return ERROR_FLASH_DST_OUT_OF_BANK;
  341. }
  342. /* Configure the flash controller timing */
  343. lpc288x_set_flash_clk(bank);
  344. /* initialise the offsets */
  345. source_offset = 0;
  346. dest_offset = 0;
  347. for (sector=first_sector; sector<=last_sector; sector++)
  348. {
  349. for(page = 0; page < bank->sectors[sector].size / FLASH_PAGE_SIZE; page++)
  350. {
  351. if(bytes_remaining == 0)
  352. {
  353. count = 0;
  354. memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
  355. }
  356. else if (bytes_remaining < FLASH_PAGE_SIZE)
  357. {
  358. count = bytes_remaining;
  359. memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
  360. memcpy(page_buffer, &buffer[source_offset], count);
  361. }
  362. else
  363. {
  364. count = FLASH_PAGE_SIZE;
  365. memcpy(page_buffer, &buffer[source_offset], count);
  366. }
  367. /* Wait for flash to become ready */
  368. if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
  369. {
  370. return ERROR_FLASH_OPERATION_FAILED;
  371. }
  372. /* fill flash data latches with 1's */
  373. target_write_u32(target, F_CTRL,
  374. FC_CS |
  375. FC_SET_DATA |
  376. FC_WEN |
  377. FC_FUNC );
  378. target_write_u32(target, F_CTRL,
  379. FC_CS |
  380. FC_WEN |
  381. FC_FUNC );
  382. /*would be better to use the clean target_write_buffer() interface but
  383. it seems not to be a LOT slower....
  384. bulk_write_memory() is no quicker :(*/
  385. #if 1
  386. if (target->type->write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK)
  387. {
  388. LOG_ERROR("Write failed s %x p %x", sector, page);
  389. return ERROR_FLASH_OPERATION_FAILED;
  390. }
  391. #else
  392. if(target_write_buffer(target, offset + dest_offset, FLASH_PAGE_SIZE, page_buffer) != ERROR_OK)
  393. {
  394. LOG_INFO("Write to flash buffer failed");
  395. return ERROR_FLASH_OPERATION_FAILED;
  396. }
  397. #endif
  398. dest_offset += FLASH_PAGE_SIZE;
  399. source_offset += count;
  400. bytes_remaining -= count;
  401. lpc288x_load_timer(LOAD_TIMER_WRITE, target);
  402. target_write_u32( target,
  403. F_CTRL,
  404. FC_PROG_REQ |
  405. FC_PROTECT |
  406. FC_FUNC |
  407. FC_CS);
  408. }
  409. }
  410. return ERROR_OK;
  411. }
  412. int lpc288x_probe(struct flash_bank_s *bank)
  413. {
  414. /* we only deal with LPC2888 so flash config is fixed
  415. */
  416. lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
  417. int retval;
  418. if (lpc288x_info->cidr != 0)
  419. {
  420. return ERROR_OK; /* already probed */
  421. }
  422. if (bank->target->state != TARGET_HALTED)
  423. {
  424. return ERROR_TARGET_NOT_HALTED;
  425. }
  426. retval = lpc288x_read_part_info(bank);
  427. if (retval != ERROR_OK)
  428. return retval;
  429. return ERROR_OK;
  430. }
  431. int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size)
  432. {
  433. snprintf(buf, buf_size, "lpc288x flash driver");
  434. return ERROR_OK;
  435. }
  436. int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last)
  437. {
  438. int lockregion, status;
  439. u32 value;
  440. target_t *target = bank->target;
  441. /* probed? halted? */
  442. status = lpc288x_system_ready(bank);
  443. if(status != ERROR_OK)
  444. {
  445. return status;
  446. }
  447. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  448. {
  449. return ERROR_FLASH_SECTOR_INVALID;
  450. }
  451. /* Configure the flash controller timing */
  452. lpc288x_set_flash_clk(bank);
  453. for (lockregion = first; lockregion <= last; lockregion++)
  454. {
  455. if(set)
  456. {
  457. /* write an odd value to base addy to protect... */
  458. value = 0x01;
  459. }
  460. else
  461. {
  462. /* write an even value to base addy to unprotect... */
  463. value = 0x00;
  464. }
  465. target_write_u32( target,
  466. bank->sectors[lockregion].offset,
  467. value);
  468. target_write_u32( target,
  469. F_CTRL,
  470. FC_LOAD_REQ |
  471. FC_PROTECT |
  472. FC_WEN |
  473. FC_FUNC |
  474. FC_CS);
  475. }
  476. return ERROR_OK;
  477. }