You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

210 lines
8.2 KiB

  1. #################################################################################################
  2. # #
  3. # Author: Gary Carlson (gcarlson@carlson-minot.com) #
  4. # Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. #
  5. # #
  6. #################################################################################################
  7. # FIXME use some standard target config, maybe create one from this
  8. #
  9. # source [find target/...cfg]
  10. # Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of
  11. # the AT91SAM9260 and shares the same tap ID as it.
  12. set _CHIPNAME at91sam9g20
  13. set _ENDIAN little
  14. set _CPUTAPID 0x0792603f
  15. # Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. In theory this script
  16. # therefore should require "srst_only". With some J-Link debuggers at least, "srst_only" causes a temporary USB
  17. # communication fault. This appears to be more likely attributed to an internal proprietary firmware quirk inside the
  18. # dongle itself. Using "trst_and_srst" works fine, however. So if you can't beat them -- join them. If you are using
  19. # something other the a J-Link dongle you may be able to change this back to "srst_only".
  20. reset_config trst_and_srst
  21. # Set up the CPU and generate a new jtag tap for AT91SAM9G20.
  22. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  23. # Use caution changing the delays listed below. These seem to be
  24. # affected by the board and type of JTAG adapter. A value of 200 ms seems
  25. # to work reliably for the configuration listed in the file header above.
  26. adapter_nsrst_delay 200
  27. jtag_ntrst_delay 200
  28. # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
  29. jtag_rclk 5
  30. set _TARGETNAME $_CHIPNAME.cpu
  31. target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
  32. # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
  33. # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
  34. # Both areas are 16 kB long.
  35. #$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
  36. $_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
  37. # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
  38. # AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
  39. # some powerful features, we want to have a special function that handles "reset init". To do this we declare
  40. # an event handler where these special activities can take place.
  41. scan_chain
  42. $_TARGETNAME configure -event reset-init {at91sam9g20_init}
  43. # NandFlash configuration and definition
  44. # Future TBD
  45. proc read_register {register} {
  46. set result ""
  47. ocd_mem2array result 32 $register 1
  48. return $result(0)
  49. }
  50. proc at91sam9g20_init { } {
  51. # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
  52. # a number of steps that must be carefully performed. The process outline below follows the
  53. # recommended procedure outlined in the AT91SAM9G20 technical manual.
  54. #
  55. # Several key and very important things to keep in mind:
  56. # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
  57. # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
  58. # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
  59. adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
  60. halt # Make sure processor is halted, or error will result in following steps.
  61. mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
  62. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
  63. # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
  64. # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
  65. mww 0xfffffc20 0x00004001
  66. while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
  67. # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
  68. # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
  69. mww 0xfffffc28 0x202a3f01
  70. while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
  71. # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
  72. # Wait for MCKRDY signal from PMC_SR to assert.
  73. mww 0xfffffc30 0x00000101
  74. while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
  75. # Now change PMC_MCKR register to select PLLA.
  76. # Wait for MCKRDY signal from PMC_SR to assert.
  77. mww 0xfffffc30 0x00001302
  78. while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
  79. # Processor and master clocks are now operating and stable at maximum frequency possible:
  80. # -> MCLK = 132.096 MHz
  81. # -> PCLK = 396.288 MHz
  82. # Switch over to adaptive clocking.
  83. adapter_khz 0
  84. # Enable faster DCC downloads.
  85. arm7_9 dcc_downloads enable
  86. # To be able to use external SDRAM, several peripheral configuration registers must
  87. # be modified. The first change is made to PIO_ASR to select peripheral functions
  88. # for D15 through D31. The second change is made to the PIO_PDR register to disable
  89. # this for D15 through D31.
  90. mww 0xfffff870 0xffff0000
  91. mww 0xfffff804 0xffff0000
  92. # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
  93. # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
  94. # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
  95. mww 0xffffef1c 0x000100a
  96. # The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
  97. # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
  98. # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
  99. mww 0xffffec30 0x00020002
  100. mww 0xffffec34 0x04040404
  101. mww 0xffffec38 0x00070007
  102. mww 0xffffec3c 0x00030003
  103. # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
  104. # nand probe 0
  105. # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
  106. # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
  107. # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
  108. # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
  109. # of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
  110. #
  111. # CAS latency = 3 cycles
  112. # TXSR = 10 cycles
  113. # TRAS = 6 cycles
  114. # TRCD = 3 cycles
  115. # TRP = 3 cycles
  116. # TRC = 9 cycles
  117. # TWR = 2 cycles
  118. # 9 column, 13 row, 4 banks
  119. # refresh equal to or less then 7.8 us for commerical/industrial rated devices
  120. #
  121. # Thus SDRAM_CR = 0xa6339279
  122. mww 0xffffea08 0xa6339279
  123. # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
  124. # the starting memory location for the SDRAM.
  125. mww 0xffffea00 0x00000001
  126. mww 0x20000000 0
  127. # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
  128. # value into the starting memory location for the SDRAM.
  129. mww 0xffffea00 0x00000002
  130. mww 0x20000000 0
  131. # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
  132. # zero values eight times into the starting memory location for the SDRAM.
  133. mww 0xffffea00 0x4
  134. mww 0x20000000 0
  135. mww 0x20000000 0
  136. mww 0x20000000 0
  137. mww 0x20000000 0
  138. mww 0x20000000 0
  139. mww 0x20000000 0
  140. mww 0x20000000 0
  141. mww 0x20000000 0
  142. # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
  143. # the starting memory location for the SDRAM.
  144. mww 0xffffea00 0x3
  145. mww 0x20000000 0
  146. # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
  147. # memory location for the SDRAM.
  148. mww 0xffffea00 0x0
  149. mww 0x20000000 0
  150. # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
  151. mww 0xffffea04 0x0000039c
  152. }