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  1. /***************************************************************************
  2. * Copyright (C) 2008 digenius technology GmbH. *
  3. * Michael Bruck *
  4. * *
  5. * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  21. ***************************************************************************/
  22. #ifndef ARM11_H
  23. #define ARM11_H
  24. #include "arm.h"
  25. #include "arm_dpm.h"
  26. #define ARM11_TAP_DEFAULT TAP_INVALID
  27. #define CHECK_RETVAL(action) \
  28. do { \
  29. int __retval = (action); \
  30. if (__retval != ERROR_OK) { \
  31. LOG_DEBUG("error while calling \"%s\"", \
  32. # action ); \
  33. return __retval; \
  34. } \
  35. } while (0)
  36. /* bits from ARMv7 DIDR */
  37. enum arm11_debug_version
  38. {
  39. ARM11_DEBUG_V6 = 0x01,
  40. ARM11_DEBUG_V61 = 0x02,
  41. ARM11_DEBUG_V7 = 0x03,
  42. ARM11_DEBUG_V7_CP14 = 0x04,
  43. };
  44. struct arm11_common
  45. {
  46. struct arm arm;
  47. /** Debug module state. */
  48. struct arm_dpm dpm;
  49. struct arm11_sc7_action *bpwp_actions;
  50. unsigned bpwp_n;
  51. size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
  52. size_t free_brps; /**< Number of breakpoints allocated */
  53. uint32_t dscr; /**< Last retrieved DSCR value. */
  54. uint32_t saved_rdtr;
  55. uint32_t saved_wdtr;
  56. bool is_rdtr_saved;
  57. bool is_wdtr_saved;
  58. bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
  59. struct arm_jtag jtag_info;
  60. };
  61. static inline struct arm11_common *target_to_arm11(struct target *target)
  62. {
  63. return container_of(target->arch_info, struct arm11_common,
  64. arm);
  65. }
  66. /**
  67. * ARM11 DBGTAP instructions
  68. *
  69. * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  70. */
  71. enum arm11_instructions
  72. {
  73. ARM11_EXTEST = 0x00,
  74. ARM11_SCAN_N = 0x02,
  75. ARM11_RESTART = 0x04,
  76. ARM11_HALT = 0x08,
  77. ARM11_INTEST = 0x0C,
  78. ARM11_ITRSEL = 0x1D,
  79. ARM11_IDCODE = 0x1E,
  80. ARM11_BYPASS = 0x1F,
  81. };
  82. enum arm11_sc7
  83. {
  84. ARM11_SC7_NULL = 0,
  85. ARM11_SC7_VCR = 7,
  86. ARM11_SC7_PC = 8,
  87. ARM11_SC7_BVR0 = 64,
  88. ARM11_SC7_BCR0 = 80,
  89. ARM11_SC7_WVR0 = 96,
  90. ARM11_SC7_WCR0 = 112,
  91. };
  92. #endif /* ARM11_H */