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  1. /***************************************************************************
  2. * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc., *
  17. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  18. ***************************************************************************/
  19. #ifdef HAVE_CONFIG_H
  20. #include "config.h"
  21. #endif
  22. #include "mflash.h"
  23. #include "target.h"
  24. #include "time_support.h"
  25. #include <helper/fileio.h>
  26. #include <helper/log.h>
  27. static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio);
  28. static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val);
  29. static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio);
  30. static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val);
  31. static struct mflash_bank *mflash_bank;
  32. static struct mflash_gpio_drv pxa270_gpio = {
  33. .name = "pxa270",
  34. .set_gpio_to_output = pxa270_set_gpio_to_output,
  35. .set_gpio_output_val = pxa270_set_gpio_output_val
  36. };
  37. static struct mflash_gpio_drv s3c2440_gpio = {
  38. .name = "s3c2440",
  39. .set_gpio_to_output = s3c2440_set_gpio_to_output,
  40. .set_gpio_output_val = s3c2440_set_gpio_output_val
  41. };
  42. static struct mflash_gpio_drv *mflash_gpio[] =
  43. {
  44. &pxa270_gpio,
  45. &s3c2440_gpio,
  46. NULL
  47. };
  48. #define PXA270_GAFR0_L 0x40E00054
  49. #define PXA270_GAFR3_U 0x40E00070
  50. #define PXA270_GAFR3_U_RESERVED_BITS 0xfffc0000u
  51. #define PXA270_GPDR0 0x40E0000C
  52. #define PXA270_GPDR3 0x40E0010C
  53. #define PXA270_GPDR3_RESERVED_BITS 0xfe000000u
  54. #define PXA270_GPSR0 0x40E00018
  55. #define PXA270_GPCR0 0x40E00024
  56. static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio)
  57. {
  58. uint32_t addr, value, mask;
  59. struct target *target = mflash_bank->target;
  60. int ret;
  61. /* remove alternate function. */
  62. mask = 0x3u << (gpio.num & 0xF)*2;
  63. addr = PXA270_GAFR0_L + (gpio.num >> 4) * 4;
  64. if ((ret = target_read_u32(target, addr, &value)) != ERROR_OK)
  65. return ret;
  66. value &= ~mask;
  67. if (addr == PXA270_GAFR3_U)
  68. value &= ~PXA270_GAFR3_U_RESERVED_BITS;
  69. if ((ret = target_write_u32(target, addr, value)) != ERROR_OK)
  70. return ret;
  71. /* set direction to output */
  72. mask = 0x1u << (gpio.num & 0x1F);
  73. addr = PXA270_GPDR0 + (gpio.num >> 5) * 4;
  74. if ((ret = target_read_u32(target, addr, &value)) != ERROR_OK)
  75. return ret;
  76. value |= mask;
  77. if (addr == PXA270_GPDR3)
  78. value &= ~PXA270_GPDR3_RESERVED_BITS;
  79. ret = target_write_u32(target, addr, value);
  80. return ret;
  81. }
  82. static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val)
  83. {
  84. uint32_t addr, value, mask;
  85. struct target *target = mflash_bank->target;
  86. int ret;
  87. mask = 0x1u << (gpio.num & 0x1F);
  88. if (val) {
  89. addr = PXA270_GPSR0 + (gpio.num >> 5) * 4;
  90. } else {
  91. addr = PXA270_GPCR0 + (gpio.num >> 5) * 4;
  92. }
  93. if ((ret = target_read_u32(target, addr, &value)) != ERROR_OK)
  94. return ret;
  95. value |= mask;
  96. ret = target_write_u32(target, addr, value);
  97. return ret;
  98. }
  99. #define S3C2440_GPACON 0x56000000
  100. #define S3C2440_GPADAT 0x56000004
  101. #define S3C2440_GPJCON 0x560000d0
  102. #define S3C2440_GPJDAT 0x560000d4
  103. static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio)
  104. {
  105. uint32_t data, mask, gpio_con;
  106. struct target *target = mflash_bank->target;
  107. int ret;
  108. if (gpio.port[0] >= 'a' && gpio.port[0] <= 'h') {
  109. gpio_con = S3C2440_GPACON + (gpio.port[0] - 'a') * 0x10;
  110. } else if (gpio.port[0] == 'j') {
  111. gpio_con = S3C2440_GPJCON;
  112. } else {
  113. LOG_ERROR("mflash: invalid port %d%s", gpio.num, gpio.port);
  114. return ERROR_INVALID_ARGUMENTS;
  115. }
  116. ret = target_read_u32(target, gpio_con, &data);
  117. if (ret == ERROR_OK) {
  118. if (gpio.port[0] == 'a') {
  119. mask = 1 << gpio.num;
  120. data &= ~mask;
  121. } else {
  122. mask = 3 << gpio.num * 2;
  123. data &= ~mask;
  124. data |= (1 << gpio.num * 2);
  125. }
  126. ret = target_write_u32(target, gpio_con, data);
  127. }
  128. return ret;
  129. }
  130. static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val)
  131. {
  132. uint32_t data, mask, gpio_dat;
  133. struct target *target = mflash_bank->target;
  134. int ret;
  135. if (gpio.port[0] >= 'a' && gpio.port[0] <= 'h') {
  136. gpio_dat = S3C2440_GPADAT + (gpio.port[0] - 'a') * 0x10;
  137. } else if (gpio.port[0] == 'j') {
  138. gpio_dat = S3C2440_GPJDAT;
  139. } else {
  140. LOG_ERROR("mflash: invalid port %d%s", gpio.num, gpio.port);
  141. return ERROR_INVALID_ARGUMENTS;
  142. }
  143. ret = target_read_u32(target, gpio_dat, &data);
  144. if (ret == ERROR_OK) {
  145. mask = 1 << gpio.num;
  146. if (val)
  147. data |= mask;
  148. else
  149. data &= ~mask;
  150. ret = target_write_u32(target, gpio_dat, data);
  151. }
  152. return ret;
  153. }
  154. static int mg_hdrst(uint8_t level)
  155. {
  156. return mflash_bank->gpio_drv->set_gpio_output_val(mflash_bank->rst_pin, level);
  157. }
  158. static int mg_init_gpio (void)
  159. {
  160. int ret;
  161. struct mflash_gpio_drv *gpio_drv = mflash_bank->gpio_drv;
  162. ret = gpio_drv->set_gpio_to_output(mflash_bank->rst_pin);
  163. if (ret != ERROR_OK)
  164. return ret;
  165. ret = gpio_drv->set_gpio_output_val(mflash_bank->rst_pin, 1);
  166. return ret;
  167. }
  168. static int mg_dsk_wait(mg_io_type_wait wait, uint32_t time)
  169. {
  170. uint8_t status, error;
  171. struct target *target = mflash_bank->target;
  172. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  173. int ret;
  174. long long t = 0;
  175. struct duration bench;
  176. duration_start(&bench);
  177. while (time) {
  178. ret = target_read_u8(target, mg_task_reg + MG_REG_STATUS, &status);
  179. if (ret != ERROR_OK)
  180. return ret;
  181. if (status & mg_io_rbit_status_busy)
  182. {
  183. if (wait == mg_io_wait_bsy)
  184. return ERROR_OK;
  185. } else {
  186. switch (wait)
  187. {
  188. case mg_io_wait_not_bsy:
  189. return ERROR_OK;
  190. case mg_io_wait_rdy_noerr:
  191. if (status & mg_io_rbit_status_ready)
  192. return ERROR_OK;
  193. break;
  194. case mg_io_wait_drq_noerr:
  195. if (status & mg_io_rbit_status_data_req)
  196. return ERROR_OK;
  197. break;
  198. default:
  199. break;
  200. }
  201. /* Now we check the error condition! */
  202. if (status & mg_io_rbit_status_error)
  203. {
  204. ret = target_read_u8(target, mg_task_reg + MG_REG_ERROR, &error);
  205. if (ret != ERROR_OK)
  206. return ret;
  207. LOG_ERROR("mflash: io error 0x%02x", error);
  208. return ERROR_MG_IO;
  209. }
  210. switch (wait)
  211. {
  212. case mg_io_wait_rdy:
  213. if (status & mg_io_rbit_status_ready)
  214. return ERROR_OK;
  215. case mg_io_wait_drq:
  216. if (status & mg_io_rbit_status_data_req)
  217. return ERROR_OK;
  218. default:
  219. break;
  220. }
  221. }
  222. ret = duration_measure(&bench);
  223. if (ERROR_OK == ret)
  224. t = duration_elapsed(&bench) * 1000.0;
  225. else
  226. LOG_ERROR("mflash: duration measurement failed: %d", ret);
  227. if (t > time)
  228. break;
  229. }
  230. LOG_ERROR("mflash: timeout occured");
  231. return ERROR_MG_TIMEOUT;
  232. }
  233. static int mg_dsk_srst(uint8_t on)
  234. {
  235. struct target *target = mflash_bank->target;
  236. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  237. uint8_t value;
  238. int ret;
  239. if ((ret = target_read_u8(target, mg_task_reg + MG_REG_DRV_CTRL, &value)) != ERROR_OK)
  240. return ret;
  241. if (on) {
  242. value |= (mg_io_rbit_devc_srst);
  243. } else {
  244. value &= ~mg_io_rbit_devc_srst;
  245. }
  246. ret = target_write_u8(target, mg_task_reg + MG_REG_DRV_CTRL, value);
  247. return ret;
  248. }
  249. static int mg_dsk_io_cmd(uint32_t sect_num, uint32_t cnt, uint8_t cmd)
  250. {
  251. struct target *target = mflash_bank->target;
  252. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  253. uint8_t value;
  254. int ret;
  255. ret = mg_dsk_wait(mg_io_wait_rdy_noerr, MG_OEM_DISK_WAIT_TIME_NORMAL);
  256. if (ret != ERROR_OK)
  257. return ret;
  258. value = mg_io_rval_dev_drv_master | mg_io_rval_dev_lba_mode |((sect_num >> 24) & 0xf);
  259. ret = target_write_u8(target, mg_task_reg + MG_REG_DRV_HEAD, value);
  260. ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_CNT, (uint8_t)cnt);
  261. ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_NUM, (uint8_t)sect_num);
  262. ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_LOW, (uint8_t)(sect_num >> 8));
  263. ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_HIGH, (uint8_t)(sect_num >> 16));
  264. if (ret != ERROR_OK)
  265. return ret;
  266. return target_write_u8(target, mg_task_reg + MG_REG_COMMAND, cmd);
  267. }
  268. static int mg_dsk_drv_info(void)
  269. {
  270. struct target *target = mflash_bank->target;
  271. uint32_t mg_buff = mflash_bank->base + MG_BUFFER_OFFSET;
  272. int ret;
  273. if ((ret = mg_dsk_io_cmd(0, 1, mg_io_cmd_identify)) != ERROR_OK)
  274. return ret;
  275. if ((ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL)) != ERROR_OK)
  276. return ret;
  277. LOG_INFO("mflash: read drive info");
  278. if (! mflash_bank->drv_info)
  279. mflash_bank->drv_info = malloc(sizeof(struct mg_drv_info));
  280. target_read_memory(target, mg_buff, 2, sizeof(mg_io_type_drv_info) >> 1,
  281. (uint8_t *)&mflash_bank->drv_info->drv_id);
  282. if (ret != ERROR_OK)
  283. return ret;
  284. mflash_bank->drv_info->tot_sects = (uint32_t)(mflash_bank->drv_info->drv_id.total_user_addressable_sectors_hi << 16)
  285. + mflash_bank->drv_info->drv_id.total_user_addressable_sectors_lo;
  286. return target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_read);
  287. }
  288. static int mg_mflash_rst(void)
  289. {
  290. int ret;
  291. if ((ret = mg_init_gpio()) != ERROR_OK)
  292. return ret;
  293. if ((ret = mg_hdrst(0)) != ERROR_OK)
  294. return ret;
  295. if ((ret = mg_dsk_wait(mg_io_wait_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  296. return ret;
  297. if ((ret = mg_hdrst(1)) != ERROR_OK)
  298. return ret;
  299. if ((ret = mg_dsk_wait(mg_io_wait_not_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  300. return ret;
  301. if ((ret = mg_dsk_srst(1)) != ERROR_OK)
  302. return ret;
  303. if ((ret = mg_dsk_wait(mg_io_wait_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  304. return ret;
  305. if ((ret = mg_dsk_srst(0)) != ERROR_OK)
  306. return ret;
  307. if ((ret = mg_dsk_wait(mg_io_wait_not_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  308. return ret;
  309. LOG_INFO("mflash: reset ok");
  310. return ERROR_OK;
  311. }
  312. static int mg_mflash_probe(void)
  313. {
  314. int ret;
  315. if ((ret = mg_mflash_rst()) != ERROR_OK)
  316. return ret;
  317. return mg_dsk_drv_info();
  318. }
  319. COMMAND_HANDLER(mg_probe_cmd)
  320. {
  321. int ret;
  322. ret = mg_mflash_probe();
  323. if (ret == ERROR_OK) {
  324. command_print(CMD_CTX, "mflash (total %" PRIu32 " sectors) found at 0x%8.8" PRIx32 "",
  325. mflash_bank->drv_info->tot_sects, mflash_bank->base);
  326. }
  327. return ret;
  328. }
  329. static int mg_mflash_do_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt)
  330. {
  331. uint32_t i, address;
  332. int ret;
  333. struct target *target = mflash_bank->target;
  334. uint8_t *buff_ptr = buff;
  335. if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, mg_io_cmd_read)) != ERROR_OK)
  336. return ret;
  337. address = mflash_bank->base + MG_BUFFER_OFFSET;
  338. struct duration bench;
  339. duration_start(&bench);
  340. for (i = 0; i < sect_cnt; i++) {
  341. ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL);
  342. if (ret != ERROR_OK)
  343. return ret;
  344. ret = target_read_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
  345. if (ret != ERROR_OK)
  346. return ret;
  347. buff_ptr += MG_MFLASH_SECTOR_SIZE;
  348. ret = target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_read);
  349. if (ret != ERROR_OK)
  350. return ret;
  351. LOG_DEBUG("mflash: %" PRIu32 " (0x%8.8" PRIx32 ") sector read", sect_num + i, (sect_num + i) * MG_MFLASH_SECTOR_SIZE);
  352. ret = duration_measure(&bench);
  353. if ((ERROR_OK == ret) && (duration_elapsed(&bench) > 3)) {
  354. LOG_INFO("mflash: read %" PRIu32 "'th sectors", sect_num + i);
  355. duration_start(&bench);
  356. }
  357. }
  358. return mg_dsk_wait(mg_io_wait_rdy, MG_OEM_DISK_WAIT_TIME_NORMAL);
  359. }
  360. static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt)
  361. {
  362. uint32_t quotient, residue, i;
  363. uint8_t *buff_ptr = buff;
  364. int ret = ERROR_OK;
  365. quotient = sect_cnt >> 8;
  366. residue = sect_cnt % 256;
  367. for (i = 0; i < quotient; i++) {
  368. LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p",
  369. sect_num, buff_ptr);
  370. ret = mg_mflash_do_read_sects(buff_ptr, sect_num, 256);
  371. if (ret != ERROR_OK)
  372. return ret;
  373. sect_num += 256;
  374. buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
  375. }
  376. if (residue) {
  377. LOG_DEBUG("mflash: sect num : %" PRIx32 " buff : %p",
  378. sect_num, buff_ptr);
  379. return mg_mflash_do_read_sects(buff_ptr, sect_num, residue);
  380. }
  381. return ret;
  382. }
  383. static int mg_mflash_do_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt,
  384. mg_io_type_cmd cmd)
  385. {
  386. uint32_t i, address;
  387. int ret;
  388. struct target *target = mflash_bank->target;
  389. uint8_t *buff_ptr = buff;
  390. if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, cmd)) != ERROR_OK)
  391. return ret;
  392. address = mflash_bank->base + MG_BUFFER_OFFSET;
  393. struct duration bench;
  394. duration_start(&bench);
  395. for (i = 0; i < sect_cnt; i++) {
  396. ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL);
  397. if (ret != ERROR_OK)
  398. return ret;
  399. ret = target_write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
  400. if (ret != ERROR_OK)
  401. return ret;
  402. buff_ptr += MG_MFLASH_SECTOR_SIZE;
  403. ret = target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_write);
  404. if (ret != ERROR_OK)
  405. return ret;
  406. LOG_DEBUG("mflash: %" PRIu32 " (0x%8.8" PRIx32 ") sector write", sect_num + i, (sect_num + i) * MG_MFLASH_SECTOR_SIZE);
  407. ret = duration_measure(&bench);
  408. if ((ERROR_OK == ret) && (duration_elapsed(&bench) > 3)) {
  409. LOG_INFO("mflash: wrote %" PRIu32 "'th sectors", sect_num + i);
  410. duration_start(&bench);
  411. }
  412. }
  413. if (cmd == mg_io_cmd_write)
  414. ret = mg_dsk_wait(mg_io_wait_rdy, MG_OEM_DISK_WAIT_TIME_NORMAL);
  415. else
  416. ret = mg_dsk_wait(mg_io_wait_rdy, MG_OEM_DISK_WAIT_TIME_LONG);
  417. return ret;
  418. }
  419. static int mg_mflash_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt)
  420. {
  421. uint32_t quotient, residue, i;
  422. uint8_t *buff_ptr = buff;
  423. int ret = ERROR_OK;
  424. quotient = sect_cnt >> 8;
  425. residue = sect_cnt % 256;
  426. for (i = 0; i < quotient; i++) {
  427. LOG_DEBUG("mflash: sect num : %" PRIu32 "buff : %p", sect_num,
  428. buff_ptr);
  429. ret = mg_mflash_do_write_sects(buff_ptr, sect_num, 256, mg_io_cmd_write);
  430. if (ret != ERROR_OK)
  431. return ret;
  432. sect_num += 256;
  433. buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
  434. }
  435. if (residue) {
  436. LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p", sect_num,
  437. buff_ptr);
  438. return mg_mflash_do_write_sects(buff_ptr, sect_num, residue, mg_io_cmd_write);
  439. }
  440. return ret;
  441. }
  442. static int mg_mflash_read (uint32_t addr, uint8_t *buff, uint32_t len)
  443. {
  444. uint8_t *buff_ptr = buff;
  445. uint8_t sect_buff[MG_MFLASH_SECTOR_SIZE];
  446. uint32_t cur_addr, next_sec_addr, end_addr, cnt, sect_num;
  447. int ret = ERROR_OK;
  448. cnt = 0;
  449. cur_addr = addr;
  450. end_addr = addr + len;
  451. if (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK) {
  452. next_sec_addr = (cur_addr + MG_MFLASH_SECTOR_SIZE) & ~MG_MFLASH_SECTOR_SIZE_MASK;
  453. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  454. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  455. if (ret != ERROR_OK)
  456. return ret;
  457. if (end_addr < next_sec_addr) {
  458. memcpy(buff_ptr, sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), end_addr - cur_addr);
  459. LOG_DEBUG("mflash: copies %" PRIu32 " byte from sector offset 0x%8.8" PRIx32 "", end_addr - cur_addr, cur_addr);
  460. cur_addr = end_addr;
  461. } else {
  462. memcpy(buff_ptr, sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), next_sec_addr - cur_addr);
  463. LOG_DEBUG("mflash: copies %" PRIu32 " byte from sector offset 0x%8.8" PRIx32 "", next_sec_addr - cur_addr, cur_addr);
  464. buff_ptr += (next_sec_addr - cur_addr);
  465. cur_addr = next_sec_addr;
  466. }
  467. }
  468. if (cur_addr < end_addr) {
  469. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  470. next_sec_addr = cur_addr + MG_MFLASH_SECTOR_SIZE;
  471. while (next_sec_addr <= end_addr) {
  472. cnt++;
  473. next_sec_addr += MG_MFLASH_SECTOR_SIZE;
  474. }
  475. if (cnt)
  476. if ((ret = mg_mflash_read_sects(buff_ptr, sect_num, cnt)) != ERROR_OK)
  477. return ret;
  478. buff_ptr += cnt * MG_MFLASH_SECTOR_SIZE;
  479. cur_addr += cnt * MG_MFLASH_SECTOR_SIZE;
  480. if (cur_addr < end_addr) {
  481. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  482. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  483. if (ret != ERROR_OK)
  484. return ret;
  485. memcpy(buff_ptr, sect_buff, end_addr - cur_addr);
  486. LOG_DEBUG("mflash: copies %u byte", (unsigned)(end_addr - cur_addr));
  487. }
  488. }
  489. return ret;
  490. }
  491. static int mg_mflash_write(uint32_t addr, uint8_t *buff, uint32_t len)
  492. {
  493. uint8_t *buff_ptr = buff;
  494. uint8_t sect_buff[MG_MFLASH_SECTOR_SIZE];
  495. uint32_t cur_addr, next_sec_addr, end_addr, cnt, sect_num;
  496. int ret = ERROR_OK;
  497. cnt = 0;
  498. cur_addr = addr;
  499. end_addr = addr + len;
  500. if (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK) {
  501. next_sec_addr = (cur_addr + MG_MFLASH_SECTOR_SIZE) & ~MG_MFLASH_SECTOR_SIZE_MASK;
  502. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  503. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  504. if (ret != ERROR_OK)
  505. return ret;
  506. if (end_addr < next_sec_addr) {
  507. memcpy(sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), buff_ptr, end_addr - cur_addr);
  508. LOG_DEBUG("mflash: copies %" PRIu32 " byte to sector offset 0x%8.8" PRIx32 "", end_addr - cur_addr, cur_addr);
  509. cur_addr = end_addr;
  510. } else {
  511. memcpy(sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), buff_ptr, next_sec_addr - cur_addr);
  512. LOG_DEBUG("mflash: copies %" PRIu32 " byte to sector offset 0x%8.8" PRIx32 "", next_sec_addr - cur_addr, cur_addr);
  513. buff_ptr += (next_sec_addr - cur_addr);
  514. cur_addr = next_sec_addr;
  515. }
  516. ret = mg_mflash_write_sects(sect_buff, sect_num, 1);
  517. if (ret != ERROR_OK)
  518. return ret;
  519. }
  520. if (cur_addr < end_addr) {
  521. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  522. next_sec_addr = cur_addr + MG_MFLASH_SECTOR_SIZE;
  523. while (next_sec_addr <= end_addr) {
  524. cnt++;
  525. next_sec_addr += MG_MFLASH_SECTOR_SIZE;
  526. }
  527. if (cnt)
  528. if ((ret = mg_mflash_write_sects(buff_ptr, sect_num, cnt)) != ERROR_OK)
  529. return ret;
  530. buff_ptr += cnt * MG_MFLASH_SECTOR_SIZE;
  531. cur_addr += cnt * MG_MFLASH_SECTOR_SIZE;
  532. if (cur_addr < end_addr) {
  533. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  534. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  535. if (ret != ERROR_OK)
  536. return ret;
  537. memcpy(sect_buff, buff_ptr, end_addr - cur_addr);
  538. LOG_DEBUG("mflash: copies %" PRIu32 " byte", end_addr - cur_addr);
  539. ret = mg_mflash_write_sects(sect_buff, sect_num, 1);
  540. }
  541. }
  542. return ret;
  543. }
  544. COMMAND_HANDLER(mg_write_cmd)
  545. {
  546. uint32_t address, cnt, res, i;
  547. uint8_t *buffer;
  548. struct fileio fileio;
  549. int ret;
  550. if (CMD_ARGC != 3) {
  551. return ERROR_COMMAND_SYNTAX_ERROR;
  552. }
  553. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
  554. ret = fileio_open(&fileio, CMD_ARGV[1], FILEIO_READ, FILEIO_BINARY);
  555. if (ret != ERROR_OK)
  556. return ret;
  557. buffer = malloc(MG_FILEIO_CHUNK);
  558. if (!buffer) {
  559. fileio_close(&fileio);
  560. return ERROR_FAIL;
  561. }
  562. cnt = fileio.size / MG_FILEIO_CHUNK;
  563. res = fileio.size % MG_FILEIO_CHUNK;
  564. struct duration bench;
  565. duration_start(&bench);
  566. size_t buf_cnt;
  567. for (i = 0; i < cnt; i++) {
  568. if ((ret = fileio_read(&fileio, MG_FILEIO_CHUNK, buffer, &buf_cnt)) !=
  569. ERROR_OK)
  570. goto mg_write_cmd_err;
  571. if ((ret = mg_mflash_write(address, buffer, MG_FILEIO_CHUNK)) != ERROR_OK)
  572. goto mg_write_cmd_err;
  573. address += MG_FILEIO_CHUNK;
  574. }
  575. if (res) {
  576. if ((ret = fileio_read(&fileio, res, buffer, &buf_cnt)) != ERROR_OK)
  577. goto mg_write_cmd_err;
  578. if ((ret = mg_mflash_write(address, buffer, res)) != ERROR_OK)
  579. goto mg_write_cmd_err;
  580. }
  581. if (duration_measure(&bench) == ERROR_OK)
  582. {
  583. command_print(CMD_CTX, "wrote %zu byte from file %s "
  584. "in %fs (%0.3f kB/s)", fileio.size, CMD_ARGV[1],
  585. duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
  586. }
  587. free(buffer);
  588. fileio_close(&fileio);
  589. return ERROR_OK;
  590. mg_write_cmd_err:
  591. free(buffer);
  592. fileio_close(&fileio);
  593. return ret;
  594. }
  595. COMMAND_HANDLER(mg_dump_cmd)
  596. {
  597. uint32_t address, size, cnt, res, i;
  598. uint8_t *buffer;
  599. struct fileio fileio;
  600. int ret;
  601. if (CMD_ARGC != 4) {
  602. return ERROR_COMMAND_SYNTAX_ERROR;
  603. }
  604. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
  605. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], size);
  606. ret = fileio_open(&fileio, CMD_ARGV[1], FILEIO_WRITE, FILEIO_BINARY);
  607. if (ret != ERROR_OK)
  608. return ret;
  609. buffer = malloc(MG_FILEIO_CHUNK);
  610. if (!buffer) {
  611. fileio_close(&fileio);
  612. return ERROR_FAIL;
  613. }
  614. cnt = size / MG_FILEIO_CHUNK;
  615. res = size % MG_FILEIO_CHUNK;
  616. struct duration bench;
  617. duration_start(&bench);
  618. size_t size_written;
  619. for (i = 0; i < cnt; i++) {
  620. if ((ret = mg_mflash_read(address, buffer, MG_FILEIO_CHUNK)) != ERROR_OK)
  621. goto mg_dump_cmd_err;
  622. if ((ret = fileio_write(&fileio, MG_FILEIO_CHUNK, buffer, &size_written))
  623. != ERROR_OK)
  624. goto mg_dump_cmd_err;
  625. address += MG_FILEIO_CHUNK;
  626. }
  627. if (res) {
  628. if ((ret = mg_mflash_read(address, buffer, res)) != ERROR_OK)
  629. goto mg_dump_cmd_err;
  630. if ((ret = fileio_write(&fileio, res, buffer, &size_written)) != ERROR_OK)
  631. goto mg_dump_cmd_err;
  632. }
  633. if (duration_measure(&bench) == ERROR_OK)
  634. {
  635. command_print(CMD_CTX, "dump image (address 0x%8.8" PRIx32 " "
  636. "size %" PRIu32 ") to file %s in %fs (%0.3f kB/s)",
  637. address, size, CMD_ARGV[1],
  638. duration_elapsed(&bench), duration_kbps(&bench, size));
  639. }
  640. free(buffer);
  641. fileio_close(&fileio);
  642. return ERROR_OK;
  643. mg_dump_cmd_err:
  644. free(buffer);
  645. fileio_close(&fileio);
  646. return ret;
  647. }
  648. static int mg_set_feature(mg_feature_id feature, mg_feature_val config)
  649. {
  650. struct target *target = mflash_bank->target;
  651. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  652. int ret;
  653. if ((ret = mg_dsk_wait(mg_io_wait_rdy_noerr, MG_OEM_DISK_WAIT_TIME_NORMAL))
  654. != ERROR_OK)
  655. return ret;
  656. ret = target_write_u8(target, mg_task_reg + MG_REG_FEATURE, feature);
  657. ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_CNT, config);
  658. ret |= target_write_u8(target, mg_task_reg + MG_REG_COMMAND,
  659. mg_io_cmd_set_feature);
  660. return ret;
  661. }
  662. static int mg_is_valid_pll(double XIN, int N, double CLK_OUT, int NO)
  663. {
  664. double v1 = XIN / N;
  665. double v2 = CLK_OUT * NO;
  666. if (v1 <1000000 || v1 > 15000000 || v2 < 100000000 || v2 > 500000000)
  667. return ERROR_MG_INVALID_PLL;
  668. return ERROR_OK;
  669. }
  670. static int mg_pll_get_M(unsigned short feedback_div)
  671. {
  672. int i, M;
  673. for (i = 1, M = 0; i < 512; i <<= 1, feedback_div >>= 1)
  674. M += (feedback_div & 1) * i;
  675. return M + 2;
  676. }
  677. static int mg_pll_get_N(unsigned char input_div)
  678. {
  679. int i, N;
  680. for (i = 1, N = 0; i < 32; i <<= 1, input_div >>= 1)
  681. N += (input_div & 1) * i;
  682. return N + 2;
  683. }
  684. static int mg_pll_get_NO(unsigned char output_div)
  685. {
  686. int i, NO;
  687. for (i = 0, NO = 1; i < 2; ++i, output_div >>= 1)
  688. if (output_div & 1)
  689. NO = NO << 1;
  690. return NO;
  691. }
  692. static double mg_do_calc_pll(double XIN, mg_pll_t * p_pll_val, int is_approximate)
  693. {
  694. unsigned short i;
  695. unsigned char j, k;
  696. int M, N, NO;
  697. double CLK_OUT;
  698. double DIV = 1;
  699. double ROUND = 0;
  700. if (is_approximate) {
  701. DIV = 1000000;
  702. ROUND = 500000;
  703. }
  704. for (i = 0; i < MG_PLL_MAX_FEEDBACKDIV_VAL ; ++i) {
  705. M = mg_pll_get_M(i);
  706. for (j = 0; j < MG_PLL_MAX_INPUTDIV_VAL ; ++j) {
  707. N = mg_pll_get_N(j);
  708. for (k = 0; k < MG_PLL_MAX_OUTPUTDIV_VAL ; ++k) {
  709. NO = mg_pll_get_NO(k);
  710. CLK_OUT = XIN * ((double)M / N) / NO;
  711. if ((int)((CLK_OUT + ROUND) / DIV)
  712. == (int)(MG_PLL_CLK_OUT / DIV)) {
  713. if (mg_is_valid_pll(XIN, N, CLK_OUT, NO) == ERROR_OK)
  714. {
  715. p_pll_val->lock_cyc = (int)(XIN * MG_PLL_STD_LOCKCYCLE / MG_PLL_STD_INPUTCLK);
  716. p_pll_val->feedback_div = i;
  717. p_pll_val->input_div = j;
  718. p_pll_val->output_div = k;
  719. return CLK_OUT;
  720. }
  721. }
  722. }
  723. }
  724. }
  725. return 0;
  726. }
  727. static double mg_calc_pll(double XIN, mg_pll_t *p_pll_val)
  728. {
  729. double CLK_OUT;
  730. CLK_OUT = mg_do_calc_pll(XIN, p_pll_val, 0);
  731. if (!CLK_OUT)
  732. return mg_do_calc_pll(XIN, p_pll_val, 1);
  733. else
  734. return CLK_OUT;
  735. }
  736. static int mg_verify_interface(void)
  737. {
  738. uint16_t buff[MG_MFLASH_SECTOR_SIZE >> 1];
  739. uint16_t i, j;
  740. uint32_t address = mflash_bank->base + MG_BUFFER_OFFSET;
  741. struct target *target = mflash_bank->target;
  742. int ret;
  743. for (j = 0; j < 10; j++) {
  744. for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++)
  745. buff[i] = i;
  746. ret = target_write_memory(target, address, 2,
  747. MG_MFLASH_SECTOR_SIZE / 2, (uint8_t *)buff);
  748. if (ret != ERROR_OK)
  749. return ret;
  750. memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE);
  751. ret = target_read_memory(target, address, 2,
  752. MG_MFLASH_SECTOR_SIZE / 2, (uint8_t *)buff);
  753. if (ret != ERROR_OK)
  754. return ret;
  755. for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++) {
  756. if (buff[i] != i) {
  757. LOG_ERROR("mflash: verify interface fail");
  758. return ERROR_MG_INTERFACE;
  759. }
  760. }
  761. }
  762. LOG_INFO("mflash: verify interface ok");
  763. return ret;
  764. }
  765. static const char g_strSEG_SerialNum[20] = {
  766. 'G','m','n','i','-','e','e','S','g','a','e','l',
  767. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  768. };
  769. static const char g_strSEG_FWRev[8] = {
  770. 'F','X','L','T','2','v','0','.'
  771. };
  772. static const char g_strSEG_ModelNum[40] = {
  773. 'F','X','A','L','H','S','2',0x20,'0','0','s','7',
  774. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  775. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  776. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  777. };
  778. static void mg_gen_ataid(mg_io_type_drv_info *pSegIdDrvInfo)
  779. {
  780. /* b15 is ATA device(0) , b7 is Removable Media Device */
  781. pSegIdDrvInfo->general_configuration = 0x045A;
  782. /* 128MB : Cylinder=> 977 , Heads=> 8 , Sectors=> 32
  783. * 256MB : Cylinder=> 980 , Heads=> 16 , Sectors=> 32
  784. * 384MB : Cylinder=> 745 , Heads=> 16 , Sectors=> 63
  785. */
  786. pSegIdDrvInfo->number_of_cylinders = 0x02E9;
  787. pSegIdDrvInfo->reserved1 = 0x0;
  788. pSegIdDrvInfo->number_of_heads = 0x10;
  789. pSegIdDrvInfo->unformatted_bytes_per_track = 0x0;
  790. pSegIdDrvInfo->unformatted_bytes_per_sector = 0x0;
  791. pSegIdDrvInfo->sectors_per_track = 0x3F;
  792. pSegIdDrvInfo->vendor_unique1[0] = 0x000B;
  793. pSegIdDrvInfo->vendor_unique1[1] = 0x7570;
  794. pSegIdDrvInfo->vendor_unique1[2] = 0x8888;
  795. memcpy(pSegIdDrvInfo->serial_number, (void *)g_strSEG_SerialNum,20);
  796. /* 0x2 : dual buffer */
  797. pSegIdDrvInfo->buffer_type = 0x2;
  798. /* buffer size : 2KB */
  799. pSegIdDrvInfo->buffer_sector_size = 0x800;
  800. pSegIdDrvInfo->number_of_ecc_bytes = 0;
  801. memcpy(pSegIdDrvInfo->firmware_revision, (void *)g_strSEG_FWRev,8);
  802. memcpy(pSegIdDrvInfo->model_number, (void *)g_strSEG_ModelNum,40);
  803. pSegIdDrvInfo->maximum_block_transfer = 0x4;
  804. pSegIdDrvInfo->vendor_unique2 = 0x0;
  805. pSegIdDrvInfo->dword_io = 0x00;
  806. /* b11 : IORDY support(PIO Mode 4), b10 : Disable/Enbale IORDY
  807. * b9 : LBA support, b8 : DMA mode support
  808. */
  809. pSegIdDrvInfo->capabilities = 0x1 << 9;
  810. pSegIdDrvInfo->reserved2 = 0x4000;
  811. pSegIdDrvInfo->vendor_unique3 = 0x00;
  812. /* PIOMode-2 support */
  813. pSegIdDrvInfo->pio_cycle_timing_mode = 0x02;
  814. pSegIdDrvInfo->vendor_unique4 = 0x00;
  815. /* MultiWord-2 support */
  816. pSegIdDrvInfo->dma_cycle_timing_mode = 0x00;
  817. /* b1 : word64~70 is valid
  818. * b0 : word54~58 are valid and reflect the current numofcyls,heads,sectors
  819. * b2 : If device supports Ultra DMA , set to one to vaildate word88
  820. */
  821. pSegIdDrvInfo->translation_fields_valid = (0x1 << 1) | (0x1 << 0);
  822. pSegIdDrvInfo->number_of_current_cylinders = 0x02E9;
  823. pSegIdDrvInfo->number_of_current_heads = 0x10;
  824. pSegIdDrvInfo->current_sectors_per_track = 0x3F;
  825. pSegIdDrvInfo->current_sector_capacity_lo = 0x7570;
  826. pSegIdDrvInfo->current_sector_capacity_hi = 0x000B;
  827. pSegIdDrvInfo->multi_sector_count = 0x04;
  828. /* b8 : Multiple secotr setting valid , b[7:0] num of secotrs per block */
  829. pSegIdDrvInfo->multi_sector_setting_valid = 0x01;
  830. pSegIdDrvInfo->total_user_addressable_sectors_lo = 0x7570;
  831. pSegIdDrvInfo->total_user_addressable_sectors_hi = 0x000B;
  832. pSegIdDrvInfo->single_dma_modes_supported = 0x00;
  833. pSegIdDrvInfo->single_dma_transfer_active = 0x00;
  834. /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
  835. pSegIdDrvInfo->multi_dma_modes_supported = (0x1 << 0);
  836. /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
  837. pSegIdDrvInfo->multi_dma_transfer_active = (0x1 << 0);
  838. /* b0 : PIO Mode-3 support, b1 : PIO Mode-4 support */
  839. pSegIdDrvInfo->adv_pio_mode = 0x00;
  840. /* 480(0x1E0)nsec for Multi-word DMA mode0
  841. * 150(0x96) nsec for Multi-word DMA mode1
  842. * 120(0x78) nsec for Multi-word DMA mode2
  843. */
  844. pSegIdDrvInfo->min_dma_cyc = 0x1E0;
  845. pSegIdDrvInfo->recommend_dma_cyc = 0x1E0;
  846. pSegIdDrvInfo->min_pio_cyc_no_iordy = 0x1E0;
  847. pSegIdDrvInfo->min_pio_cyc_with_iordy = 0x1E0;
  848. memset((void *)pSegIdDrvInfo->reserved3, 0x00, 22);
  849. /* b7 : ATA/ATAPI-7 ,b6 : ATA/ATAPI-6 ,b5 : ATA/ATAPI-5,b4 : ATA/ATAPI-4 */
  850. pSegIdDrvInfo->major_ver_num = 0x7E;
  851. /* 0x1C : ATA/ATAPI-6 T13 1532D revision1 */
  852. pSegIdDrvInfo->minor_ver_num = 0x19;
  853. /* NOP/READ BUFFER/WRITE BUFFER/Power management feature set support */
  854. pSegIdDrvInfo->feature_cmd_set_suprt0 = 0x7068;
  855. /* Features/command set is valid/Advanced Pwr management/CFA feature set
  856. * not support
  857. */
  858. pSegIdDrvInfo->feature_cmd_set_suprt1 = 0x400C;
  859. pSegIdDrvInfo->feature_cmd_set_suprt2 = 0x4000;
  860. /* READ/WRITE BUFFER/PWR Management enable */
  861. pSegIdDrvInfo->feature_cmd_set_en0 = 0x7000;
  862. /* CFA feature is disabled / Advancde power management disable */
  863. pSegIdDrvInfo->feature_cmd_set_en1 = 0x0;
  864. pSegIdDrvInfo->feature_cmd_set_en2 = 0x4000;
  865. pSegIdDrvInfo->reserved4 = 0x0;
  866. /* 0x1 * 2minutes */
  867. pSegIdDrvInfo->req_time_for_security_er_done = 0x19;
  868. pSegIdDrvInfo->req_time_for_enhan_security_er_done = 0x19;
  869. /* Advanced power management level 1 */
  870. pSegIdDrvInfo->adv_pwr_mgm_lvl_val = 0x0;
  871. pSegIdDrvInfo->reserved5 = 0x0;
  872. memset((void *)pSegIdDrvInfo->reserved6, 0x00, 68);
  873. /* Security mode feature is disabled */
  874. pSegIdDrvInfo->security_stas = 0x0;
  875. memset((void *)pSegIdDrvInfo->vendor_uniq_bytes, 0x00, 62);
  876. /* CFA power mode 1 support in maximum 200mA */
  877. pSegIdDrvInfo->cfa_pwr_mode = 0x0100;
  878. memset((void *)pSegIdDrvInfo->reserved7, 0x00, 190);
  879. }
  880. static int mg_storage_config(void)
  881. {
  882. uint8_t buff[512];
  883. int ret;
  884. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  885. != ERROR_OK)
  886. return ret;
  887. mg_gen_ataid((mg_io_type_drv_info *)buff);
  888. if ((ret = mg_mflash_do_write_sects(buff, 0, 1, mg_vcmd_update_stgdrvinfo))
  889. != ERROR_OK)
  890. return ret;
  891. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  892. != ERROR_OK)
  893. return ret;
  894. LOG_INFO("mflash: storage config ok");
  895. return ret;
  896. }
  897. static int mg_boot_config(void)
  898. {
  899. uint8_t buff[512];
  900. int ret;
  901. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  902. != ERROR_OK)
  903. return ret;
  904. memset(buff, 0xff, 512);
  905. buff[0] = mg_op_mode_snd; /* operation mode */
  906. buff[1] = MG_UNLOCK_OTP_AREA;
  907. buff[2] = 4; /* boot size */
  908. *((uint32_t *)(buff + 4)) = 0; /* XIP size */
  909. if ((ret = mg_mflash_do_write_sects(buff, 0, 1, mg_vcmd_update_xipinfo))
  910. != ERROR_OK)
  911. return ret;
  912. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  913. != ERROR_OK)
  914. return ret;
  915. LOG_INFO("mflash: boot config ok");
  916. return ret;
  917. }
  918. static int mg_set_pll(mg_pll_t *pll)
  919. {
  920. uint8_t buff[512];
  921. int ret;
  922. memset(buff, 0xff, 512);
  923. /* PLL Lock cycle and Feedback 9bit Divider */
  924. memcpy(buff, &pll->lock_cyc, sizeof(uint32_t));
  925. memcpy(buff + 4, &pll->feedback_div, sizeof(uint16_t));
  926. buff[6] = pll->input_div; /* PLL Input 5bit Divider */
  927. buff[7] = pll->output_div; /* PLL Output Divider */
  928. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  929. != ERROR_OK)
  930. return ret;
  931. if ((ret = mg_mflash_do_write_sects(buff, 0, 1, mg_vcmd_wr_pll))
  932. != ERROR_OK)
  933. return ret;
  934. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  935. != ERROR_OK)
  936. return ret;
  937. LOG_INFO("mflash: set pll ok");
  938. return ret;
  939. }
  940. static int mg_erase_nand(void)
  941. {
  942. int ret;
  943. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  944. != ERROR_OK)
  945. return ret;
  946. if ((ret = mg_mflash_do_write_sects(NULL, 0, 0, mg_vcmd_purge_nand))
  947. != ERROR_OK)
  948. return ret;
  949. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  950. != ERROR_OK)
  951. return ret;
  952. LOG_INFO("mflash: erase nand ok");
  953. return ret;
  954. }
  955. COMMAND_HANDLER(mg_config_cmd)
  956. {
  957. double fin, fout;
  958. mg_pll_t pll;
  959. int ret;
  960. if ((ret = mg_verify_interface()) != ERROR_OK)
  961. return ret;
  962. if ((ret = mg_mflash_rst()) != ERROR_OK)
  963. return ret;
  964. switch (CMD_ARGC) {
  965. case 2:
  966. if (!strcmp(CMD_ARGV[1], "boot"))
  967. return mg_boot_config();
  968. else if (!strcmp(CMD_ARGV[1], "storage"))
  969. return mg_storage_config();
  970. else
  971. return ERROR_COMMAND_NOTFOUND;
  972. break;
  973. case 3:
  974. if (!strcmp(CMD_ARGV[1], "pll")) {
  975. unsigned long freq;
  976. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], freq);
  977. fin = freq;
  978. if (fin > MG_PLL_CLK_OUT) {
  979. LOG_ERROR("mflash: input freq. is too large");
  980. return ERROR_MG_INVALID_OSC;
  981. }
  982. fout = mg_calc_pll(fin, &pll);
  983. if (!fout) {
  984. LOG_ERROR("mflash: cannot generate valid pll");
  985. return ERROR_MG_INVALID_PLL;
  986. }
  987. LOG_INFO("mflash: Fout=%" PRIu32 " Hz, feedback=%u,"
  988. "indiv=%u, outdiv=%u, lock=%u",
  989. (uint32_t)fout, pll.feedback_div,
  990. pll.input_div, pll.output_div,
  991. pll.lock_cyc);
  992. if ((ret = mg_erase_nand()) != ERROR_OK)
  993. return ret;
  994. return mg_set_pll(&pll);
  995. } else
  996. return ERROR_COMMAND_NOTFOUND;
  997. break;
  998. default:
  999. return ERROR_COMMAND_SYNTAX_ERROR;
  1000. }
  1001. }
  1002. static const struct command_registration mflash_exec_command_handlers[] = {
  1003. {
  1004. .name = "probe",
  1005. .handler = &mg_probe_cmd,
  1006. .mode = COMMAND_EXEC,
  1007. .help = "Detect bank configuration information",
  1008. },
  1009. {
  1010. .name = "write",
  1011. .handler = &mg_write_cmd,
  1012. .mode = COMMAND_EXEC,
  1013. .usage = "<num> <file> <address>",
  1014. .help = "Write a file at the specified address",
  1015. },
  1016. {
  1017. .name = "dump",
  1018. .handler = &mg_dump_cmd,
  1019. .mode = COMMAND_EXEC,
  1020. .usage = "<num> <file> <address> <size>",
  1021. .help = "Dump to a file from the specified address",
  1022. },
  1023. {
  1024. .name = "config",
  1025. .handler = &mg_config_cmd,
  1026. .mode = COMMAND_EXEC,
  1027. .usage = "<num> <stage>",
  1028. .help = "Dump to a file from the specified address",
  1029. },
  1030. COMMAND_REGISTRATION_DONE
  1031. };
  1032. int mflash_init_drivers(struct command_context *cmd_ctx)
  1033. {
  1034. if (!mflash_bank)
  1035. return ERROR_OK;
  1036. return register_commands(cmd_ctx, NULL, mflash_exec_command_handlers);
  1037. }
  1038. COMMAND_HANDLER(handle_mflash_init_command)
  1039. {
  1040. if (CMD_ARGC != 0)
  1041. return ERROR_COMMAND_SYNTAX_ERROR;
  1042. static bool mflash_initialized = false;
  1043. if (mflash_initialized)
  1044. {
  1045. LOG_INFO("'mflash init' has already been called");
  1046. return ERROR_OK;
  1047. }
  1048. mflash_initialized = true;
  1049. LOG_DEBUG("Initializing mflash devices...");
  1050. return mflash_init_drivers(CMD_CTX);
  1051. }
  1052. COMMAND_HANDLER(mg_bank_cmd)
  1053. {
  1054. struct target *target;
  1055. int i;
  1056. if (CMD_ARGC < 4)
  1057. {
  1058. return ERROR_COMMAND_SYNTAX_ERROR;
  1059. }
  1060. if ((target = get_target(CMD_ARGV[3])) == NULL)
  1061. {
  1062. LOG_ERROR("target '%s' not defined", CMD_ARGV[3]);
  1063. return ERROR_FAIL;
  1064. }
  1065. mflash_bank = calloc(sizeof(struct mflash_bank), 1);
  1066. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], mflash_bank->base);
  1067. /// @todo Verify how this parsing should work, then document it.
  1068. char *str;
  1069. mflash_bank->rst_pin.num = strtoul(CMD_ARGV[2], &str, 0);
  1070. if (*str)
  1071. mflash_bank->rst_pin.port[0] = (uint16_t)tolower(str[0]);
  1072. mflash_bank->target = target;
  1073. for (i = 0; mflash_gpio[i] ; i++) {
  1074. if (! strcmp(mflash_gpio[i]->name, CMD_ARGV[0])) {
  1075. mflash_bank->gpio_drv = mflash_gpio[i];
  1076. }
  1077. }
  1078. if (! mflash_bank->gpio_drv) {
  1079. LOG_ERROR("%s is unsupported soc", CMD_ARGV[0]);
  1080. return ERROR_MG_UNSUPPORTED_SOC;
  1081. }
  1082. return ERROR_OK;
  1083. }
  1084. static const struct command_registration mflash_config_command_handlers[] = {
  1085. {
  1086. .name = "bank",
  1087. .handler = &mg_bank_cmd,
  1088. .mode = COMMAND_CONFIG,
  1089. .help = "configure a mflash device bank",
  1090. .usage = "<soc> <base> <RST pin> <target #>",
  1091. },
  1092. {
  1093. .name = "init",
  1094. .mode = COMMAND_CONFIG,
  1095. .handler = &handle_mflash_init_command,
  1096. .help = "initialize mflash devices",
  1097. },
  1098. COMMAND_REGISTRATION_DONE
  1099. };
  1100. static const struct command_registration mflash_command_handler[] = {
  1101. {
  1102. .name = "mflash",
  1103. .mode = COMMAND_ANY,
  1104. .help = "mflash command group",
  1105. .chain = mflash_config_command_handlers,
  1106. },
  1107. COMMAND_REGISTRATION_DONE
  1108. };
  1109. int mflash_register_commands(struct command_context *cmd_ctx)
  1110. {
  1111. return register_commands(cmd_ctx, NULL, mflash_command_handler);
  1112. }