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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Partially based on drivers/mtd/nand_ids.c from Linux. *
  6. * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "replacements.h"
  27. #include "log.h"
  28. #include <stdlib.h>
  29. #include <string.h>
  30. #include <inttypes.h>
  31. #include <errno.h>
  32. #include "nand.h"
  33. #include "flash.h"
  34. #include "time_support.h"
  35. #include "fileio.h"
  36. #include "image.h"
  37. int nand_register_commands(struct command_context_s *cmd_ctx);
  38. int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39. int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40. int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41. int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42. int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43. int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44. int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45. int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46. int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47. int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  48. int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  49. int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
  50. int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  51. int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  52. /* NAND flash controller
  53. */
  54. extern nand_flash_controller_t lpc3180_nand_controller;
  55. extern nand_flash_controller_t s3c2410_nand_controller;
  56. extern nand_flash_controller_t s3c2412_nand_controller;
  57. extern nand_flash_controller_t s3c2440_nand_controller;
  58. extern nand_flash_controller_t s3c2443_nand_controller;
  59. /* extern nand_flash_controller_t boundary_scan_nand_controller; */
  60. nand_flash_controller_t *nand_flash_controllers[] =
  61. {
  62. &lpc3180_nand_controller,
  63. &s3c2410_nand_controller,
  64. &s3c2412_nand_controller,
  65. &s3c2440_nand_controller,
  66. &s3c2443_nand_controller,
  67. /* &boundary_scan_nand_controller, */
  68. NULL
  69. };
  70. /* configured NAND devices and NAND Flash command handler */
  71. nand_device_t *nand_devices = NULL;
  72. static command_t *nand_cmd;
  73. /* Chip ID list
  74. *
  75. * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
  76. * options
  77. *
  78. * Pagesize; 0, 256, 512
  79. * 0 get this information from the extended chip ID
  80. * 256 256 Byte page size
  81. * 512 512 Byte page size
  82. */
  83. nand_info_t nand_flash_ids[] =
  84. {
  85. {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
  86. {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
  87. {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
  88. {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
  89. {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
  90. {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
  91. {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
  92. {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
  93. {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
  94. {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
  95. {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
  96. {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
  97. {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
  98. {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
  99. {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
  100. {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
  101. {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
  102. {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
  103. {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
  104. {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
  105. {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
  106. {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
  107. {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
  108. {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
  109. {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
  110. {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
  111. {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
  112. {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
  113. {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
  114. {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  115. {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  116. {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  117. {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  118. {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
  119. {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
  120. {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
  121. {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
  122. {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
  123. {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
  124. {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
  125. {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
  126. {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
  127. {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
  128. {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
  129. {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
  130. {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
  131. {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
  132. {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
  133. {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
  134. {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
  135. {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
  136. {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
  137. {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
  138. {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
  139. {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
  140. {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
  141. {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
  142. {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
  143. {NULL, 0,}
  144. };
  145. /* Manufacturer ID list
  146. */
  147. nand_manufacturer_t nand_manuf_ids[] =
  148. {
  149. {0x0, "unknown"},
  150. {NAND_MFR_TOSHIBA, "Toshiba"},
  151. {NAND_MFR_SAMSUNG, "Samsung"},
  152. {NAND_MFR_FUJITSU, "Fujitsu"},
  153. {NAND_MFR_NATIONAL, "National"},
  154. {NAND_MFR_RENESAS, "Renesas"},
  155. {NAND_MFR_STMICRO, "ST Micro"},
  156. {NAND_MFR_HYNIX, "Hynix"},
  157. {0x0, NULL},
  158. };
  159. /* nand device <nand_controller> [controller options]
  160. */
  161. int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  162. {
  163. int i;
  164. int retval;
  165. if (argc < 1)
  166. {
  167. LOG_WARNING("incomplete flash device nand configuration");
  168. return ERROR_FLASH_BANK_INVALID;
  169. }
  170. for (i = 0; nand_flash_controllers[i]; i++)
  171. {
  172. nand_device_t *p, *c;
  173. if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
  174. {
  175. /* register flash specific commands */
  176. if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
  177. {
  178. LOG_ERROR("couldn't register '%s' commands", args[0]);
  179. exit(-1);
  180. }
  181. c = malloc(sizeof(nand_device_t));
  182. c->controller = nand_flash_controllers[i];
  183. c->controller_priv = NULL;
  184. c->manufacturer = NULL;
  185. c->device = NULL;
  186. c->bus_width = 0;
  187. c->address_cycles = 0;
  188. c->page_size = 0;
  189. c->use_raw = 0;
  190. c->next = NULL;
  191. if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
  192. {
  193. LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
  194. free(c);
  195. return ERROR_OK;
  196. }
  197. /* put NAND device in linked list */
  198. if (nand_devices)
  199. {
  200. /* find last flash device */
  201. for (p = nand_devices; p && p->next; p = p->next);
  202. if (p)
  203. p->next = c;
  204. }
  205. else
  206. {
  207. nand_devices = c;
  208. }
  209. return ERROR_OK;
  210. }
  211. }
  212. /* no valid NAND controller was found (i.e. the configuration option,
  213. * didn't match one of the compiled-in controllers)
  214. */
  215. LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
  216. LOG_ERROR("compiled-in NAND flash controllers:");
  217. for (i = 0; nand_flash_controllers[i]; i++)
  218. {
  219. LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
  220. }
  221. return ERROR_OK;
  222. }
  223. int nand_register_commands(struct command_context_s *cmd_ctx)
  224. {
  225. nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
  226. register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
  227. return ERROR_OK;
  228. }
  229. int nand_init(struct command_context_s *cmd_ctx)
  230. {
  231. if (nand_devices)
  232. {
  233. register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
  234. "list configured NAND flash devices");
  235. register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
  236. "print info about NAND flash device <num>");
  237. register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
  238. "identify NAND flash device <num>");
  239. register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
  240. "check NAND flash device <num> for bad blocks [<first> <last>]");
  241. register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
  242. "erase blocks on NAND flash device <num> <first> <last>");
  243. register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
  244. "copy from NAND flash device <num> <offset> <length> <ram-address>");
  245. register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
  246. "dump from NAND flash device <num> <filename> <offset> <size> [options]");
  247. register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
  248. "write to NAND flash device <num> <filename> <offset> [options]");
  249. register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
  250. "raw access to NAND flash device <num> ['enable'|'disable']");
  251. }
  252. return ERROR_OK;
  253. }
  254. nand_device_t *get_nand_device_by_num(int num)
  255. {
  256. nand_device_t *p;
  257. int i = 0;
  258. for (p = nand_devices; p; p = p->next)
  259. {
  260. if (i++ == num)
  261. {
  262. return p;
  263. }
  264. }
  265. return NULL;
  266. }
  267. int nand_build_bbt(struct nand_device_s *device, int first, int last)
  268. {
  269. u32 page = 0x0;
  270. int i;
  271. u8 *oob;
  272. oob = malloc(6);
  273. if ((first < 0) || (first >= device->num_blocks))
  274. first = 0;
  275. if ((last >= device->num_blocks) || (last == -1))
  276. last = device->num_blocks - 1;
  277. for (i = first; i < last; i++)
  278. {
  279. nand_read_page(device, page, NULL, 0, oob, 6);
  280. if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
  281. || (((device->page_size == 512) && (oob[5] != 0xff)) ||
  282. ((device->page_size == 2048) && (oob[0] != 0xff))))
  283. {
  284. LOG_WARNING("invalid block: %i", i);
  285. device->blocks[i].is_bad = 1;
  286. }
  287. else
  288. {
  289. device->blocks[i].is_bad = 0;
  290. }
  291. page += (device->erase_size / device->page_size);
  292. }
  293. return ERROR_OK;
  294. }
  295. int nand_read_status(struct nand_device_s *device, u8 *status)
  296. {
  297. if (!device->device)
  298. return ERROR_NAND_DEVICE_NOT_PROBED;
  299. /* Send read status command */
  300. device->controller->command(device, NAND_CMD_STATUS);
  301. usleep(1000);
  302. /* read status */
  303. if (device->device->options & NAND_BUSWIDTH_16)
  304. {
  305. u16 data;
  306. device->controller->read_data(device, &data);
  307. *status = data & 0xff;
  308. }
  309. else
  310. {
  311. device->controller->read_data(device, status);
  312. }
  313. return ERROR_OK;
  314. }
  315. int nand_probe(struct nand_device_s *device)
  316. {
  317. u8 manufacturer_id, device_id;
  318. u8 id_buff[5];
  319. int retval;
  320. int i;
  321. /* clear device data */
  322. device->device = NULL;
  323. device->manufacturer = NULL;
  324. /* clear device parameters */
  325. device->bus_width = 0;
  326. device->address_cycles = 0;
  327. device->page_size = 0;
  328. device->erase_size = 0;
  329. /* initialize controller (device parameters are zero, use controller default) */
  330. if ((retval = device->controller->init(device) != ERROR_OK))
  331. {
  332. switch (retval)
  333. {
  334. case ERROR_NAND_OPERATION_FAILED:
  335. LOG_DEBUG("controller initialization failed");
  336. return ERROR_NAND_OPERATION_FAILED;
  337. case ERROR_NAND_OPERATION_NOT_SUPPORTED:
  338. LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
  339. return ERROR_NAND_OPERATION_FAILED;
  340. default:
  341. LOG_ERROR("BUG: unknown controller initialization failure");
  342. return ERROR_NAND_OPERATION_FAILED;
  343. }
  344. }
  345. device->controller->command(device, NAND_CMD_RESET);
  346. device->controller->reset(device);
  347. device->controller->command(device, NAND_CMD_READID);
  348. device->controller->address(device, 0x0);
  349. if (device->bus_width == 8)
  350. {
  351. device->controller->read_data(device, &manufacturer_id);
  352. device->controller->read_data(device, &device_id);
  353. }
  354. else
  355. {
  356. u16 data_buf;
  357. device->controller->read_data(device, &data_buf);
  358. manufacturer_id = data_buf & 0xff;
  359. device->controller->read_data(device, &data_buf);
  360. device_id = data_buf & 0xff;
  361. }
  362. for (i = 0; nand_flash_ids[i].name; i++)
  363. {
  364. if (nand_flash_ids[i].id == device_id)
  365. {
  366. device->device = &nand_flash_ids[i];
  367. break;
  368. }
  369. }
  370. for (i = 0; nand_manuf_ids[i].name; i++)
  371. {
  372. if (nand_manuf_ids[i].id == manufacturer_id)
  373. {
  374. device->manufacturer = &nand_manuf_ids[i];
  375. break;
  376. }
  377. }
  378. if (!device->manufacturer)
  379. {
  380. device->manufacturer = &nand_manuf_ids[0];
  381. device->manufacturer->id = manufacturer_id;
  382. }
  383. if (!device->device)
  384. {
  385. LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
  386. manufacturer_id, device_id);
  387. return ERROR_NAND_OPERATION_FAILED;
  388. }
  389. LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
  390. /* initialize device parameters */
  391. /* bus width */
  392. if (device->device->options & NAND_BUSWIDTH_16)
  393. device->bus_width = 16;
  394. else
  395. device->bus_width = 8;
  396. /* Do we need extended device probe information? */
  397. if (device->device->page_size == 0 ||
  398. device->device->erase_size == 0)
  399. {
  400. if (device->bus_width == 8)
  401. {
  402. device->controller->read_data(device, id_buff+3);
  403. device->controller->read_data(device, id_buff+4);
  404. device->controller->read_data(device, id_buff+5);
  405. }
  406. else
  407. {
  408. u16 data_buf;
  409. device->controller->read_data(device, &data_buf);
  410. id_buff[3] = data_buf;
  411. device->controller->read_data(device, &data_buf);
  412. id_buff[4] = data_buf;
  413. device->controller->read_data(device, &data_buf);
  414. id_buff[5] = data_buf >> 8;
  415. }
  416. }
  417. /* page size */
  418. if (device->device->page_size == 0)
  419. {
  420. device->page_size = 1 << (10 + (id_buff[4] & 3));
  421. }
  422. else if (device->device->page_size == 256)
  423. {
  424. LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
  425. return ERROR_NAND_OPERATION_FAILED;
  426. }
  427. else
  428. {
  429. device->page_size = device->device->page_size;
  430. }
  431. /* number of address cycles */
  432. if (device->page_size <= 512)
  433. {
  434. /* small page devices */
  435. if (device->device->chip_size <= 32)
  436. device->address_cycles = 3;
  437. else if (device->device->chip_size <= 8*1024)
  438. device->address_cycles = 4;
  439. else
  440. {
  441. LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
  442. device->address_cycles = 5;
  443. }
  444. }
  445. else
  446. {
  447. /* large page devices */
  448. if (device->device->chip_size <= 128)
  449. device->address_cycles = 4;
  450. else if (device->device->chip_size <= 32*1024)
  451. device->address_cycles = 5;
  452. else
  453. {
  454. LOG_ERROR("BUG: small page NAND device with more than 32 GiB encountered");
  455. device->address_cycles = 6;
  456. }
  457. }
  458. /* erase size */
  459. if (device->device->erase_size == 0)
  460. {
  461. switch ((id_buff[4] >> 4) & 3) {
  462. case 0:
  463. device->erase_size = 64 << 10;
  464. break;
  465. case 1:
  466. device->erase_size = 128 << 10;
  467. break;
  468. case 2:
  469. device->erase_size = 256 << 10;
  470. break;
  471. case 3:
  472. device->erase_size =512 << 10;
  473. break;
  474. }
  475. }
  476. else
  477. {
  478. device->erase_size = device->device->erase_size;
  479. }
  480. /* initialize controller, but leave parameters at the controllers default */
  481. if ((retval = device->controller->init(device) != ERROR_OK))
  482. {
  483. switch (retval)
  484. {
  485. case ERROR_NAND_OPERATION_FAILED:
  486. LOG_DEBUG("controller initialization failed");
  487. return ERROR_NAND_OPERATION_FAILED;
  488. case ERROR_NAND_OPERATION_NOT_SUPPORTED:
  489. LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
  490. device->bus_width, device->address_cycles, device->page_size);
  491. return ERROR_NAND_OPERATION_FAILED;
  492. default:
  493. LOG_ERROR("BUG: unknown controller initialization failure");
  494. return ERROR_NAND_OPERATION_FAILED;
  495. }
  496. }
  497. device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
  498. device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
  499. for (i = 0; i < device->num_blocks; i++)
  500. {
  501. device->blocks[i].size = device->erase_size;
  502. device->blocks[i].offset = i * device->erase_size;
  503. device->blocks[i].is_erased = -1;
  504. device->blocks[i].is_bad = -1;
  505. }
  506. return ERROR_OK;
  507. }
  508. int nand_erase(struct nand_device_s *device, int first_block, int last_block)
  509. {
  510. int i;
  511. u32 page;
  512. u8 status;
  513. int retval;
  514. if (!device->device)
  515. return ERROR_NAND_DEVICE_NOT_PROBED;
  516. if ((first_block < 0) || (last_block > device->num_blocks))
  517. return ERROR_INVALID_ARGUMENTS;
  518. /* make sure we know if a block is bad before erasing it */
  519. for (i = first_block; i <= last_block; i++)
  520. {
  521. if (device->blocks[i].is_bad == -1)
  522. {
  523. nand_build_bbt(device, i, last_block);
  524. break;
  525. }
  526. }
  527. for (i = first_block; i <= last_block; i++)
  528. {
  529. /* Send erase setup command */
  530. device->controller->command(device, NAND_CMD_ERASE1);
  531. page = i * (device->erase_size / device->page_size);
  532. /* Send page address */
  533. if (device->page_size <= 512)
  534. {
  535. /* row */
  536. device->controller->address(device, page & 0xff);
  537. device->controller->address(device, (page >> 8) & 0xff);
  538. /* 3rd cycle only on devices with more than 32 MiB */
  539. if (device->address_cycles >= 4)
  540. device->controller->address(device, (page >> 16) & 0xff);
  541. /* 4th cycle only on devices with more than 8 GiB */
  542. if (device->address_cycles >= 5)
  543. device->controller->address(device, (page >> 24) & 0xff);
  544. }
  545. else
  546. {
  547. /* row */
  548. device->controller->address(device, page & 0xff);
  549. device->controller->address(device, (page >> 8) & 0xff);
  550. /* 3rd cycle only on devices with more than 128 MiB */
  551. if (device->address_cycles >= 5)
  552. device->controller->address(device, (page >> 16) & 0xff);
  553. }
  554. /* Send erase confirm command */
  555. device->controller->command(device, NAND_CMD_ERASE2);
  556. if (!device->controller->nand_ready(device, 1000))
  557. {
  558. LOG_ERROR("timeout waiting for NAND flash block erase to complete");
  559. return ERROR_NAND_OPERATION_TIMEOUT;
  560. }
  561. if ((retval = nand_read_status(device, &status)) != ERROR_OK)
  562. {
  563. LOG_ERROR("couldn't read status");
  564. return ERROR_NAND_OPERATION_FAILED;
  565. }
  566. if (status & 0x1)
  567. {
  568. LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
  569. return ERROR_NAND_OPERATION_FAILED;
  570. }
  571. }
  572. return ERROR_OK;
  573. }
  574. int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
  575. {
  576. u8 *page;
  577. if (!device->device)
  578. return ERROR_NAND_DEVICE_NOT_PROBED;
  579. if (address % device->page_size)
  580. {
  581. LOG_ERROR("reads need to be page aligned");
  582. return ERROR_NAND_OPERATION_FAILED;
  583. }
  584. page = malloc(device->page_size);
  585. while (data_size > 0 )
  586. {
  587. u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
  588. u32 page_address;
  589. page_address = address / device->page_size;
  590. nand_read_page(device, page_address, page, device->page_size, NULL, 0);
  591. memcpy(data, page, thisrun_size);
  592. address += thisrun_size;
  593. data += thisrun_size;
  594. data_size -= thisrun_size;
  595. }
  596. free(page);
  597. return ERROR_OK;
  598. }
  599. int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
  600. {
  601. u8 *page;
  602. if (!device->device)
  603. return ERROR_NAND_DEVICE_NOT_PROBED;
  604. if (address % device->page_size)
  605. {
  606. LOG_ERROR("writes need to be page aligned");
  607. return ERROR_NAND_OPERATION_FAILED;
  608. }
  609. page = malloc(device->page_size);
  610. while (data_size > 0 )
  611. {
  612. u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
  613. u32 page_address;
  614. memset(page, 0xff, device->page_size);
  615. memcpy(page, data, thisrun_size);
  616. page_address = address / device->page_size;
  617. nand_write_page(device, page_address, page, device->page_size, NULL, 0);
  618. address += thisrun_size;
  619. data += thisrun_size;
  620. data_size -= thisrun_size;
  621. }
  622. free(page);
  623. return ERROR_OK;
  624. }
  625. int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
  626. {
  627. if (!device->device)
  628. return ERROR_NAND_DEVICE_NOT_PROBED;
  629. if (device->use_raw || device->controller->write_page == NULL)
  630. return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
  631. else
  632. return device->controller->write_page(device, page, data, data_size, oob, oob_size);
  633. }
  634. int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
  635. {
  636. if (!device->device)
  637. return ERROR_NAND_DEVICE_NOT_PROBED;
  638. if (device->use_raw || device->controller->read_page == NULL)
  639. return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
  640. else
  641. return device->controller->read_page(device, page, data, data_size, oob, oob_size);
  642. }
  643. int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
  644. {
  645. int i;
  646. if (!device->device)
  647. return ERROR_NAND_DEVICE_NOT_PROBED;
  648. if (device->page_size <= 512)
  649. {
  650. /* small page device */
  651. if (data)
  652. device->controller->command(device, NAND_CMD_READ0);
  653. else
  654. device->controller->command(device, NAND_CMD_READOOB);
  655. /* column (always 0, we start at the beginning of a page/OOB area) */
  656. device->controller->address(device, 0x0);
  657. /* row */
  658. device->controller->address(device, page & 0xff);
  659. device->controller->address(device, (page >> 8) & 0xff);
  660. /* 4th cycle only on devices with more than 32 MiB */
  661. if (device->address_cycles >= 4)
  662. device->controller->address(device, (page >> 16) & 0xff);
  663. /* 5th cycle only on devices with more than 8 GiB */
  664. if (device->address_cycles >= 5)
  665. device->controller->address(device, (page >> 24) & 0xff);
  666. }
  667. else
  668. {
  669. /* large page device */
  670. device->controller->command(device, NAND_CMD_READ0);
  671. /* column (0 when we start at the beginning of a page,
  672. * or 2048 for the beginning of OOB area)
  673. */
  674. device->controller->address(device, 0x0);
  675. device->controller->address(device, 0x8);
  676. /* row */
  677. device->controller->address(device, page & 0xff);
  678. device->controller->address(device, (page >> 8) & 0xff);
  679. /* 5th cycle only on devices with more than 128 MiB */
  680. if (device->address_cycles >= 5)
  681. device->controller->address(device, (page >> 16) & 0xff);
  682. /* large page devices need a start command */
  683. device->controller->command(device, NAND_CMD_READSTART);
  684. }
  685. if (!device->controller->nand_ready(device, 100))
  686. return ERROR_NAND_OPERATION_TIMEOUT;
  687. if (data)
  688. {
  689. if (device->controller->read_block_data != NULL)
  690. (device->controller->read_block_data)(device, data, data_size);
  691. else
  692. {
  693. for (i = 0; i < data_size;)
  694. {
  695. if (device->device->options & NAND_BUSWIDTH_16)
  696. {
  697. device->controller->read_data(device, data);
  698. data += 2;
  699. i += 2;
  700. }
  701. else
  702. {
  703. device->controller->read_data(device, data);
  704. data += 1;
  705. i += 1;
  706. }
  707. }
  708. }
  709. }
  710. if (oob)
  711. {
  712. if (device->controller->read_block_data != NULL)
  713. (device->controller->read_block_data)(device, oob, oob_size);
  714. else
  715. {
  716. for (i = 0; i < oob_size;)
  717. {
  718. if (device->device->options & NAND_BUSWIDTH_16)
  719. {
  720. device->controller->read_data(device, oob);
  721. oob += 2;
  722. i += 2;
  723. }
  724. else
  725. {
  726. device->controller->read_data(device, oob);
  727. oob += 1;
  728. i += 1;
  729. }
  730. }
  731. }
  732. }
  733. return ERROR_OK;
  734. }
  735. int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
  736. {
  737. int i;
  738. int retval;
  739. u8 status;
  740. if (!device->device)
  741. return ERROR_NAND_DEVICE_NOT_PROBED;
  742. device->controller->command(device, NAND_CMD_SEQIN);
  743. if (device->page_size <= 512)
  744. {
  745. /* column (always 0, we start at the beginning of a page/OOB area) */
  746. device->controller->address(device, 0x0);
  747. /* row */
  748. device->controller->address(device, page & 0xff);
  749. device->controller->address(device, (page >> 8) & 0xff);
  750. /* 4th cycle only on devices with more than 32 MiB */
  751. if (device->address_cycles >= 4)
  752. device->controller->address(device, (page >> 16) & 0xff);
  753. /* 5th cycle only on devices with more than 8 GiB */
  754. if (device->address_cycles >= 5)
  755. device->controller->address(device, (page >> 24) & 0xff);
  756. }
  757. else
  758. {
  759. /* column (0 when we start at the beginning of a page,
  760. * or 2048 for the beginning of OOB area)
  761. */
  762. device->controller->address(device, 0x0);
  763. device->controller->address(device, 0x8);
  764. /* row */
  765. device->controller->address(device, page & 0xff);
  766. device->controller->address(device, (page >> 8) & 0xff);
  767. /* 5th cycle only on devices with more than 128 MiB */
  768. if (device->address_cycles >= 5)
  769. device->controller->address(device, (page >> 16) & 0xff);
  770. }
  771. if (data)
  772. {
  773. if (device->controller->write_block_data != NULL)
  774. (device->controller->write_block_data)(device, data, data_size);
  775. else
  776. {
  777. for (i = 0; i < data_size;)
  778. {
  779. if (device->device->options & NAND_BUSWIDTH_16)
  780. {
  781. u16 data_buf = le_to_h_u16(data);
  782. device->controller->write_data(device, data_buf);
  783. data += 2;
  784. i += 2;
  785. }
  786. else
  787. {
  788. device->controller->write_data(device, *data);
  789. data += 1;
  790. i += 1;
  791. }
  792. }
  793. }
  794. }
  795. if (oob)
  796. {
  797. if (device->controller->write_block_data != NULL)
  798. (device->controller->write_block_data)(device, oob, oob_size);
  799. else
  800. {
  801. for (i = 0; i < oob_size;)
  802. {
  803. if (device->device->options & NAND_BUSWIDTH_16)
  804. {
  805. u16 oob_buf = le_to_h_u16(data);
  806. device->controller->write_data(device, oob_buf);
  807. oob += 2;
  808. i += 2;
  809. }
  810. else
  811. {
  812. device->controller->write_data(device, *oob);
  813. oob += 1;
  814. i += 1;
  815. }
  816. }
  817. }
  818. }
  819. device->controller->command(device, NAND_CMD_PAGEPROG);
  820. if (!device->controller->nand_ready(device, 100))
  821. return ERROR_NAND_OPERATION_TIMEOUT;
  822. if ((retval = nand_read_status(device, &status)) != ERROR_OK)
  823. {
  824. LOG_ERROR("couldn't read status");
  825. return ERROR_NAND_OPERATION_FAILED;
  826. }
  827. if (status & NAND_STATUS_FAIL)
  828. {
  829. LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
  830. return ERROR_NAND_OPERATION_FAILED;
  831. }
  832. return ERROR_OK;
  833. }
  834. int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  835. {
  836. nand_device_t *p;
  837. int i = 0;
  838. if (!nand_devices)
  839. {
  840. command_print(cmd_ctx, "no NAND flash devices configured");
  841. return ERROR_OK;
  842. }
  843. for (p = nand_devices; p; p = p->next)
  844. {
  845. if (p->device)
  846. command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
  847. i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
  848. else
  849. command_print(cmd_ctx, "#%i: not probed");
  850. }
  851. return ERROR_OK;
  852. }
  853. int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  854. {
  855. nand_device_t *p;
  856. int i = 0;
  857. int j = 0;
  858. int first = -1;
  859. int last = -1;
  860. if ((argc < 1) || (argc > 3))
  861. {
  862. return ERROR_COMMAND_SYNTAX_ERROR;
  863. }
  864. if (argc == 2)
  865. {
  866. first = last = strtoul(args[1], NULL, 0);
  867. }
  868. else if (argc == 3)
  869. {
  870. first = strtoul(args[1], NULL, 0);
  871. last = strtoul(args[2], NULL, 0);
  872. }
  873. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  874. if (p)
  875. {
  876. if (p->device)
  877. {
  878. if (first >= p->num_blocks)
  879. first = p->num_blocks - 1;
  880. if (last >= p->num_blocks)
  881. last = p->num_blocks - 1;
  882. command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
  883. i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
  884. for (j = first; j <= last; j++)
  885. {
  886. char *erase_state, *bad_state;
  887. if (p->blocks[j].is_erased == 0)
  888. erase_state = "not erased";
  889. else if (p->blocks[j].is_erased == 1)
  890. erase_state = "erased";
  891. else
  892. erase_state = "erase state unknown";
  893. if (p->blocks[j].is_bad == 0)
  894. bad_state = "";
  895. else if (p->blocks[j].is_bad == 1)
  896. bad_state = " (marked bad)";
  897. else
  898. bad_state = " (block condition unknown)";
  899. command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
  900. j, p->blocks[j].offset, p->blocks[j].size / 1024,
  901. erase_state, bad_state);
  902. }
  903. }
  904. else
  905. {
  906. command_print(cmd_ctx, "#%i: not probed");
  907. }
  908. }
  909. return ERROR_OK;
  910. }
  911. int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  912. {
  913. nand_device_t *p;
  914. int retval;
  915. if (argc != 1)
  916. {
  917. return ERROR_COMMAND_SYNTAX_ERROR;
  918. }
  919. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  920. if (p)
  921. {
  922. if ((retval = nand_probe(p)) == ERROR_OK)
  923. {
  924. command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
  925. }
  926. else if (retval == ERROR_NAND_OPERATION_FAILED)
  927. {
  928. command_print(cmd_ctx, "probing failed for NAND flash device");
  929. }
  930. else
  931. {
  932. command_print(cmd_ctx, "unknown error when probing NAND flash device");
  933. }
  934. }
  935. else
  936. {
  937. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  938. }
  939. return ERROR_OK;
  940. }
  941. int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  942. {
  943. nand_device_t *p;
  944. int retval;
  945. if (argc != 3)
  946. {
  947. return ERROR_COMMAND_SYNTAX_ERROR;
  948. }
  949. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  950. if (p)
  951. {
  952. int first = strtoul(args[1], NULL, 0);
  953. int last = strtoul(args[2], NULL, 0);
  954. if ((retval = nand_erase(p, first, last)) == ERROR_OK)
  955. {
  956. command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
  957. }
  958. else if (retval == ERROR_NAND_OPERATION_FAILED)
  959. {
  960. command_print(cmd_ctx, "erase failed");
  961. }
  962. else
  963. {
  964. command_print(cmd_ctx, "unknown error when erasing NAND flash device");
  965. }
  966. }
  967. else
  968. {
  969. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  970. }
  971. return ERROR_OK;
  972. }
  973. int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  974. {
  975. nand_device_t *p;
  976. int retval;
  977. int first = -1;
  978. int last = -1;
  979. if ((argc < 1) || (argc > 3) || (argc == 2))
  980. {
  981. return ERROR_COMMAND_SYNTAX_ERROR;
  982. }
  983. if (argc == 3)
  984. {
  985. first = strtoul(args[1], NULL, 0);
  986. last = strtoul(args[2], NULL, 0);
  987. }
  988. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  989. if (p)
  990. {
  991. if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
  992. {
  993. command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
  994. }
  995. else if (retval == ERROR_NAND_OPERATION_FAILED)
  996. {
  997. command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
  998. }
  999. else
  1000. {
  1001. command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
  1002. }
  1003. }
  1004. else
  1005. {
  1006. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  1007. }
  1008. return ERROR_OK;
  1009. }
  1010. int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1011. {
  1012. nand_device_t *p;
  1013. if (argc != 4)
  1014. {
  1015. return ERROR_COMMAND_SYNTAX_ERROR;
  1016. }
  1017. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  1018. if (p)
  1019. {
  1020. }
  1021. else
  1022. {
  1023. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  1024. }
  1025. return ERROR_OK;
  1026. }
  1027. int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1028. {
  1029. u32 offset;
  1030. u32 binary_size;
  1031. u32 buf_cnt;
  1032. enum oob_formats oob_format = NAND_OOB_NONE;
  1033. fileio_t fileio;
  1034. duration_t duration;
  1035. char *duration_text;
  1036. nand_device_t *p;
  1037. if (argc < 3)
  1038. {
  1039. return ERROR_COMMAND_SYNTAX_ERROR;
  1040. }
  1041. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  1042. if (p)
  1043. {
  1044. u8 *page = NULL;
  1045. u32 page_size = 0;
  1046. u8 *oob = NULL;
  1047. u32 oob_size = 0;
  1048. duration_start_measure(&duration);
  1049. offset = strtoul(args[2], NULL, 0);
  1050. if (argc > 3)
  1051. {
  1052. int i;
  1053. for (i = 3; i < argc; i++)
  1054. {
  1055. if (!strcmp(args[i], "oob_raw"))
  1056. oob_format |= NAND_OOB_RAW;
  1057. else if (!strcmp(args[i], "oob_only"))
  1058. oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
  1059. else
  1060. {
  1061. command_print(cmd_ctx, "unknown option: %s", args[i]);
  1062. }
  1063. }
  1064. }
  1065. if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
  1066. {
  1067. return ERROR_OK;
  1068. }
  1069. buf_cnt = binary_size = fileio.size;
  1070. if (!(oob_format & NAND_OOB_ONLY))
  1071. {
  1072. page_size = p->page_size;
  1073. page = malloc(p->page_size);
  1074. }
  1075. if (oob_format & NAND_OOB_RAW)
  1076. {
  1077. if (p->page_size == 512)
  1078. oob_size = 16;
  1079. else if (p->page_size == 2048)
  1080. oob_size = 64;
  1081. oob = malloc(oob_size);
  1082. }
  1083. if (offset % p->page_size)
  1084. {
  1085. command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
  1086. return ERROR_OK;
  1087. }
  1088. while (buf_cnt > 0)
  1089. {
  1090. u32 size_read;
  1091. if (page)
  1092. {
  1093. fileio_read(&fileio, page_size, page, &size_read);
  1094. buf_cnt -= size_read;
  1095. if (size_read < page_size)
  1096. {
  1097. memset(page + size_read, 0xff, page_size - size_read);
  1098. }
  1099. }
  1100. if (oob)
  1101. {
  1102. fileio_read(&fileio, oob_size, oob, &size_read);
  1103. buf_cnt -= size_read;
  1104. if (size_read < oob_size)
  1105. {
  1106. memset(oob + size_read, 0xff, oob_size - size_read);
  1107. }
  1108. }
  1109. if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
  1110. {
  1111. command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
  1112. args[1], args[0], offset);
  1113. return ERROR_OK;
  1114. }
  1115. offset += page_size;
  1116. }
  1117. fileio_close(&fileio);
  1118. duration_stop_measure(&duration, &duration_text);
  1119. command_print(cmd_ctx, "wrote file %s to NAND flash %s at offset 0x%8.8x in %s",
  1120. args[1], args[0], offset, duration_text);
  1121. free(duration_text);
  1122. }
  1123. else
  1124. {
  1125. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  1126. }
  1127. return ERROR_OK;
  1128. }
  1129. int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1130. {
  1131. nand_device_t *p;
  1132. if (argc < 4)
  1133. {
  1134. return ERROR_COMMAND_SYNTAX_ERROR;
  1135. }
  1136. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  1137. if (p)
  1138. {
  1139. if (p->device)
  1140. {
  1141. fileio_t fileio;
  1142. duration_t duration;
  1143. char *duration_text;
  1144. int retval;
  1145. u8 *page = NULL;
  1146. u32 page_size = 0;
  1147. u8 *oob = NULL;
  1148. u32 oob_size = 0;
  1149. u32 address = strtoul(args[2], NULL, 0);
  1150. u32 size = strtoul(args[3], NULL, 0);
  1151. u32 bytes_done = 0;
  1152. enum oob_formats oob_format = NAND_OOB_NONE;
  1153. if (argc > 4)
  1154. {
  1155. int i;
  1156. for (i = 4; i < argc; i++)
  1157. {
  1158. if (!strcmp(args[i], "oob_raw"))
  1159. oob_format |= NAND_OOB_RAW;
  1160. else if (!strcmp(args[i], "oob_only"))
  1161. oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
  1162. else
  1163. command_print(cmd_ctx, "unknown option: '%s'", args[i]);
  1164. }
  1165. }
  1166. if ((address % p->page_size) || (size % p->page_size))
  1167. {
  1168. command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
  1169. return ERROR_OK;
  1170. }
  1171. if (!(oob_format & NAND_OOB_ONLY))
  1172. {
  1173. page_size = p->page_size;
  1174. page = malloc(p->page_size);
  1175. }
  1176. if (oob_format & NAND_OOB_RAW)
  1177. {
  1178. if (p->page_size == 512)
  1179. oob_size = 16;
  1180. else if (p->page_size == 2048)
  1181. oob_size = 64;
  1182. oob = malloc(oob_size);
  1183. }
  1184. if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
  1185. {
  1186. return ERROR_OK;
  1187. }
  1188. duration_start_measure(&duration);
  1189. while (size > 0)
  1190. {
  1191. u32 size_written;
  1192. if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
  1193. {
  1194. command_print(cmd_ctx, "reading NAND flash page failed");
  1195. return ERROR_OK;
  1196. }
  1197. if (page)
  1198. {
  1199. fileio_write(&fileio, page_size, page, &size_written);
  1200. bytes_done += page_size;
  1201. }
  1202. if (oob)
  1203. {
  1204. fileio_write(&fileio, oob_size, oob, &size_written);
  1205. bytes_done += oob_size;
  1206. }
  1207. size -= p->page_size;
  1208. address += p->page_size;
  1209. }
  1210. if (page)
  1211. free(page);
  1212. if (oob)
  1213. free(oob);
  1214. fileio_close(&fileio);
  1215. duration_stop_measure(&duration, &duration_text);
  1216. command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
  1217. free(duration_text);
  1218. }
  1219. else
  1220. {
  1221. command_print(cmd_ctx, "#%i: not probed");
  1222. }
  1223. }
  1224. else
  1225. {
  1226. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  1227. }
  1228. return ERROR_OK;
  1229. }
  1230. int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1231. {
  1232. nand_device_t *p;
  1233. if ((argc < 1) || (argc > 2))
  1234. {
  1235. return ERROR_COMMAND_SYNTAX_ERROR;
  1236. }
  1237. p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
  1238. if (p)
  1239. {
  1240. if (p->device)
  1241. {
  1242. if (argc == 2)
  1243. {
  1244. if (strcmp("enable", args[1]) == 0)
  1245. {
  1246. p->use_raw = 1;
  1247. }
  1248. else if (strcmp("disable", args[1]) == 0)
  1249. {
  1250. p->use_raw = 0;
  1251. }
  1252. else
  1253. {
  1254. return ERROR_COMMAND_SYNTAX_ERROR;
  1255. }
  1256. }
  1257. command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
  1258. }
  1259. else
  1260. {
  1261. command_print(cmd_ctx, "#%i: not probed");
  1262. }
  1263. }
  1264. else
  1265. {
  1266. command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
  1267. }
  1268. return ERROR_OK;
  1269. }