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openocd/tcl/board/imx35pdk.cfg

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  1. # The IMX35PDK eval board has a single IMX35 chip

  2. source [find target/imx35.cfg]

  3. source [find target/imx.cfg]

  4. $_TARGETNAME configure -event reset-init { imx35pdk_init }

  5. 

  6. # Stick to *really* low clock rate or reset will fail

  7. # without RTCK / RCLK

  8. jtag_rclk 10

  9. 

  10. proc imx35pdk_init { } {

  11. 	

  12. 	imx3x_reset

  13. 	

  14. 	mww 0x43f00040 0x00000000

  15. 	mww 0x43f00044 0x00000000

  16. 	mww 0x43f00048 0x00000000

  17. 	mww 0x43f0004C 0x00000000

  18. 	mww 0x43f00050 0x00000000

  19. 	mww 0x43f00000 0x77777777

  20. 	mww 0x43f00004 0x77777777

  21. 	mww 0x53f00040 0x00000000

  22. 	mww 0x53f00044 0x00000000

  23. 	mww 0x53f00048 0x00000000

  24. 	mww 0x53f0004C 0x00000000

  25. 	mww 0x53f00050 0x00000000

  26. 	mww 0x53f00000 0x77777777

  27. 	mww 0x53f00004 0x77777777

  28. 	

  29. 	# clock setup

  30. 	mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP

  31. 	mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.

  32. 	

  33. 	#=================================================

  34. 	# WEIM config

  35. 	#=================================================

  36. 	# CS0U

  37. 	mww 0xB8002000 0x0000CC03

  38. 	# CS0L

  39. 	mww 0xB8002004 0xA0330D01

  40. 	# CS0A

  41. 	mww 0xB8002008 0x00220800

  42. 	# CS5U

  43. 	mww 0xB8002050 0x0000dcf6

  44. 	# CS5L

  45. 	mww 0xB8002054 0x444a4541

  46. 	# CS5A

  47. 	mww 0xB8002058 0x44443302

  48. 	

  49. 	# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR

  50. 	mww 0x43FAC368 0x00000006

  51. 	mww 0x43FAC36C 0x00000006

  52. 	mww 0x43FAC370 0x00000006

  53. 	mww 0x43FAC374 0x00000006

  54. 	mww 0x43FAC378 0x00000006

  55. 	mww 0x43FAC37C 0x00000006	

  56. 	mww 0x43FAC380 0x00000006

  57. 	mww 0x43FAC384 0x00000006

  58. 	mww 0x43FAC388 0x00000006

  59. 	mww 0x43FAC38C 0x00000006

  60. 	mww 0x43FAC390 0x00000006

  61. 	mww 0x43FAC394 0x00000006

  62. 	mww 0x43FAC398 0x00000006

  63. 	mww 0x43FAC39C 0x00000006

  64. 	mww 0x43FAC3A0 0x00000006

  65. 	mww 0x43FAC3A4 0x00000006

  66. 	mww 0x43FAC3A8 0x00000006

  67. 	mww 0x43FAC3AC 0x00000006

  68. 	mww 0x43FAC3B0 0x00000006

  69. 	mww 0x43FAC3B4 0x00000006

  70. 	mww 0x43FAC3B8 0x00000006

  71. 	mww 0x43FAC3BC 0x00000006

  72. 	mww 0x43FAC3C0 0x00000006

  73. 	mww 0x43FAC3C4 0x00000006

  74. 	mww 0x43FAC3C8 0x00000006

  75. 	mww 0x43FAC3CC 0x00000006

  76. 	mww 0x43FAC3D0 0x00000006

  77. 	mww 0x43FAC3D4 0x00000006

  78. 	mww 0x43FAC3D8 0x00000006

  79. 	

  80. 	# DDR data bus SD 0 through 31

  81. 	mww 0x43FAC3DC 0x00000082

  82. 	mww 0x43FAC3E0 0x00000082

  83. 	mww 0x43FAC3E4 0x00000082

  84. 	mww 0x43FAC3E8 0x00000082

  85. 	mww 0x43FAC3EC 0x00000082

  86. 	mww 0x43FAC3F0 0x00000082

  87. 	mww 0x43FAC3F4 0x00000082

  88. 	mww 0x43FAC3F8 0x00000082

  89. 	mww 0x43FAC3FC 0x00000082

  90. 	mww 0x43FAC400 0x00000082

  91. 	mww 0x43FAC404 0x00000082

  92. 	mww 0x43FAC408 0x00000082

  93. 	mww 0x43FAC40C 0x00000082

  94. 	mww 0x43FAC410 0x00000082

  95. 	mww 0x43FAC414 0x00000082

  96. 	mww 0x43FAC418 0x00000082

  97. 	mww 0x43FAC41c 0x00000082

  98. 	mww 0x43FAC420 0x00000082

  99. 	mww 0x43FAC424 0x00000082

  100. 	mww 0x43FAC428 0x00000082

  101. 	mww 0x43FAC42c 0x00000082

  102. 	mww 0x43FAC430 0x00000082

  103. 	mww 0x43FAC434 0x00000082

  104. 	mww 0x43FAC438 0x00000082

  105. 	mww 0x43FAC43c 0x00000082

  106. 	mww 0x43FAC440 0x00000082

  107. 	mww 0x43FAC444 0x00000082

  108. 	mww 0x43FAC448 0x00000082

  109. 	mww 0x43FAC44c 0x00000082

  110. 	mww 0x43FAC450 0x00000082

  111. 	mww 0x43FAC454 0x00000082

  112. 	mww 0x43FAC458 0x00000082

  113. 	

  114. 	# DQM setup

  115. 	mww 0x43FAC45c 0x00000082

  116. 	mww 0x43FAC460 0x00000082

  117. 	mww 0x43FAC464 0x00000082

  118. 	mww 0x43FAC468 0x00000082

  119. 	

  120. 	mww 0x43FAC46c 0x00000006

  121. 	mww 0x43FAC470 0x00000006

  122. 	mww 0x43FAC474 0x00000006

  123. 	mww 0x43FAC478 0x00000006

  124. 	mww 0x43FAC47c 0x00000006

  125. 	mww 0x43FAC480 0x00000006	# CSD0

  126. 	mww 0x43FAC484 0x00000006	# CSD1

  127. 	mww 0x43FAC488 0x00000006

  128. 	mww 0x43FAC48c 0x00000006

  129. 	mww 0x43FAC490 0x00000006

  130. 	mww 0x43FAC494 0x00000006

  131. 	mww 0x43FAC498 0x00000006

  132. 	mww 0x43FAC49c 0x00000006

  133. 	mww 0x43FAC4A0 0x00000006	

  134. 	mww 0x43FAC4A4 0x00000006	# RAS

  135. 	mww 0x43FAC4A8 0x00000006	# CAS

  136. 	mww 0x43FAC4Ac 0x00000006	# SDWE

  137. 	mww 0x43FAC4B0 0x00000006 	# SDCKE0

  138. 	mww 0x43FAC4B4 0x00000006  # SDCKE1

  139. 	mww 0x43FAC4B8 0x00000002  # SDCLK

  140. 	

  141. 	# SDQS0 through SDQS3

  142. 	mww 0x43FAC4Bc 0x00000082

  143. 	mww 0x43FAC4C0 0x00000082

  144. 	mww 0x43FAC4C4 0x00000082

  145. 	mww 0x43FAC4C8 0x00000082

  146. 	

  147. 	

  148. 	# *==================================================

  149. 	#  Initialization script for 32 bit DDR2 on RINGO 3DS

  150. 	# *==================================================

  151. 	

  152. 	#--------------------------------------------

  153. 	# Init CCM

  154. 	#--------------------------------------------

  155. 	mww 0x53F80028 0x7D000028

  156. 	

  157. 	#--------------------------------------------

  158. 	# Init IOMUX for JTAG

  159. 	#--------------------------------------------

  160. 	mww 0x43FAC5EC 0x000000C3

  161. 	mww 0x43FAC5F0 0x000000C3

  162. 	mww 0x43FAC5F4 0x000000F3

  163. 	mww 0x43FAC5F8 0x000000F3

  164. 	mww 0x43FAC5FC 0x000000F3

  165. 	mww 0x43FAC600 0x000000F3

  166. 	mww 0x43FAC604 0x000000F3

  167. 	

  168. 	

  169. 	# ESD_MISC : enable DDR2

  170. 	mww 0xB8001010 0x00000304

  171. 	

  172. 	#--------------------------------------------

  173. 	# Init 32-bit DDR2 memeory on CSD0

  174. 	# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]

  175. 	#--------------------------------------------

  176. 	

  177. 	# ESD_ESDCFG0 : set timing paramters

  178. 	mww 0xB8001004 0x007ffC2f	

  179. 	

  180. 	# ESD_ESDCTL0 : select Prechare-All mode

  181. 	mww 0xB8001000 0x92220000

  182. 	# DDR2 : Prechare-All

  183. 	mww 0x80000400 0x12345678

  184. 	

  185. 	# ESD_ESDCTL0 : select Load-Mode-Register mode

  186. 	mww 0xB8001000 0xB2220000

  187. 	# DDR2 : Load reg EMR2

  188. 	mwb 0x84000000 0xda

  189. 	# DDR2 : Load reg EMR3

  190. 	mwb 0x86000000 0xda

  191. 	# DDR2 : Load reg EMR1 -- enable DLL

  192. 	mwb 0x82000400 0xda

  193. 	# DDR2 : Load reg MR -- reset DLL

  194. 	mwb 0x80000333 0xda

  195. 	

  196. 	# ESD_ESDCTL0 : select Prechare-All mode

  197. 	mww 0xB8001000 0x92220000

  198. 	# DDR2 : Prechare-All

  199. 	mwb 0x80000400 0x12345678

  200. 	

  201. 	# ESD_ESDCTL0 : select Manual-Refresh mode

  202. 	mww 0xB8001000 0xA2220000

  203. 	# DDR2 : Manual-Refresh 2 times

  204. 	mww 0x80000000 0x87654321

  205. 	mww 0x80000000 0x87654321

  206. 	

  207. 	# ESD_ESDCTL0 : select Load-Mode-Register mode

  208. 	mww 0xB8001000 0xB2220000

  209. 	# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset

  210. 	mwb 0x80000233 0xda

  211. 	# DDR2 : Load reg EMR1 -- OCD default

  212. 	mwb 0x82000780 0xda

  213. 	# DDR2 : Load reg EMR1 -- OCD exit

  214. 	mwb 0x82000400 0xda	# ODT disabled

  215. 	

  216. 	# ESD_ESDCTL0 : select normal-operation mode

  217. 	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit

  218. 	# disable PWT & PRCT

  219. 	# disable Auto-Refresh

  220. 	mww 0xB8001000 0x82220080

  221. 	

  222. 	## ESD_ESDCTL0 : enable Auto-Refresh

  223. 	mww 0xB8001000 0x82228080

  224. 	## ESD_ESDCTL1 : enable Auto-Refresh

  225. 	mww 0xB8001008 0x00002000

  226. 	

  227. 	

  228. 	#***********************************************

  229. 	# Adjust the ESDCDLY5 register

  230. 	#***********************************************

  231. 	# Vary DQS_ABS_OFFSET5 for writes

  232. 	mww 0xB8001020 0x00F48000	# this is the default value

  233. 	mww 0xB8001024 0x00F48000	# this is the default value

  234. 	mww 0xB8001028 0x00F48000	# this is the default value

  235. 	mww 0xB800102c 0x00F48000	# this is the default value

  236. 	

  237. 	

  238. 	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)

  239. 	mww 0xB8001010 0x00000384

  240. 	# wait a while

  241. 	sleep 1000

  242. 	# now clear the force measurement bit

  243. 	mww 0xB8001010 0x00000304

  244. 	

  245. 	# dummy write to DDR memory to set DQS low

  246. 	mww 0x80000000 0x00000000

  247. 	

  248. 	mww 0x30000100 0x0

  249. 	mww 0x30000104 0x31024

  250. 	

  251. 	

  252. }