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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "arm7_9_common.h"
  24. #include "etb.h"
  25. static char* etb_reg_list[] =
  26. {
  27. "ETB_identification",
  28. "ETB_ram_depth",
  29. "ETB_ram_width",
  30. "ETB_status",
  31. "ETB_ram_data",
  32. "ETB_ram_read_pointer",
  33. "ETB_ram_write_pointer",
  34. "ETB_trigger_counter",
  35. "ETB_control",
  36. };
  37. static int etb_reg_arch_type = -1;
  38. static int etb_get_reg(reg_t *reg);
  39. static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40. static int etb_set_instr(etb_t *etb, u32 new_instr)
  41. {
  42. jtag_tap_t *tap;
  43. tap = etb->tap;
  44. if (tap==NULL)
  45. return ERROR_FAIL;
  46. if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  47. {
  48. scan_field_t field;
  49. field.tap = tap;
  50. field.num_bits = tap->ir_length;
  51. field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  52. buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  53. field.in_value = NULL;
  54. jtag_add_ir_scan(1, &field, jtag_get_end_state());
  55. free(field.out_value);
  56. }
  57. return ERROR_OK;
  58. }
  59. static int etb_scann(etb_t *etb, u32 new_scan_chain)
  60. {
  61. if (etb->cur_scan_chain != new_scan_chain)
  62. {
  63. scan_field_t field;
  64. field.tap = etb->tap;
  65. field.num_bits = 5;
  66. field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  67. buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
  68. field.in_value = NULL;
  69. /* select INTEST instruction */
  70. etb_set_instr(etb, 0x2);
  71. jtag_add_dr_scan(1, &field, jtag_get_end_state());
  72. etb->cur_scan_chain = new_scan_chain;
  73. free(field.out_value);
  74. }
  75. return ERROR_OK;
  76. }
  77. reg_cache_t* etb_build_reg_cache(etb_t *etb)
  78. {
  79. reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  80. reg_t *reg_list = NULL;
  81. etb_reg_t *arch_info = NULL;
  82. int num_regs = 9;
  83. int i;
  84. /* register a register arch-type for etm registers only once */
  85. if (etb_reg_arch_type == -1)
  86. etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
  87. /* the actual registers are kept in two arrays */
  88. reg_list = calloc(num_regs, sizeof(reg_t));
  89. arch_info = calloc(num_regs, sizeof(etb_reg_t));
  90. /* fill in values for the reg cache */
  91. reg_cache->name = "etb registers";
  92. reg_cache->next = NULL;
  93. reg_cache->reg_list = reg_list;
  94. reg_cache->num_regs = num_regs;
  95. /* set up registers */
  96. for (i = 0; i < num_regs; i++)
  97. {
  98. reg_list[i].name = etb_reg_list[i];
  99. reg_list[i].size = 32;
  100. reg_list[i].dirty = 0;
  101. reg_list[i].valid = 0;
  102. reg_list[i].bitfield_desc = NULL;
  103. reg_list[i].num_bitfields = 0;
  104. reg_list[i].value = calloc(1, 4);
  105. reg_list[i].arch_info = &arch_info[i];
  106. reg_list[i].arch_type = etb_reg_arch_type;
  107. reg_list[i].size = 32;
  108. arch_info[i].addr = i;
  109. arch_info[i].etb = etb;
  110. }
  111. return reg_cache;
  112. }
  113. static int etb_get_reg(reg_t *reg)
  114. {
  115. int retval;
  116. if ((retval = etb_read_reg(reg)) != ERROR_OK)
  117. {
  118. LOG_ERROR("BUG: error scheduling etm register read");
  119. return retval;
  120. }
  121. if ((retval = jtag_execute_queue()) != ERROR_OK)
  122. {
  123. LOG_ERROR("register read failed");
  124. return retval;
  125. }
  126. return ERROR_OK;
  127. }
  128. static void etb_getbuf(u8 *in)
  129. {
  130. *((u32 *)in)=buf_get_u32(in, 0, 32);
  131. }
  132. static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
  133. {
  134. scan_field_t fields[3];
  135. int i;
  136. jtag_add_end_state(TAP_IDLE);
  137. etb_scann(etb, 0x0);
  138. etb_set_instr(etb, 0xc);
  139. fields[0].tap = etb->tap;
  140. fields[0].num_bits = 32;
  141. fields[0].out_value = NULL;
  142. fields[0].in_value = NULL;
  143. fields[1].tap = etb->tap;
  144. fields[1].num_bits = 7;
  145. fields[1].out_value = malloc(1);
  146. buf_set_u32(fields[1].out_value, 0, 7, 4);
  147. fields[1].in_value = NULL;
  148. fields[2].tap = etb->tap;
  149. fields[2].num_bits = 1;
  150. fields[2].out_value = malloc(1);
  151. buf_set_u32(fields[2].out_value, 0, 1, 0);
  152. fields[2].in_value = NULL;
  153. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  154. for (i = 0; i < num_frames; i++)
  155. {
  156. /* ensure nR/W reamins set to read */
  157. buf_set_u32(fields[2].out_value, 0, 1, 0);
  158. /* address remains set to 0x4 (RAM data) until we read the last frame */
  159. if (i < num_frames - 1)
  160. buf_set_u32(fields[1].out_value, 0, 7, 4);
  161. else
  162. buf_set_u32(fields[1].out_value, 0, 7, 0);
  163. fields[0].in_value = (u8 *)(data+i);
  164. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  165. jtag_add_callback(etb_getbuf, (u8 *)(data+i));
  166. }
  167. jtag_execute_queue();
  168. free(fields[1].out_value);
  169. free(fields[2].out_value);
  170. return ERROR_OK;
  171. }
  172. int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
  173. {
  174. etb_reg_t *etb_reg = reg->arch_info;
  175. u8 reg_addr = etb_reg->addr & 0x7f;
  176. scan_field_t fields[3];
  177. LOG_DEBUG("%i", etb_reg->addr);
  178. jtag_add_end_state(TAP_IDLE);
  179. etb_scann(etb_reg->etb, 0x0);
  180. etb_set_instr(etb_reg->etb, 0xc);
  181. fields[0].tap = etb_reg->etb->tap;
  182. fields[0].num_bits = 32;
  183. fields[0].out_value = reg->value;
  184. fields[0].in_value = NULL;
  185. fields[0].check_value = NULL;
  186. fields[0].check_mask = NULL;
  187. fields[1].tap = etb_reg->etb->tap;
  188. fields[1].num_bits = 7;
  189. fields[1].out_value = malloc(1);
  190. buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
  191. fields[1].in_value = NULL;
  192. fields[1].check_value = NULL;
  193. fields[1].check_mask = NULL;
  194. fields[2].tap = etb_reg->etb->tap;
  195. fields[2].num_bits = 1;
  196. fields[2].out_value = malloc(1);
  197. buf_set_u32(fields[2].out_value, 0, 1, 0);
  198. fields[2].in_value = NULL;
  199. fields[2].check_value = NULL;
  200. fields[2].check_mask = NULL;
  201. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  202. /* read the identification register in the second run, to make sure we
  203. * don't read the ETB data register twice, skipping every second entry
  204. */
  205. buf_set_u32(fields[1].out_value, 0, 7, 0x0);
  206. fields[0].in_value = reg->value;
  207. fields[0].check_value = check_value;
  208. fields[0].check_mask = check_mask;
  209. jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
  210. free(fields[1].out_value);
  211. free(fields[2].out_value);
  212. return ERROR_OK;
  213. }
  214. int etb_read_reg(reg_t *reg)
  215. {
  216. return etb_read_reg_w_check(reg, NULL, NULL);
  217. }
  218. int etb_set_reg(reg_t *reg, u32 value)
  219. {
  220. int retval;
  221. if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
  222. {
  223. LOG_ERROR("BUG: error scheduling etm register write");
  224. return retval;
  225. }
  226. buf_set_u32(reg->value, 0, reg->size, value);
  227. reg->valid = 1;
  228. reg->dirty = 0;
  229. return ERROR_OK;
  230. }
  231. int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
  232. {
  233. int retval;
  234. etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
  235. if ((retval = jtag_execute_queue()) != ERROR_OK)
  236. {
  237. LOG_ERROR("register write failed");
  238. return retval;
  239. }
  240. return ERROR_OK;
  241. }
  242. int etb_write_reg(reg_t *reg, u32 value)
  243. {
  244. etb_reg_t *etb_reg = reg->arch_info;
  245. u8 reg_addr = etb_reg->addr & 0x7f;
  246. scan_field_t fields[3];
  247. LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
  248. jtag_add_end_state(TAP_IDLE);
  249. etb_scann(etb_reg->etb, 0x0);
  250. etb_set_instr(etb_reg->etb, 0xc);
  251. fields[0].tap = etb_reg->etb->tap;
  252. fields[0].num_bits = 32;
  253. fields[0].out_value = malloc(4);
  254. buf_set_u32(fields[0].out_value, 0, 32, value);
  255. fields[0].in_value = NULL;
  256. fields[1].tap = etb_reg->etb->tap;
  257. fields[1].num_bits = 7;
  258. fields[1].out_value = malloc(1);
  259. buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
  260. fields[1].in_value = NULL;
  261. fields[2].tap = etb_reg->etb->tap;
  262. fields[2].num_bits = 1;
  263. fields[2].out_value = malloc(1);
  264. buf_set_u32(fields[2].out_value, 0, 1, 1);
  265. fields[2].in_value = NULL;
  266. free(fields[0].out_value);
  267. free(fields[1].out_value);
  268. free(fields[2].out_value);
  269. return ERROR_OK;
  270. }
  271. int etb_store_reg(reg_t *reg)
  272. {
  273. return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
  274. }
  275. static int etb_register_commands(struct command_context_s *cmd_ctx)
  276. {
  277. command_t *etb_cmd;
  278. etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
  279. register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
  280. return ERROR_OK;
  281. }
  282. static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  283. {
  284. target_t *target;
  285. jtag_tap_t *tap;
  286. armv4_5_common_t *armv4_5;
  287. arm7_9_common_t *arm7_9;
  288. if (argc != 2)
  289. {
  290. return ERROR_COMMAND_SYNTAX_ERROR;
  291. }
  292. target = get_target(args[0]);
  293. if (!target)
  294. {
  295. LOG_ERROR("target '%s' not defined", args[0]);
  296. return ERROR_FAIL;
  297. }
  298. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  299. {
  300. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  301. return ERROR_FAIL;
  302. }
  303. tap = jtag_TapByString( args[1] );
  304. if (tap == NULL)
  305. {
  306. command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
  307. return ERROR_FAIL;
  308. }
  309. if (arm7_9->etm_ctx)
  310. {
  311. etb_t *etb = malloc(sizeof(etb_t));
  312. arm7_9->etm_ctx->capture_driver_priv = etb;
  313. etb->tap = tap;
  314. etb->cur_scan_chain = 0xffffffff;
  315. etb->reg_cache = NULL;
  316. etb->ram_width = 0;
  317. etb->ram_depth = 0;
  318. }
  319. else
  320. {
  321. LOG_ERROR("target has no ETM defined, ETB left unconfigured");
  322. return ERROR_FAIL;
  323. }
  324. return ERROR_OK;
  325. }
  326. static int etb_init(etm_context_t *etm_ctx)
  327. {
  328. etb_t *etb = etm_ctx->capture_driver_priv;
  329. etb->etm_ctx = etm_ctx;
  330. /* identify ETB RAM depth and width */
  331. etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
  332. etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
  333. jtag_execute_queue();
  334. etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
  335. etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
  336. return ERROR_OK;
  337. }
  338. static trace_status_t etb_status(etm_context_t *etm_ctx)
  339. {
  340. etb_t *etb = etm_ctx->capture_driver_priv;
  341. etb->etm_ctx = etm_ctx;
  342. /* if tracing is currently idle, return this information */
  343. if (etm_ctx->capture_status == TRACE_IDLE)
  344. {
  345. return etm_ctx->capture_status;
  346. }
  347. else if (etm_ctx->capture_status & TRACE_RUNNING)
  348. {
  349. reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
  350. int etb_timeout = 100;
  351. /* trace is running, check the ETB status flags */
  352. etb_get_reg(etb_status_reg);
  353. /* check Full bit to identify an overflow */
  354. if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
  355. etm_ctx->capture_status |= TRACE_OVERFLOWED;
  356. /* check Triggered bit to identify trigger condition */
  357. if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
  358. etm_ctx->capture_status |= TRACE_TRIGGERED;
  359. /* check AcqComp to identify trace completion */
  360. if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
  361. {
  362. while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
  363. {
  364. /* wait for data formatter idle */
  365. etb_get_reg(etb_status_reg);
  366. }
  367. if (etb_timeout == 0)
  368. {
  369. LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
  370. buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
  371. }
  372. if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
  373. {
  374. LOG_ERROR("trace completed, but no trigger condition detected");
  375. }
  376. etm_ctx->capture_status &= ~TRACE_RUNNING;
  377. etm_ctx->capture_status |= TRACE_COMPLETED;
  378. }
  379. }
  380. return etm_ctx->capture_status;
  381. }
  382. static int etb_read_trace(etm_context_t *etm_ctx)
  383. {
  384. etb_t *etb = etm_ctx->capture_driver_priv;
  385. int first_frame = 0;
  386. int num_frames = etb->ram_depth;
  387. u32 *trace_data = NULL;
  388. int i, j;
  389. etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
  390. etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
  391. jtag_execute_queue();
  392. /* check if we overflowed, and adjust first frame of the trace accordingly
  393. * if we didn't overflow, read only up to the frame that would be written next,
  394. * i.e. don't read invalid entries
  395. */
  396. if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
  397. {
  398. first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
  399. }
  400. else
  401. {
  402. num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
  403. }
  404. etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
  405. /* read data into temporary array for unpacking */
  406. trace_data = malloc(sizeof(u32) * num_frames);
  407. etb_read_ram(etb, trace_data, num_frames);
  408. if (etm_ctx->trace_depth > 0)
  409. {
  410. free(etm_ctx->trace_data);
  411. }
  412. if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
  413. etm_ctx->trace_depth = num_frames * 3;
  414. else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
  415. etm_ctx->trace_depth = num_frames * 2;
  416. else
  417. etm_ctx->trace_depth = num_frames;
  418. etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
  419. for (i = 0, j = 0; i < num_frames; i++)
  420. {
  421. if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
  422. {
  423. /* trace word j */
  424. etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
  425. etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
  426. etm_ctx->trace_data[j].flags = 0;
  427. if ((trace_data[i] & 0x80) >> 7)
  428. {
  429. etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
  430. }
  431. if (etm_ctx->trace_data[j].pipestat == STAT_TR)
  432. {
  433. etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
  434. etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
  435. }
  436. /* trace word j+1 */
  437. etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
  438. etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
  439. etm_ctx->trace_data[j+1].flags = 0;
  440. if ((trace_data[i] & 0x8000) >> 15)
  441. {
  442. etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
  443. }
  444. if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
  445. {
  446. etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
  447. etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
  448. }
  449. /* trace word j+2 */
  450. etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
  451. etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
  452. etm_ctx->trace_data[j+2].flags = 0;
  453. if ((trace_data[i] & 0x800000) >> 23)
  454. {
  455. etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
  456. }
  457. if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
  458. {
  459. etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
  460. etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
  461. }
  462. j += 3;
  463. }
  464. else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
  465. {
  466. /* trace word j */
  467. etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
  468. etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
  469. etm_ctx->trace_data[j].flags = 0;
  470. if ((trace_data[i] & 0x800) >> 11)
  471. {
  472. etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
  473. }
  474. if (etm_ctx->trace_data[j].pipestat == STAT_TR)
  475. {
  476. etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
  477. etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
  478. }
  479. /* trace word j+1 */
  480. etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
  481. etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
  482. etm_ctx->trace_data[j+1].flags = 0;
  483. if ((trace_data[i] & 0x800000) >> 23)
  484. {
  485. etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
  486. }
  487. if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
  488. {
  489. etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
  490. etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
  491. }
  492. j += 2;
  493. }
  494. else
  495. {
  496. /* trace word j */
  497. etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
  498. etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
  499. etm_ctx->trace_data[j].flags = 0;
  500. if ((trace_data[i] & 0x80000) >> 19)
  501. {
  502. etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
  503. }
  504. if (etm_ctx->trace_data[j].pipestat == STAT_TR)
  505. {
  506. etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
  507. etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
  508. }
  509. j += 1;
  510. }
  511. }
  512. free(trace_data);
  513. return ERROR_OK;
  514. }
  515. static int etb_start_capture(etm_context_t *etm_ctx)
  516. {
  517. etb_t *etb = etm_ctx->capture_driver_priv;
  518. u32 etb_ctrl_value = 0x1;
  519. u32 trigger_count;
  520. if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
  521. {
  522. if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
  523. {
  524. LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
  525. return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
  526. }
  527. etb_ctrl_value |= 0x2;
  528. }
  529. if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
  530. return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
  531. trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
  532. etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
  533. etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
  534. etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
  535. jtag_execute_queue();
  536. /* we're starting a new trace, initialize capture status */
  537. etm_ctx->capture_status = TRACE_RUNNING;
  538. return ERROR_OK;
  539. }
  540. static int etb_stop_capture(etm_context_t *etm_ctx)
  541. {
  542. etb_t *etb = etm_ctx->capture_driver_priv;
  543. reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
  544. etb_write_reg(etb_ctrl_reg, 0x0);
  545. jtag_execute_queue();
  546. /* trace stopped, just clear running flag, but preserve others */
  547. etm_ctx->capture_status &= ~TRACE_RUNNING;
  548. return ERROR_OK;
  549. }
  550. etm_capture_driver_t etb_capture_driver =
  551. {
  552. .name = "etb",
  553. .register_commands = etb_register_commands,
  554. .init = etb_init,
  555. .status = etb_status,
  556. .start_capture = etb_start_capture,
  557. .stop_capture = etb_stop_capture,
  558. .read_trace = etb_read_trace,
  559. };