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openocd/tcl/target/c100helper.tcl

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  1. 

  2. proc helpC100 {} {

  3.     echo "List of useful functions for C100 processor:"

  4.     echo "1)  reset init:        will set up your Telo board"

  5.     echo "2)  setupNOR:          will setup NOR access"

  6.     echo "3)  showNOR:           will show current NOR config registers for 16-bit, 16MB NOR"

  7.     echo "4)  setupGPIO:         will setup GPIOs for Telo board"

  8.     echo "5)  showGPIO:          will show current GPIO config registers"

  9.     echo "6)  highGPIO5:         will set GPIO5=NOR_addr22=1 to access upper 8MB"

  10.     echo "7)  lowGPIO5:          will set GPIO5=NOR_addr22=0 to access lower 8MB"

  11.     echo "8)  showAmbaClk:       will show current config registers for Amba Bus Clock"

  12.     echo "9)  setupAmbaClk:      will setup Amba Bus Clock=165MHz"

  13.     echo "10) showArmClk:        will show current config registers for Arm Bus Clock"

  14.     echo "11) setupArmClk:       will setup Amba Bus Clock=450MHz"

  15.     echo "12) ooma_board_detect: will show which version of Telo you have"

  16.     echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configureg"

  17.     echo "14) showDDR2:          will show DDR2 config registers"

  18.     echo "15) showWatchdog:      will show current register config for watchdog"

  19.     echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"

  20.     echo "17) bootNOR:           will boot Telo from NOR"

  21.     echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be confiured"

  22.     echo "19) putcUART0:         will print a character on UART0"

  23.     echo "20) putsUART0:         will print a string on UART0"

  24.     echo "21) trainDDR2:          will run DDR2 training program"

  25.     echo "22) flashUBOOT:        will prgram NOR sectors 0-3 with u-boot.bin"

  26. }

  27. 

  28. source [find mem_helper.tcl]

  29. 

  30. # read a 64-bit register (memory mapped)

  31. proc mr64bit {reg} {

  32.     set value ""

  33.     mem2array value 32 $reg 2

  34.     return $value

  35. }

  36. 

  37. 

  38. # write a 64-bit register (memory mapped)

  39. proc mw64bit {reg value} {

  40.     set high [expr $value >> 32]

  41.     set low  [expr $value & 0xffffffff]

  42.     #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]

  43.     mww $reg $low

  44.     mww [expr $reg+4] $high

  45. }

  46. 

  47. 

  48. proc showNOR {} {

  49.     echo "This is the current NOR setup"

  50.     set EX_CSEN_REG	    [regs EX_CSEN_REG ]

  51.     set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]

  52.     set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]

  53.     set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]

  54.     set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]

  55.     set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]

  56.     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]

  57.     set EX_MFSM_REG	    [regs EX_MFSM_REG ]

  58.     set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]

  59.     set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]

  60.     set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]

  61. 

  62.     echo [format "EX_CSEN_REG      (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]

  63.     echo [format "EX_CS0_SEG_REG   (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]

  64.     echo [format "EX_CS0_CFG_REG   (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]

  65.     echo [format "EX_CS0_TMG1_REG  (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]

  66.     echo [format "EX_CS0_TMG2_REG  (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]

  67.     echo [format "EX_CS0_TMG3_REG  (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]

  68.     echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]

  69.     echo [format "EX_MFSM_REG      (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]

  70.     echo [format "EX_CSFSM_REG     (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]

  71.     echo [format "EX_WRFSM_REG     (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]

  72.     echo [format "EX_RDFSM_REG     (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]

  73. }

  74. 

  75. 

  76. 

  77. proc showGPIO {} {

  78.     echo "This is the current GPIO register setup"

  79.     # GPIO outputs register

  80.     set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]

  81.     # GPIO Output Enable register

  82.     set GPIO_OE_REG		    [regs GPIO_OE_REG]

  83.     set GPIO_HI_INT_ENABLE_REG	    [regs GPIO_HI_INT_ENABLE_REG]

  84.     set GPIO_LO_INT_ENABLE_REG	    [regs GPIO_LO_INT_ENABLE_REG]

  85.     # GPIO input register

  86.     set GPIO_INPUT_REG		    [regs GPIO_INPUT_REG]

  87.     set APB_ACCESS_WS_REG	    [regs APB_ACCESS_WS_REG]

  88.     set MUX_CONF_REG		    [regs MUX_CONF_REG]

  89.     set SYSCONF_REG		    [regs SYSCONF_REG]

  90.     set GPIO_ARM_ID_REG		    [regs GPIO_ARM_ID_REG]

  91.     set GPIO_BOOTSTRAP_REG	    [regs GPIO_BOOTSTRAP_REG]

  92.     set GPIO_LOCK_REG		    [regs GPIO_LOCK_REG]

  93.     set GPIO_IOCTRL_REG		    [regs GPIO_IOCTRL_REG]

  94.     set GPIO_DEVID_REG		    [regs GPIO_DEVID_REG]

  95. 

  96.     echo [format "GPIO_OUTPUT_REG       (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]

  97.     echo [format "GPIO_OE_REG           (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]

  98.     echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]

  99.     echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]

  100.     echo [format "GPIO_INPUT_REG        (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]

  101.     echo [format "APB_ACCESS_WS_REG     (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]

  102.     echo [format "MUX_CONF_REG          (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]

  103.     echo [format "SYSCONF_REG           (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]

  104.     echo [format "GPIO_ARM_ID_REG       (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]

  105.     echo [format "GPIO_BOOTSTRAP_REG    (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]

  106.     echo [format "GPIO_LOCK_REG         (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]

  107.     echo [format "GPIO_IOCTRL_REG       (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]

  108.     echo [format "GPIO_DEVID_REG        (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]

  109. }

  110. 

  111. 

  112. 

  113. # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())

  114. proc showAmbaClk {} {

  115.     set CFG_REFCLKFREQ		     [config CFG_REFCLKFREQ]

  116.     set CLKCORE_AHB_CLK_CNTRL	     [regs CLKCORE_AHB_CLK_CNTRL]

  117.     set PLL_CLK_BYPASS	             [regs PLL_CLK_BYPASS]

  118. 

  119.     echo [format "CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]

  120.     mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1

  121.     # see if the PLL is in bypass mode

  122.     set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]

  123.     echo [format "PLL bypass bit: %d" $bypass]

  124.     if {$bypass == 1} {

  125. 	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]

  126.     } else {

  127. 	# nope, extract x,y,w and compute the PLL output freq.

  128. 	set x [expr ($value(0) & 0x0001F0000) >> 16]

  129. 	echo [format "x: %d" $x]

  130. 	set y [expr ($value(0) & 0x00000007F)]

  131. 	echo [format "y: %d" $y]

  132. 	set w [expr ($value(0) & 0x000000300) >> 8]

  133. 	echo [format "w: %d" $w]

  134. 	echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]

  135.     }

  136. }

  137. 

  138. 

  139. # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())

  140. # this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)

  141. proc setupAmbaClk {} {

  142.     set CLKCORE_PLL_STATUS           [regs CLKCORE_PLL_STATUS]

  143.     set CLKCORE_AHB_CLK_CNTRL	     [regs CLKCORE_AHB_CLK_CNTRL]

  144.     set ARM_PLL_BY_CTRL	    [regs ARM_PLL_BY_CTRL]

  145.     set ARM_AHB_BYP	    [regs ARM_AHB_BYP]

  146.     set PLL_DISABLE	    [regs PLL_DISABLE]

  147.     set PLL_CLK_BYPASS	    [regs PLL_CLK_BYPASS]

  148.     set AHB_PLL_BY_CTRL	    [regs AHB_PLL_BY_CTRL]

  149.     set DIV_BYPASS	    [regs DIV_BYPASS]

  150.     set AHBCLK_PLL_LOCK	    [regs AHBCLK_PLL_LOCK]

  151.     set CFG_REFCLKFREQ		 [config CFG_REFCLKFREQ]

  152.     set CONFIG_SYS_HZ_CLOCK      [config CONFIG_SYS_HZ_CLOCK]

  153.     set w    [config w_amba]

  154.     set x    [config x_amba]

  155.     set y    [config y_amba]

  156. 

  157.     echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]

  158.     #echo [format "setupAmbaClk: w= %d" $w]

  159.     #echo [format "setupAmbaClk: x= %d" $x]

  160.     #echo [format "setupAmbaClk: y= %d" $y]

  161.     # set PLL into BYPASS mode using MUX

  162.     mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0

  163.     # do an internal PLL bypass

  164.     mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0

  165.     # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)

  166.     # openocd smallest resolution is 1ms so, wait 1ms

  167.     sleep 1

  168.     # disable the PLL

  169.     mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0

  170.     # wait 1ms

  171.     sleep 1

  172.     # enable the PLL

  173.     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE

  174.     sleep 1

  175.     # set X, W and X

  176.     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF

  177.     mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0

  178.     # wait for PLL to lock

  179.     echo "Waiting for Amba PLL to lock"

  180.     while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }

  181.     # remove the internal PLL bypass

  182.     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL

  183.     # remove PLL from BYPASS mode using MUX

  184.     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS

  185. }

  186. 

  187. 

  188. # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())

  189. proc showArmClk {} {

  190.     set CFG_REFCLKFREQ		[config CFG_REFCLKFREQ]

  191.     set CLKCORE_ARM_CLK_CNTRL	[regs CLKCORE_ARM_CLK_CNTRL]

  192.     set PLL_CLK_BYPASS	        [regs PLL_CLK_BYPASS]

  193. 

  194.     echo [format "CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]

  195.     mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1

  196.     # see if the PLL is in bypass mode

  197.     set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]

  198.     echo [format "PLL bypass bit: %d" $bypass]

  199.     if {$bypass == 1} {

  200. 	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]

  201.     } else {

  202. 	# nope, extract x,y,w and compute the PLL output freq.

  203. 	set x [expr ($value(0) & 0x0001F0000) >> 16]

  204. 	echo [format "x: %d" $x]

  205. 	set y [expr ($value(0) & 0x00000007F)]

  206. 	echo [format "y: %d" $y]

  207. 	set w [expr ($value(0) & 0x000000300) >> 8]

  208. 	echo [format "w: %d" $w]

  209. 	echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]

  210.     }

  211. }

  212. 

  213. # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())

  214. # Arm Clock is used by two ARM1136 cores

  215. proc setupArmClk {} {

  216.     set CLKCORE_PLL_STATUS        [regs CLKCORE_PLL_STATUS]

  217.     set CLKCORE_ARM_CLK_CNTRL	  [regs CLKCORE_ARM_CLK_CNTRL]

  218.     set ARM_PLL_BY_CTRL	          [regs ARM_PLL_BY_CTRL]

  219.     set ARM_AHB_BYP	          [regs ARM_AHB_BYP]

  220.     set PLL_DISABLE	          [regs PLL_DISABLE]

  221.     set PLL_CLK_BYPASS	          [regs PLL_CLK_BYPASS]

  222.     set AHB_PLL_BY_CTRL	          [regs AHB_PLL_BY_CTRL]

  223.     set DIV_BYPASS	          [regs DIV_BYPASS]

  224.     set FCLK_PLL_LOCK	          [regs FCLK_PLL_LOCK]

  225.     set CFG_REFCLKFREQ		[config CFG_REFCLKFREQ]

  226.     set CFG_ARM_CLOCK		[config CFG_ARM_CLOCK]

  227.     set w    [config w_arm]

  228.     set x    [config x_arm]

  229.     set y    [config y_arm]

  230. 

  231.     echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]

  232.     #echo [format "setupArmClk: w= %d" $w]

  233.     #echo [format "setupArmaClk: x= %d" $x]

  234.     #echo [format "setupArmaClk: y= %d" $y]

  235.     # set PLL into BYPASS mode using MUX

  236.     mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0

  237.     # do an internal PLL bypass

  238.     mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0

  239.     # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)

  240.     # openocd smallest resolution is 1ms so, wait 1ms

  241.     sleep 1

  242.     # disable the PLL

  243.     mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0

  244.     # wait 1ms

  245.     sleep 1

  246.     # enable the PLL

  247.     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE

  248.     sleep 1

  249.     # set X, W and X

  250.     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF

  251.     mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0

  252.     # wait for PLL to lock

  253.     echo "Waiting for Amba PLL to lock"

  254.     while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }

  255.     # remove the internal PLL bypass

  256.     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL

  257.     # remove PLL from BYPASS mode using MUX

  258.     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS

  259. }

  260. 

  261. 

  262. 

  263. proc setupPLL {} {

  264.     echo "PLLs setup"

  265.     setupAmbaClk

  266.     setupArmClk

  267. }

  268. 

  269. # converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()

  270. proc setupDDR2 {} {

  271.     echo "Configuring DDR2"

  272. 

  273.     set MEMORY_BASE_ADDR	    [regs  MEMORY_BASE_ADDR]

  274.     set MEMORY_MAX_ADDR	            [regs  MEMORY_MAX_ADDR]

  275.     set MEMORY_CR 		    [regs  MEMORY_CR]

  276.     set BLOCK_RESET_REG		    [regs  BLOCK_RESET_REG]

  277.     set DDR_RST		            [regs  DDR_RST]

  278. 

  279.     # put DDR controller in reset (so that it is reset and correctly configured)

  280.     # this is only necessary if DDR was previously confiured

  281.     # and not reset.

  282.     mmw $BLOCK_RESET_REG 0x0 $DDR_RST

  283. 

  284.     set M [expr 1024 * 1024]

  285.     set DDR_SZ_1024M	[expr 1024 * $M]

  286.     set DDR_SZ_256M	[expr 256 * $M]

  287.     set DDR_SZ_128M	[expr 128 * $M]

  288.     set DDR_SZ_64M	[expr 64 * $M]

  289.     # ooma_board_detect returns DDR2 memory size

  290.     set tmp [ooma_board_detect]

  291.     if {$tmp == "128M"} {

  292. 	echo "DDR2 size 128MB"

  293. 	set ddr_size $DDR_SZ_128M

  294.     } elseif {$tmp == "256M"} {

  295. 	echo "DDR2 size 256MB"

  296. 	set ddr_size $DDR_SZ_256M

  297.     } else {

  298. 	echo "Don't know how to handle this DDR2 size?"

  299.     }

  300. 

  301.     # Memory setup register

  302.     mww $MEMORY_MAX_ADDR  [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]

  303.     # disable ROM remap

  304.     mww $MEMORY_CR 0x0

  305.     # Take DDR controller out of reset

  306.     mmw $BLOCK_RESET_REG $DDR_RST 0x0

  307.     # min. 20 ops delay

  308.     sleep 1

  309. 

  310.     # This will setup Denali DDR2 controller

  311.     if {$tmp == "128M"} {

  312. 	configureDDR2regs_128M

  313.     } elseif {$tmp == "256M"} {

  314. 	configureDDR2regs_256M

  315.     } else {

  316. 	echo "Don't know how to configure DDR2 setup?"

  317.     }

  318. }

  319. 

  320. 

  321. 

  322. proc showDDR2 {} {

  323. 

  324.     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]

  325.     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]

  326.     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]

  327.     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]

  328.     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]

  329.     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]

  330.     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]

  331.     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]

  332.     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]

  333.     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]

  334.     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]

  335.     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]

  336.     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]

  337.     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]

  338.     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]

  339.     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]

  340.     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]

  341.     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]

  342.     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]

  343.     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]

  344.     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]

  345. 

  346.     set tmp [mr64bit $DENALI_CTL_00_DATA]

  347.     echo [format "DENALI_CTL_00_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]

  348.     set tmp [mr64bit $DENALI_CTL_01_DATA]

  349.     echo [format "DENALI_CTL_01_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]

  350.     set tmp [mr64bit $DENALI_CTL_02_DATA]

  351.     echo [format "DENALI_CTL_02_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]

  352.     set tmp [mr64bit $DENALI_CTL_03_DATA]

  353.     echo [format "DENALI_CTL_03_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]

  354.     set tmp [mr64bit $DENALI_CTL_04_DATA]

  355.     echo [format "DENALI_CTL_04_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]

  356.     set tmp [mr64bit $DENALI_CTL_05_DATA]

  357.     echo [format "DENALI_CTL_05_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]

  358.     set tmp [mr64bit $DENALI_CTL_06_DATA]

  359.     echo [format "DENALI_CTL_06_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]

  360.     set tmp [mr64bit $DENALI_CTL_07_DATA]

  361.     echo [format "DENALI_CTL_07_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]

  362.     set tmp [mr64bit $DENALI_CTL_08_DATA]

  363.     echo [format "DENALI_CTL_08_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]

  364.     set tmp [mr64bit $DENALI_CTL_09_DATA]

  365.     echo [format "DENALI_CTL_09_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]

  366.     set tmp [mr64bit $DENALI_CTL_10_DATA]

  367.     echo [format "DENALI_CTL_10_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]

  368.     set tmp [mr64bit $DENALI_CTL_11_DATA]

  369.     echo [format "DENALI_CTL_11_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]

  370.     set tmp [mr64bit $DENALI_CTL_12_DATA]

  371.     echo [format "DENALI_CTL_12_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]

  372.     set tmp [mr64bit $DENALI_CTL_13_DATA]

  373.     echo [format "DENALI_CTL_13_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]

  374.     set tmp [mr64bit $DENALI_CTL_14_DATA]

  375.     echo [format "DENALI_CTL_14_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]

  376.     set tmp [mr64bit $DENALI_CTL_15_DATA]

  377.     echo [format "DENALI_CTL_15_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]

  378.     set tmp [mr64bit $DENALI_CTL_16_DATA]

  379.     echo [format "DENALI_CTL_16_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]

  380.     set tmp [mr64bit $DENALI_CTL_17_DATA]

  381.     echo [format "DENALI_CTL_17_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]

  382.     set tmp [mr64bit $DENALI_CTL_18_DATA]

  383.     echo [format "DENALI_CTL_18_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]

  384.     set tmp [mr64bit $DENALI_CTL_19_DATA]

  385.     echo [format "DENALI_CTL_19_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]

  386.     set tmp [mr64bit $DENALI_CTL_20_DATA]

  387.     echo [format "DENALI_CTL_20_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]

  388. 

  389. }

  390. 

  391. proc initC100 {} {

  392.     # this follows u-boot/cpu/arm1136/start.S

  393.     set GPIO_LOCK_REG		    [regs GPIO_LOCK_REG]

  394.     set GPIO_IOCTRL_REG		    [regs GPIO_IOCTRL_REG]

  395.     set GPIO_IOCTRL_VAL	            [regs GPIO_IOCTRL_VAL]

  396.     set APB_ACCESS_WS_REG           [regs APB_ACCESS_WS_REG]

  397.     set ASA_ARAM_BASEADDR	    [regs ASA_ARAM_BASEADDR]

  398.     set ASA_ARAM_TC_CR_REG	    [regs ASA_ARAM_TC_CR_REG]

  399.     set ASA_EBUS_BASEADDR	    [regs ASA_EBUS_BASEADDR]

  400.     set ASA_EBUS_TC_CR_REG	    [regs ASA_EBUS_TC_CR_REG]

  401.     set ASA_TC_REQIDMAEN	    [regs ASA_TC_REQIDMAEN]

  402.     set ASA_TC_REQTDMEN	            [regs ASA_TC_REQTDMEN]

  403.     set ASA_TC_REQIPSECUSBEN        [regs ASA_TC_REQIPSECUSBEN]

  404.     set ASA_TC_REQARM0EN	    [regs ASA_TC_REQARM0EN]

  405.     set ASA_TC_REQARM1EN	    [regs ASA_TC_REQARM1EN]

  406.     set ASA_TC_REQMDMAEN	    [regs ASA_TC_REQMDMAEN]

  407.     set INTC_ARM1_CONTROL_REG       [regs INTC_ARM1_CONTROL_REG]

  408. 

  409. 

  410.     # unlock writing to IOCTRL register

  411.     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL

  412.     # enable address lines A15-A21

  413.     mmw $GPIO_IOCTRL_REG 0xf 0x0

  414.     # set ARM into supervisor mode (SVC32)

  415.     # disable IRQ, FIQ

  416.     # Do I need this in JTAG mode?

  417.     # it really should be done as 'and ~0x1f | 0xd3 but

  418.     # openocd does not support this yet

  419.     reg cpsr 0xd3

  420.     #	/*

  421.     #	 * flush v4 I/D caches

  422.     #	 */

  423.     #	mov	r0, #0

  424.     #	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */

  425.     arm mcr 15 0 7 7 0 0x0

  426.     #	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

  427.     arm mcr 15 0 8 7 0 0x0

  428. 

  429.     #	/*

  430.     #	 * disable MMU stuff and caches

  431.     #	 */

  432.     #	mrc	p15, 0, r0, c1, c0, 0

  433.     arm mrc 15 0 1 0 0

  434.     #	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)

  435.     #	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)

  436.     #	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align

  437.     #	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache

  438.     #	orr	r0, r0, #0x00400000	@ set bit 22 (U)

  439.     #	mcr	p15, 0, r0, c1, c0, 0

  440.     arm mcr 15 0 1 0 0 0x401002

  441.     # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c

  442.     # APB init

  443.     #    	// Setting APB Bus Wait states to 1, set post write

  444.     #	(*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;

  445.     mww [expr $APB_ACCESS_WS_REG] 0x40

  446.     # AHB init

  447.     #	// enable all 6 masters for ARAM

  448.     mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0

  449.     #	// enable all 6 masters for EBUS

  450.     mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0

  451. 

  452.     # ARAM init

  453.     #	// disable pipeline mode in ARAM

  454.     # I don't think this is documented anywhere?

  455.     mww $INTC_ARM1_CONTROL_REG 0x1

  456.     # configure clocks

  457.     setupPLL

  458.     # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.

  459.     setupUART0

  460.     # enable cache

  461.     # ? (u-boot does nothing here)

  462.     # DDR2 memory init

  463.     setupDDR2

  464.     putsUART0 "C100 initialization complete.\n"

  465.     echo "C100 initialization complete."

  466. }

  467. 

  468. # show current state of watchdog timer

  469. proc showWatchdog {} {

  470.     set TIMER_WDT_HIGH_BOUND	[regs TIMER_WDT_HIGH_BOUND]

  471.     set TIMER_WDT_CONTROL	[regs TIMER_WDT_CONTROL]

  472.     set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]

  473. 

  474.     echo [format "TIMER_WDT_HIGH_BOUND    (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]

  475.     echo [format "TIMER_WDT_CONTROL       (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]

  476.     echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]

  477. }

  478. 

  479. # converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)

  480. # this will trigger watchdog reset

  481. # the sw. reset does not work on C100

  482. # watchdog reset effectively works as hw. reset

  483. proc reboot {} {

  484.     set TIMER_WDT_HIGH_BOUND	[regs TIMER_WDT_HIGH_BOUND]

  485.     set TIMER_WDT_CONTROL	[regs TIMER_WDT_CONTROL]

  486.     set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]

  487. 

  488.     # allow the counter to count to high value  before triggering

  489.     # this is because register writes are slow over JTAG and

  490.     # I don't want to miss the high_bound==curr_count condition

  491.     mww $TIMER_WDT_HIGH_BOUND  0xffffff

  492.     mww $TIMER_WDT_CURRENT_COUNT 0x0

  493.     echo "JTAG speed lowered to 100kHz"

  494.     adapter speed 100

  495.     mww $TIMER_WDT_CONTROL 0x1

  496.     # wait until the reset

  497.     echo -n "Waiting for watchdog to trigger..."

  498.     #while {[mrw $TIMER_WDT_CONTROL] == 1} {

  499.     #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]

  500.     #    sleep 1

  501.     #

  502.     #}

  503.     while {[c100.cpu curstate] != "running"} { sleep 1}

  504.     echo "done."

  505.     echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]

  506. }