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feroceon.c 24 KiB

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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Marvell Semiconductors, Inc. *
  3. * Written by Nicolas Pitre <nico@marvell.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. /*
  21. * Marvell Feroceon (88F5182, 88F5281) support.
  22. *
  23. * The Feroceon core mimics the ARM926 ICE interface with the following
  24. * differences:
  25. *
  26. * - the MOE (method of entry) reporting is not implemented
  27. *
  28. * - breakpoint/watchpoint comparator #1 is seemingly not implemented
  29. *
  30. * - due to a different pipeline implementation, some injected debug
  31. * instruction sequences have to be somewhat different
  32. *
  33. * Other issues:
  34. *
  35. * - asserting DBGRQ doesn't work if target is looping on the undef vector
  36. *
  37. * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
  38. * not at the top, and rather meaningless due to existing discrepencies
  39. *
  40. * - the DCC channel is half duplex (only one FIFO for both directions) with
  41. * seemingly no proper flow control.
  42. */
  43. #ifdef HAVE_CONFIG_H
  44. #include "config.h"
  45. #endif
  46. #include "arm926ejs.h"
  47. #include "jtag.h"
  48. #include "log.h"
  49. #include "arm_simulator.h"
  50. #include <stdlib.h>
  51. #include <string.h>
  52. int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  53. int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
  54. int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  55. int feroceon_quit();
  56. target_type_t feroceon_target =
  57. {
  58. .name = "feroceon",
  59. .poll = arm7_9_poll,
  60. .arch_state = arm926ejs_arch_state,
  61. .target_request_data = arm7_9_target_request_data,
  62. .halt = arm7_9_halt,
  63. .resume = arm7_9_resume,
  64. .step = arm7_9_step,
  65. .assert_reset = arm7_9_assert_reset,
  66. .deassert_reset = arm7_9_deassert_reset,
  67. .soft_reset_halt = arm926ejs_soft_reset_halt,
  68. .prepare_reset_halt = arm7_9_prepare_reset_halt,
  69. .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  70. .read_memory = arm7_9_read_memory,
  71. .write_memory = arm926ejs_write_memory,
  72. .bulk_write_memory = feroceon_bulk_write_memory,
  73. .checksum_memory = arm7_9_checksum_memory,
  74. .run_algorithm = armv4_5_run_algorithm,
  75. .add_breakpoint = arm7_9_add_breakpoint,
  76. .remove_breakpoint = arm7_9_remove_breakpoint,
  77. .add_watchpoint = arm7_9_add_watchpoint,
  78. .remove_watchpoint = arm7_9_remove_watchpoint,
  79. .register_commands = arm926ejs_register_commands,
  80. .target_command = feroceon_target_command,
  81. .init_target = feroceon_init_target,
  82. .quit = feroceon_quit
  83. };
  84. void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc)
  85. {
  86. armv4_5_common_t *armv4_5 = target->arch_info;
  87. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  88. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  89. /*
  90. * save r0 before using it and put system in ARM state
  91. * to allow common handling of ARM and THUMB debugging
  92. */
  93. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  94. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  95. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  96. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
  97. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  98. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  99. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
  100. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  101. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  102. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
  103. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
  104. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  105. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  106. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
  107. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  108. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  109. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(15), 0, NULL, 0);
  110. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  111. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  112. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  113. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  114. jtag_execute_queue();
  115. /*
  116. * fix program counter:
  117. * MOV R0, PC was the 10th instruction (+18)
  118. * reading PC in Thumb state gives address of instruction + 4
  119. */
  120. *pc -= 22;
  121. }
  122. void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
  123. {
  124. int i;
  125. armv4_5_common_t *armv4_5 = target->arch_info;
  126. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  127. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  128. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  129. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  130. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  131. for (i = 0; i <= 15; i++)
  132. if (mask & (1 << i))
  133. arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
  134. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  135. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  136. }
  137. void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
  138. {
  139. int i;
  140. armv4_5_common_t *armv4_5 = target->arch_info;
  141. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  142. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  143. int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
  144. u32 *buf_u32 = buffer;
  145. u16 *buf_u16 = buffer;
  146. u8 *buf_u8 = buffer;
  147. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  148. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  149. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  150. for (i = 0; i <= 15; i++)
  151. {
  152. if (mask & (1 << i)) {
  153. switch (size)
  154. {
  155. case 4:
  156. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
  157. break;
  158. case 2:
  159. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
  160. break;
  161. case 1:
  162. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
  163. break;
  164. }
  165. }
  166. }
  167. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  168. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  169. }
  170. void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr)
  171. {
  172. armv4_5_common_t *armv4_5 = target->arch_info;
  173. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  174. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  175. arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
  176. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  177. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  178. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  179. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  180. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  181. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  182. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
  183. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  184. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  185. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
  186. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  187. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  188. }
  189. void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
  190. {
  191. armv4_5_common_t *armv4_5 = target->arch_info;
  192. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  193. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  194. DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
  195. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
  196. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  197. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  198. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  199. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  200. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  201. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  202. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
  203. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  204. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  205. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  206. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  207. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  208. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  209. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
  210. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  211. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  212. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  213. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  214. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  215. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  216. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
  217. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  218. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  219. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  220. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  221. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  222. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  223. }
  224. void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
  225. {
  226. armv4_5_common_t *armv4_5 = target->arch_info;
  227. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  228. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  229. DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
  230. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
  231. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  232. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  233. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  234. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  235. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  236. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  237. }
  238. void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
  239. {
  240. int i;
  241. armv4_5_common_t *armv4_5 = target->arch_info;
  242. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  243. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  244. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  245. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  246. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  247. for (i = 0; i <= 15; i++)
  248. if (mask & (1 << i))
  249. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
  250. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  251. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  252. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  253. }
  254. void feroceon_branch_resume(target_t *target)
  255. {
  256. armv4_5_common_t *armv4_5 = target->arch_info;
  257. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  258. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  259. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  260. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  261. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  262. arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffff9, 0), 0, NULL, 0);
  263. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  264. /* need BYPASS before RESTART */
  265. jtag_add_end_state(TAP_RTI);
  266. arm_jtag_set_instr(jtag_info, 0xf, NULL);
  267. }
  268. void feroceon_branch_resume_thumb(target_t *target)
  269. {
  270. DEBUG("-");
  271. armv4_5_common_t *armv4_5 = target->arch_info;
  272. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  273. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  274. u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
  275. u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  276. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
  277. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  278. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  279. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc & ~3, NULL, 0);
  280. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  281. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  282. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  283. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  284. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  285. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  286. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  287. arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,r15,#1 */
  288. arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
  289. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  290. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  291. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 1), 0, NULL, 0);
  292. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  293. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  294. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0);
  295. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  296. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  297. pc = (pc & 2) >> 1;
  298. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7e9 + pc), 0, NULL, 0);
  299. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 1);
  300. /* need BYPASS before RESTART */
  301. jtag_add_end_state(TAP_RTI);
  302. arm_jtag_set_instr(jtag_info, 0xf, NULL);
  303. }
  304. int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
  305. {
  306. armv4_5_common_t *armv4_5 = target->arch_info;
  307. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  308. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  309. int err;
  310. arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
  311. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  312. err = arm7_9_execute_sys_speed(target);
  313. if (err != ERROR_OK)
  314. return err;
  315. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
  316. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  317. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  318. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, value, 0);
  319. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  320. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  321. return jtag_execute_queue();
  322. }
  323. int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
  324. {
  325. armv4_5_common_t *armv4_5 = target->arch_info;
  326. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  327. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  328. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
  329. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  330. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  331. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, value, NULL, 0);
  332. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  333. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  334. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  335. arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
  336. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  337. return arm7_9_execute_sys_speed(target);
  338. }
  339. void feroceon_enable_single_step(target_t *target)
  340. {
  341. armv4_5_common_t *armv4_5 = target->arch_info;
  342. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  343. u32 next_pc;
  344. /* calculate PC of next instruction */
  345. if (arm_simulate_step(target, &next_pc) != ERROR_OK)
  346. {
  347. u32 current_pc, current_opcode;
  348. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  349. target_read_u32(target, current_pc, &current_opcode);
  350. ERROR("BUG: couldn't calculate PC of next instruction, "
  351. "current opcode is 0x%8.8x", current_opcode);
  352. next_pc = current_pc;
  353. }
  354. arm7_9_restore_context(target);
  355. /* set a breakpoint there */
  356. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
  357. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0);
  358. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  359. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
  360. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
  361. }
  362. void feroceon_disable_single_step(target_t *target)
  363. {
  364. armv4_5_common_t *armv4_5 = target->arch_info;
  365. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  366. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
  367. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
  368. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
  369. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
  370. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
  371. }
  372. int feroceon_examine_debug_reason(target_t *target)
  373. {
  374. /* the MOE is not implemented */
  375. if (target->debug_reason != DBG_REASON_SINGLESTEP)
  376. {
  377. target->debug_reason = DBG_REASON_DBGRQ;
  378. }
  379. return ERROR_OK;
  380. }
  381. int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
  382. {
  383. armv4_5_common_t *armv4_5 = target->arch_info;
  384. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  385. enum armv4_5_state core_state = armv4_5->core_state;
  386. u32 x, flip, shift, save[7];
  387. int i;
  388. /*
  389. * We can't use the dcc flow control bits, so let's transfer data
  390. * with 31 bits and flip the MSB each time a new data word is sent.
  391. */
  392. static u32 dcc_code[] =
  393. {
  394. 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
  395. 0xe3a0301e, /* 1: mov r3, #30 */
  396. 0xe3a04002, /* mov r4, #2 */
  397. 0xee111e10, /* 2: mrc p14, 0, r1, c1, c0, 0 */
  398. 0xe1310005, /* teq r1, r5 */
  399. 0x0afffffc, /* beq 1b */
  400. 0xe1a05001, /* mov r5, r1 */
  401. 0xe1a01081, /* mov r1, r1, lsl #1 */
  402. 0xee112e10, /* 3: mrc p14, 0, r2, c1, c0, 0 */
  403. 0xe1320005, /* teq r2, r5 */
  404. 0x0afffffc, /* beq 3b */
  405. 0xe1a05002, /* mov r5, r2 */
  406. 0xe3c22102, /* bic r2, r2, #0x80000000 */
  407. 0xe1811332, /* orr r1, r1, r2, lsr r3 */
  408. 0xe2533001, /* subs r3, r3, #1 */
  409. 0xe4801004, /* str r1, [r0], #4 */
  410. 0xe1a01412, /* mov r1, r2, lsl r4 */
  411. 0xe2844001, /* add r4, r4, #1 */
  412. 0x4affffed, /* bmi 1b */
  413. 0xeafffff3, /* b 3b */
  414. };
  415. int dcc_size = sizeof(dcc_code);
  416. if (!arm7_9->dcc_downloads)
  417. return target->type->write_memory(target, address, 4, count, buffer);
  418. /* regrab previously allocated working_area, or allocate a new one */
  419. if (!arm7_9->dcc_working_area)
  420. {
  421. u8 dcc_code_buf[dcc_size];
  422. /* make sure we have a working area */
  423. if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
  424. {
  425. INFO("no working area available, falling back to memory writes");
  426. return target->type->write_memory(target, address, 4, count, buffer);
  427. }
  428. /* copy target instructions to target endianness */
  429. for (i = 0; i < dcc_size/4; i++)
  430. target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
  431. /* write DCC code to working area */
  432. target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
  433. }
  434. /* backup clobbered processor state */
  435. for (i = 0; i <= 5; i++)
  436. save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
  437. save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  438. /* set up target address in r0 */
  439. buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
  440. armv4_5->core_cache->reg_list[0].valid = 1;
  441. armv4_5->core_cache->reg_list[0].dirty = 1;
  442. armv4_5->core_state = ARMV4_5_STATE_ARM;
  443. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
  444. arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
  445. /* send data over */
  446. x = 0;
  447. flip = 0;
  448. shift = 1;
  449. for (i = 0; i < count; i++)
  450. {
  451. u32 y = target_buffer_get_u32(target, buffer);
  452. u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
  453. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
  454. x = y << (32 - shift);
  455. if (++shift >= 32 || i + 1 >= count)
  456. {
  457. z = (x >> 1) | (flip ^= 0x80000000);
  458. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
  459. x = 0;
  460. shift = 1;
  461. }
  462. buffer += 4;
  463. }
  464. target->type->halt(target);
  465. while (target->state != TARGET_HALTED)
  466. target->type->poll(target);
  467. /* restore target state */
  468. for (i = 0; i <= 5; i++)
  469. {
  470. buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, save[i]);
  471. armv4_5->core_cache->reg_list[i].valid = 1;
  472. armv4_5->core_cache->reg_list[i].dirty = 1;
  473. }
  474. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
  475. armv4_5->core_cache->reg_list[15].valid = 1;
  476. armv4_5->core_cache->reg_list[15].dirty = 1;
  477. armv4_5->core_state = core_state;
  478. return ERROR_OK;
  479. }
  480. int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  481. {
  482. armv4_5_common_t *armv4_5;
  483. arm7_9_common_t *arm7_9;
  484. arm9tdmi_init_target(cmd_ctx, target);
  485. armv4_5 = target->arch_info;
  486. arm7_9 = armv4_5->arch_info;
  487. /* the COMMS_CTRL bits are all contiguous */
  488. if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
  489. ERROR("unexpected Feroceon EICE version signature");
  490. arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
  491. arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
  492. arm7_9->has_monitor_mode = 1;
  493. /* vector catch reg is not initialized on reset */
  494. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
  495. /* clear monitor mode, enable comparators */
  496. embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
  497. jtag_execute_queue();
  498. buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
  499. buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
  500. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
  501. return ERROR_OK;
  502. }
  503. int feroceon_quit()
  504. {
  505. return ERROR_OK;
  506. }
  507. int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
  508. {
  509. int chain_pos;
  510. char *variant = NULL;
  511. armv4_5_common_t *armv4_5;
  512. arm7_9_common_t *arm7_9;
  513. arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
  514. if (argc < 4)
  515. {
  516. ERROR("'target arm926ejs' requires at least one additional argument");
  517. exit(-1);
  518. }
  519. chain_pos = strtoul(args[3], NULL, 0);
  520. if (argc >= 5)
  521. variant = args[4];
  522. DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
  523. arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
  524. armv4_5 = target->arch_info;
  525. arm7_9 = armv4_5->arch_info;
  526. /* override some insn sequence functions */
  527. arm7_9->change_to_arm = feroceon_change_to_arm;
  528. arm7_9->read_core_regs = feroceon_read_core_regs;
  529. arm7_9->read_core_regs_target_buffer = feroceon_read_core_regs_target_buffer;
  530. arm7_9->read_xpsr = feroceon_read_xpsr;
  531. arm7_9->write_xpsr = feroceon_write_xpsr;
  532. arm7_9->write_xpsr_im8 = feroceon_write_xpsr_im8;
  533. arm7_9->write_core_regs = feroceon_write_core_regs;
  534. arm7_9->branch_resume = feroceon_branch_resume;
  535. arm7_9->branch_resume_thumb = feroceon_branch_resume_thumb;
  536. /* must be implemented with only one comparator */
  537. arm7_9->enable_single_step = feroceon_enable_single_step;
  538. arm7_9->disable_single_step = feroceon_disable_single_step;
  539. /* MOE is not implemented */
  540. arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
  541. /* the standard ARM926 methods don't always work (don't ask...) */
  542. arm926ejs->read_cp15 = feroceon_read_cp15;
  543. arm926ejs->write_cp15 = feroceon_write_cp15;
  544. /* asserting DBGRQ won't win over the undef exception */
  545. arm7_9->use_dbgrq = 0;
  546. /* only one working comparator */
  547. arm7_9->wp_available = 1;
  548. arm7_9->wp1_used = -1;
  549. return ERROR_OK;
  550. }