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@@ -78,6 +78,10 @@ There are some known bugs to fix in JTAG adapter drivers: |
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- usbprog.c |
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- vsllink.c |
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- rlink/rlink.c |
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- bug: USBprog is broken with new tms sequence; it needs 7-clock cycles. |
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Fix promised from Peter Denison openwrt at marshadder.org |
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Workaround: use "tms_sequence long" @par |
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https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html |
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The following tasks have been suggeted for improving OpenOCD's JTAG |
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interface support: |
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@@ -131,10 +135,6 @@ Once the above are completed: |
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- general layer cleanup: @par |
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https://lists.berlios.de/pipermail/openocd-development/2009-May/006590.html |
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- bug: either USBprog is broken with new tms sequence or there is a general |
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problem with XScale and the new tms sequence. Workaround: use "tms_sequence long" |
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@par |
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https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html |
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- regression: "reset halt" between 729(works) and 788(fails): @par |
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https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html |
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- ARM7/9: |
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@@ -144,7 +144,7 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html |
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- add reset option to allow programming embedded ice while srst is asserted. |
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Some CPUs will gate the JTAG clock when srst is asserted and in this case, |
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it is necessary to program embedded ice and then assert srst afterwards. |
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- ARM923EJS: |
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- ARM926EJS: |
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- reset run/halt/step is not robust; needs testing to map out problems. |
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- ARM11 improvements (MB?) |
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- add support for asserting srst to reset the core. |
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