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@@ -77,6 +77,53 @@ target_to_armv7a(struct target *target) |
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armv4_5_common); |
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} |
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/* register offsets from armv7a.debug_base */ |
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/* See ARMv7a arch spec section C10.2 */ |
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#define CPUDBG_DIDR 0x000 |
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/* See ARMv7a arch spec section C10.3 */ |
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#define CPUDBG_WFAR 0x018 |
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/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */ |
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#define CPUDBG_DSCR 0x088 |
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#define CPUDBG_DRCR 0x090 |
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#define CPUDBG_PRCR 0x310 |
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#define CPUDBG_PRSR 0x314 |
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/* See ARMv7a arch spec section C10.4 */ |
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#define CPUDBG_DTRRX 0x080 |
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#define CPUDBG_ITR 0x084 |
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#define CPUDBG_DTRTX 0x08c |
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/* See ARMv7a arch spec section C10.5 */ |
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#define CPUDBG_BVR_BASE 0x100 |
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#define CPUDBG_BCR_BASE 0x140 |
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#define CPUDBG_WVR_BASE 0x180 |
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#define CPUDBG_WCR_BASE 0x1C0 |
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#define CPUDBG_VCR 0x01C |
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/* See ARMv7a arch spec section C10.6 */ |
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#define CPUDBG_OSLAR 0x300 |
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#define CPUDBG_OSLSR 0x304 |
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#define CPUDBG_OSSRR 0x308 |
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#define CPUDBG_ECR 0x024 |
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/* See ARMv7a arch spec section C10.7 */ |
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#define CPUDBG_DSCCR 0x028 |
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/* See ARMv7a arch spec section C10.8 */ |
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#define CPUDBG_AUTHSTATUS 0xFB8 |
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/* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */ |
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#define DSCR_CORE_HALTED 0 |
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#define DSCR_CORE_RESTARTED 1 |
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#define DSCR_EXT_INT_EN 13 |
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#define DSCR_HALT_DBG_MODE 14 |
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#define DSCR_MON_DBG_MODE 15 |
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#define DSCR_INSTR_COMP 24 |
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#define DSCR_DTR_TX_FULL 29 |
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#define DSCR_DTR_RX_FULL 30 |
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struct armv7a_algorithm |
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{ |
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int common_magic; |
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