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@@ -236,11 +236,25 @@ int cortex_a8_write_cp(target_t *target, uint32_t value, |
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uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) |
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{ |
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int retval; |
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uint32_t dscr; |
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/* get pointers to arch-specific information */ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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armv7a_common_t *armv7a = armv4_5->arch_info; |
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swjdp_common_t *swjdp = &armv7a->swjdp_info; |
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LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); |
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/* Check that DCCRX is not full */ |
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retval = mem_ap_read_atomic_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DSCR, &dscr); |
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if (dscr & (1 << DSCR_DTR_RX_FULL)) |
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{ |
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LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); |
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/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ |
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); |
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} |
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retval = mem_ap_write_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DTRRX, value); |
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/* Move DTRRX to r0 */ |
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@@ -311,12 +325,25 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r |
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{ |
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int retval = ERROR_OK; |
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uint8_t Rd = regnum&0xFF; |
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uint32_t dscr; |
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/* get pointers to arch-specific information */ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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armv7a_common_t *armv7a = armv4_5->arch_info; |
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swjdp_common_t *swjdp = &armv7a->swjdp_info; |
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LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); |
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/* Check that DCCRX is not full */ |
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retval = mem_ap_read_atomic_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DSCR, &dscr); |
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if (dscr & (1 << DSCR_DTR_RX_FULL)) |
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{ |
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LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); |
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/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ |
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); |
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} |
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if (Rd > 16) |
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return retval; |
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