Browse Source

- merged XScale branch back into trunk

- fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c
- free working area and register stuff if str7x block write algorithm failed
- check PC after exiting a target algorithm in armv4_5.c


git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
tags/v0.1.0
drath 17 years ago
parent
commit
4a5f45e87d
21 changed files with 5038 additions and 74 deletions
  1. +5
    -4
      src/flash/str7x.c
  2. +11
    -10
      src/helper/fileio.c
  3. +1
    -1
      src/jtag/amt_jtagaccel.c
  4. +1
    -1
      src/jtag/bitbang.c
  5. +1
    -1
      src/jtag/parport.c
  6. +1
    -1
      src/openocd.c
  7. +2
    -2
      src/target/Makefile.am
  8. +24
    -11
      src/target/arm_disassembler.c
  9. +19
    -17
      src/target/arm_disassembler.h
  10. +684
    -0
      src/target/arm_simulator.c
  11. +31
    -0
      src/target/arm_simulator.h
  12. +8
    -1
      src/target/armv4_5.c
  13. +10
    -0
      src/target/armv4_5.h
  14. +68
    -19
      src/target/target.c
  15. +8
    -6
      src/target/target.h
  16. +3175
    -0
      src/target/xscale.c
  17. +145
    -0
      src/target/xscale.h
  18. +7
    -0
      src/target/xscale/build.sh
  19. +718
    -0
      src/target/xscale/debug_handler.S
  20. +49
    -0
      src/target/xscale/debug_handler.cmd
  21. +70
    -0
      src/target/xscale/protocol.h

+ 5
- 4
src/flash/str7x.c View File

@@ -451,7 +451,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
u32 address = bank->base + offset;
reg_param_t reg_params[5];
armv4_5_algorithm_t armv4_5_info;
int retval;
int retval = ERROR_OK;
u32 str7x_flash_write_code[] = {
/* write: */
@@ -537,12 +537,13 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
if ((retval = target->type->run_algorithm(target, 0, NULL, 5, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
{
ERROR("error executing str7x flash write algorithm");
return ERROR_FLASH_OPERATION_FAILED;
break;
}
if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
{
return ERROR_FLASH_OPERATION_FAILED;
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
buffer += thisrun_count * 8;
@@ -558,7 +559,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
destroy_reg_param(&reg_params[3]);
destroy_reg_param(&reg_params[4]);
return ERROR_OK;
return retval;
}

int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)


+ 11
- 10
src/helper/fileio.c View File

@@ -242,22 +242,23 @@ int fileio_open(fileio_t *fileio, char *url, enum fileio_access access,
enum fileio_pri_type pri_type, void *pri_info, enum fileio_sec_type sec_type)
{
int retval = ERROR_OK;
if ((!url) || (strlen(url) < 3))
char *resource_identifier = NULL;

/* try to identify file location */
if ((resource_identifier = strstr(url, "bootp://")) && (resource_identifier == url))
{
snprintf(fileio->error_str, FILEIO_MAX_ERROR_STRING, "invalid file url");
return ERROR_INVALID_ARGUMENTS;
ERROR("bootp resource location isn't supported yet");
return ERROR_FILEIO_RESOURCE_TYPE_UNKNOWN;
}
if ((url[0] == '/') || (isalpha(url[0])) || ((url[1] == ':') && (url[2] == '\\')))
else if ((resource_identifier = strstr(url, "tftp://")) && (resource_identifier == url))
{
fileio->location = FILEIO_LOCAL;
ERROR("tftp resource location isn't supported yet");
return ERROR_FILEIO_RESOURCE_TYPE_UNKNOWN;
}
else
{
ERROR("couldn't identify resource location from URL '%s'", url);
snprintf(fileio->error_str, FILEIO_MAX_ERROR_STRING, "couldn't identify resource location from URL '%s'", url);
return ERROR_FILEIO_LOCATION_UNKNOWN;
/* default to local files */
fileio->location = FILEIO_LOCAL;
}
fileio->access = access;


+ 1
- 1
src/jtag/amt_jtagaccel.c View File

@@ -385,7 +385,7 @@ int amt_jtagaccel_execute_queue(void)
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
DEBUG("sleep", cmd->cmd.sleep->us);
DEBUG("sleep %i", cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;


+ 1
- 1
src/jtag/bitbang.c View File

@@ -248,7 +248,7 @@ int bitbang_execute_queue(void)
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
DEBUG("sleep", cmd->cmd.sleep->us);
DEBUG("sleep %i", cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;


+ 1
- 1
src/jtag/parport.c View File

@@ -375,7 +375,7 @@ int parport_init(void)
dataport = parport_port;
statusport = parport_port + 1;
DEBUG("requesting privileges for parallel port 0x%x...", dataport);
DEBUG("requesting privileges for parallel port 0x%lx...", dataport);
#if PARPORT_USE_GIVEIO == 1
if (parport_get_giveio_access() != 0)
#else /* PARPORT_USE_GIVEIO */


+ 1
- 1
src/openocd.c View File

@@ -18,7 +18,7 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-15 14:30 CET)"
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-28 18:30 CEST)"

#ifdef HAVE_CONFIG_H
#include "config.h"


+ 2
- 2
src/target/Makefile.am View File

@@ -3,7 +3,7 @@ METASOURCES = AUTO
noinst_LIBRARIES = libtarget.a
libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c etb.c
arm966e.c arm926ejs.c etb.c xscale.c arm_simulator.c
noinst_HEADERS = target.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h

+ 24
- 11
src/target/arm_disassembler.c View File

@@ -835,6 +835,9 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX%s r%i",
address, opcode, COND(opcode), Rm);
instruction->info.b_bl_bx_blx.reg_operand = Rm;
instruction->info.b_bl_bx_blx.target_address = -1;
}
/* Enhanced DSP add/subtracts */
@@ -1078,6 +1081,18 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
/* LSR encodes a shift by 32 bit as 0x0 */
if ((shift == 0x1) && (shift_imm == 0x0))
shift_imm = 0x20;
/* ASR encodes a shift by 32 bit as 0x0 */
if ((shift == 0x2) && (shift_imm == 0x0))
shift_imm = 0x20;

/* ROR by 32 bit is actually a RRX */
if ((shift == 0x3) && (shift_imm == 0x0))
shift = 0x4;
if ((shift_imm == 0x0) && (shift == 0x0))
{
snprintf(shifter_operand, 32, "r%i", Rm);
@@ -1090,22 +1105,19 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
}
else if (shift == 0x1) /* LSR */
{
if (shift_imm == 0x0)
shift_imm = 0x32;
snprintf(shifter_operand, 32, "r%i, LSR #0x%x", Rm, shift_imm);
}
else if (shift == 0x2) /* ASR */
{
if (shift_imm == 0x0)
shift_imm = 0x32;
snprintf(shifter_operand, 32, "r%i, ASR #0x%x", Rm, shift_imm);
}
else if (shift == 0x3) /* ROR or RRX */
else if (shift == 0x3) /* ROR */
{
snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
}
else if (shift == 0x4) /* RRX */
{
if (shift_imm == 0x0) /* RRX */
snprintf(shifter_operand, 32, "r%i, RRX", Rm);
else
snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
snprintf(shifter_operand, 32, "r%i, RRX", Rm);
}
}
}
@@ -1130,7 +1142,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
{
snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs);
}
else if (shift == 0x3) /* ROR or RRX */
else if (shift == 0x3) /* ROR */
{
snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs);
}
@@ -1159,7 +1171,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
return ERROR_OK;
}
int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
{
/* clear fields, to avoid confusion */
memset(instruction, 0, sizeof(arm_instruction_t));
@@ -1302,3 +1314,4 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
ERROR("should never reach this point");
return -1;
}


+ 19
- 17
src/target/arm_disassembler.h View File

@@ -126,28 +126,30 @@ typedef struct arm_b_bl_bx_blx_instr_s
u32 target_address;
} arm_b_bl_bx_blx_instr_t;

union arm_shifter_operand
{
struct {
u32 immediate;
} immediate;
struct {
u8 Rm;
u8 shift;
u8 shift_imm;
} immediate_shift;
struct {
u8 Rm;
u8 shift;
u8 Rs;
} register_shift;
};

typedef struct arm_data_proc_instr_s
{
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
u8 S;
u8 Rn;
u8 Rd;
union
{
struct {
u8 immediate;
} immediate;
struct {
u8 Rm;
u8 shift;
u8 shift_imm;
} immediate_shift;
struct {
u8 Rm;
u8 shift;
u8 Rs;
} register_shift;
} shifter_operand;
union arm_shifter_operand shifter_operand;
} arm_data_proc_instr_t;

typedef struct arm_load_store_instr_s
@@ -192,7 +194,7 @@ typedef struct arm_instruction_s

} arm_instruction_t;

extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);

#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])



+ 684
- 0
src/target/arm_simulator.c View File

@@ -0,0 +1,684 @@
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "target.h"
#include "armv4_5.h"
#include "arm_disassembler.h"
#include "arm_simulator.h"
#include "log.h"
#include "binarybuffer.h"

#include <string.h>

u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
{
u32 return_value;
shift_amount &= 0xff;
if (shift == 0x0) /* LSL */
{
if ((shift_amount > 0) && (shift_amount <= 32))
{
return_value = Rm << shift_amount;
*carry = Rm >> (32 - shift_amount);
}
else if (shift_amount > 32)
{
return_value = 0x0;
*carry = 0x0;
}
else /* (shift_amount == 0) */
{
return_value = Rm;
}
}
else if (shift == 0x1) /* LSR */
{
if ((shift_amount > 0) && (shift_amount <= 32))
{
return_value = Rm >> shift_amount;
*carry = (Rm >> (shift_amount - 1)) & 1;
}
else if (shift_amount > 32)
{
return_value = 0x0;
*carry = 0x0;
}
else /* (shift_amount == 0) */
{
return_value = Rm;
}
}
else if (shift == 0x2) /* ASR */
{
if ((shift_amount > 0) && (shift_amount <= 32))
{
/* right shifts of unsigned values are guaranteed to be logical (shift in zeroes)
* simulate an arithmetic shift (shift in signed-bit) by adding the signed-bit manually */
return_value = Rm >> shift_amount;
if (Rm & 0x80000000)
return_value |= 0xffffffff << (32 - shift_amount);
}
else if (shift_amount > 32)
{
if (Rm & 0x80000000)
{
return_value = 0xffffffff;
*carry = 0x1;
}
else
{
return_value = 0x0;
*carry = 0x0;
}
}
else /* (shift_amount == 0) */
{
return_value = Rm;
}
}
else if (shift == 0x3) /* ROR */
{
if (shift_amount == 0)
{
return_value = Rm;
}
else
{
shift_amount = shift_amount % 32;
return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount));
*carry = (return_value >> 31) & 0x1;
}
}
else if (shift == 0x4) /* RRX */
{
return_value = Rm >> 1;
if (*carry)
Rm |= 0x80000000;
*carry = Rm & 0x1;
}
return return_value;
}

u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, u8 *shifter_carry_out)
{
u32 return_value;
int instruction_size;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
instruction_size = 4;
else
instruction_size = 2;
*shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
if (variant == 0) /* 32-bit immediate */
{
return_value = shifter_operand.immediate.immediate;
}
else if (variant == 1) /* immediate shift */
{
u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32);
/* adjust RM in case the PC is being read */
if (shifter_operand.immediate_shift.Rm == 15)
Rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out);
}
else if (variant == 2) /* register shift */
{
u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32);
u32 Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32);
/* adjust RM in case the PC is being read */
if (shifter_operand.register_shift.Rm == 15)
Rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out);
}
else
{
ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff;
}
return return_value;
}

int pass_condition(u32 cpsr, u32 opcode)
{
switch ((opcode & 0xf0000000) >> 28)
{
case 0x0: /* EQ */
if (cpsr & 0x40000000)
return 1;
else
return 0;
case 0x1: /* NE */
if (!(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x2: /* CS */
if (cpsr & 0x20000000)
return 1;
else
return 0;
case 0x3: /* CC */
if (!(cpsr & 0x20000000))
return 1;
else
return 0;
case 0x4: /* MI */
if (cpsr & 0x80000000)
return 1;
else
return 0;
case 0x5: /* PL */
if (!(cpsr & 0x80000000))
return 1;
else
return 0;
case 0x6: /* VS */
if (cpsr & 0x10000000)
return 1;
else
return 0;
case 0x7: /* VC */
if (!(cpsr & 0x10000000))
return 1;
else
return 0;
case 0x8: /* HI */
if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x9: /* LS */
if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
return 1;
else
return 0;
case 0xa: /* GE */
if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xb: /* LT */
if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xc: /* GT */
if (!(cpsr & 0x40000000) &&
(((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
return 1;
else
return 0;
case 0xd: /* LE */
if ((cpsr & 0x40000000) &&
(((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000))))
return 1;
else
return 0;
case 0xe:
case 0xf:
return 1;
}
ERROR("BUG: should never get here");
return 0;
}

/* simulate a single step (if possible)
* if the dry_run_pc argument is provided, no state is changed,
* but the new pc is stored in the variable pointed at by the argument
*/
int arm_simulate_step(target_t *target, u32 *dry_run_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
u32 opcode;
u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
arm_instruction_t instruction;
int instruction_size;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
/* get current instruction, and identify it */
target_read_u32(target, current_pc, &opcode);
arm_evaluate_opcode(opcode, current_pc, &instruction);
instruction_size = 4;
}
else
{
/* TODO: add support for Thumb instruction set */
instruction_size = 2;
}
/* check condition code */
if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
{
if (dry_run_pc)
{
*dry_run_pc = current_pc + instruction_size;
}
else
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
}
return ERROR_OK;
}
/* examine instruction type */

/* branch instructions */
if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
{
u32 target;
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
{
target = instruction.info.b_bl_bx_blx.target_address;
}
else
{
target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
}
if (dry_run_pc)
{
*dry_run_pc = target;
return ERROR_OK;
}
else
{
if (instruction.type == ARM_B)
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
}
else if (instruction.type == ARM_BL)
{
u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
}
else if (instruction.type == ARM_BX)
{
if (target & 0x1)
{
armv4_5->core_state = ARMV4_5_STATE_THUMB;
}
else
{
armv4_5->core_state = ARMV4_5_STATE_ARM;
}
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
}
else if (instruction.type == ARM_BLX)
{
u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);

if (target & 0x1)
{
armv4_5->core_state = ARMV4_5_STATE_THUMB;
}
else
{
armv4_5->core_state = ARMV4_5_STATE_ARM;
}
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
}
return ERROR_OK;
}
}
/* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
{
u32 Rd, Rn, shifter_operand;
u8 C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
u8 carry_out;
Rd = 0x0;
Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);

/* adjust Rn in case the PC is being read */
if (instruction.info.data_proc.Rn == 15)
Rn += 2 * instruction_size;
if (instruction.type == ARM_AND)
Rd = Rn & shifter_operand;
else if (instruction.type == ARM_EOR)
Rd = Rn ^ shifter_operand;
else if (instruction.type == ARM_SUB)
Rd = Rn - shifter_operand;
else if (instruction.type == ARM_RSB)
Rd = shifter_operand - Rn;
else if (instruction.type == ARM_ADD)
Rd = Rn + shifter_operand;
else if (instruction.type == ARM_ADC)
Rd = Rn + shifter_operand + (C & 1);
else if (instruction.type == ARM_SBC)
Rd = Rn - shifter_operand - (C & 1) ? 0 : 1;
else if (instruction.type == ARM_RSC)
Rd = shifter_operand - Rn - (C & 1) ? 0 : 1;
else if (instruction.type == ARM_ORR)
Rd = Rn | shifter_operand;
else if (instruction.type == ARM_BIC)
Rd = Rn & ~(shifter_operand);
else if (instruction.type == ARM_MOV)
Rd = shifter_operand;
else if (instruction.type == ARM_MVN)
Rd = ~shifter_operand;
if (dry_run_pc)
{
if (instruction.info.data_proc.Rd == 15)
{
*dry_run_pc = Rd;
return ERROR_OK;
}
else
{
*dry_run_pc = current_pc + instruction_size;
}
return ERROR_OK;
}
else
{
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
WARNING("no updating of flags yet");

if (instruction.info.data_proc.Rd == 15)
return ERROR_OK;
}
}
/* compare instructions (CMP, CMN, TST, TEQ) */
else if ((instruction.type >= ARM_TST) && (instruction.type <= ARM_CMN))
{
if (dry_run_pc)
{
*dry_run_pc = current_pc + instruction_size;
return ERROR_OK;
}
else
{
WARNING("no updating of flags yet");
}
}
/* load register instructions */
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
{
u32 load_address, modified_address, load_value;
u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
/* adjust Rn in case the PC is being read */
if (instruction.info.load_store.Rn == 15)
Rn += 2 * instruction_size;
if (instruction.info.load_store.offset_mode == 0)
{
if (instruction.info.load_store.U)
modified_address = Rn + instruction.info.load_store.offset.offset;
else
modified_address = Rn - instruction.info.load_store.offset.offset;
}
else if (instruction.info.load_store.offset_mode == 1)
{
u32 offset;
u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.offset.reg.Rm).value, 0, 32);
u8 shift = instruction.info.load_store.offset.reg.shift;
u8 shift_imm = instruction.info.load_store.offset.reg.shift_imm;
u8 carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
offset = arm_shift(shift, Rm, shift_imm, &carry);
if (instruction.info.load_store.U)
modified_address = Rn + offset;
else
modified_address = Rn - offset;
}
else
{
ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
}
if (instruction.info.load_store.index_mode == 0)
{
/* offset mode
* we load from the modified address, but don't change the base address register */
load_address = modified_address;
modified_address = Rn;
}
else if (instruction.info.load_store.index_mode == 1)
{
/* pre-indexed mode
* we load from the modified address, and write it back to the base address register */
load_address = modified_address;
}
else if (instruction.info.load_store.index_mode == 2)
{
/* post-indexed mode
* we load from the unmodified address, and write the modified address back */
load_address = Rn;
}
target_read_u32(target, load_address, &load_value);
if (dry_run_pc)
{
if (instruction.info.load_store.Rd == 15)
{
*dry_run_pc = load_value;
return ERROR_OK;
}
else
{
*dry_run_pc = current_pc + instruction_size;
}
return ERROR_OK;
}
else
{
if ((instruction.info.load_store.index_mode == 1) ||
(instruction.info.load_store.index_mode == 2))
{
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32, modified_address);
}
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rd).value, 0, 32, load_value);
if (instruction.info.load_store.Rd == 15)
return ERROR_OK;
}
}
/* load multiple instruction */
else if (instruction.type == ARM_LDM)
{
int i;
u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32);
u32 load_values[16];
int bits_set = 0;

for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
bits_set++;
}
switch (instruction.info.load_store_multiple.addressing_mode)
{
case 0: /* Increment after */
Rn = Rn;
break;
case 1: /* Increment before */
Rn = Rn + 4;
break;
case 2: /* Decrement after */
Rn = Rn - (bits_set * 4) + 4;
break;
case 3: /* Decrement before */
Rn = Rn - (bits_set * 4);
break;
}

for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
target_read_u32(target, Rn, &load_values[i]);
Rn += 4;
}
}
if (dry_run_pc)
{
if (instruction.info.load_store_multiple.register_list & 0x8000)
{
*dry_run_pc = load_values[15];
return ERROR_OK;
}
}
else
{
enum armv4_5_mode mode = armv4_5->core_mode;
int update_cpsr = 0;

if (instruction.info.load_store_multiple.S)
{
if (instruction.info.load_store_multiple.register_list & 0x8000)
update_cpsr = 1;
else
mode = ARMV4_5_MODE_USR;
}

for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, i).value, 0, 32, load_values[i]);
}
}
if (update_cpsr)
{
u32 spsr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32);
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
}
/* base register writeback */
if (instruction.info.load_store_multiple.W)
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
if (instruction.info.load_store_multiple.register_list & 0x8000)
return ERROR_OK;
}
}
/* store multiple instruction */
else if (instruction.type == ARM_STM)
{
int i;

if (dry_run_pc)
{
/* STM wont affect PC (advance by instruction size */
}
else
{
u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32);
int bits_set = 0;
enum armv4_5_mode mode = armv4_5->core_mode;

for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
bits_set++;
}
if (instruction.info.load_store_multiple.S)
{
mode = ARMV4_5_MODE_USR;
}
switch (instruction.info.load_store_multiple.addressing_mode)
{
case 0: /* Increment after */
Rn = Rn;
break;
case 1: /* Increment before */
Rn = Rn + 4;
break;
case 2: /* Decrement after */
Rn = Rn - (bits_set * 4) + 4;
break;
case 3: /* Decrement before */
Rn = Rn - (bits_set * 4);
break;
}
for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
target_write_u32(target, Rn, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32));
Rn += 4;
}
}
/* base register writeback */
if (instruction.info.load_store_multiple.W)
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
}
}
else if (!dry_run_pc)
{
/* the instruction wasn't handled, but we're supposed to simulate it
*/
return ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED;
}
if (dry_run_pc)
{
*dry_run_pc = current_pc + instruction_size;
return ERROR_OK;
}
else
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
return ERROR_OK;
}
}

+ 31
- 0
src/target/arm_simulator.h View File

@@ -0,0 +1,31 @@
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef ARM_SIMULATOR_H
#define ARM_SIMULATOR_H

#include "target.h"
#include "types.h"

extern int arm_simulate_step(target_t *target, u32 *dry_run_pc);


#define ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED (-1000)

#endif /* ARM_SIMULATOR_H */

+ 8
- 1
src/target/armv4_5.c View File

@@ -442,7 +442,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
for (i = 0; i < count; i++)
{
target_read_u32(target, address, &opcode);
evaluate_opcode(opcode, address, &cur_instruction);
arm_evaluate_opcode(opcode, address, &cur_instruction);
command_print(cmd_ctx, "%s", cur_instruction.text);
address += (thumb) ? 2 : 4;
}
@@ -598,6 +598,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
}
}
if ((retval != ERROR_TARGET_TIMEOUT) &&
(buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point))
{
WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
}
breakpoint_remove(target, exit_point);
for (i = 0; i < num_mem_params; i++)


+ 10
- 0
src/target/armv4_5.h View File

@@ -213,6 +213,11 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
*/
#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))

/* Breakpoint instruction (ARMv5)
* Im: 16-bit immediate
*/
#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))


/* Thumb mode instructions
*/
@@ -266,4 +271,9 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
*/
#define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))

/* Breakpoint instruction (ARMv5) (Thumb state)
* Im: 8-bit immediate
*/
#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))

#endif /* ARMV4_5_H */

+ 68
- 19
src/target/target.c View File

@@ -79,6 +79,7 @@ extern target_type_t arm9tdmi_target;
extern target_type_t arm920t_target;
extern target_type_t arm966e_target;
extern target_type_t arm926ejs_target;
extern target_type_t xscale_target;

target_type_t *target_types[] =
{
@@ -88,6 +89,7 @@ target_type_t *target_types[] =
&arm720t_target,
&arm966e_target,
&arm926ejs_target,
&xscale_target,
NULL,
};

@@ -727,60 +729,107 @@ int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffe
return ERROR_OK;
}

void target_read_u32(struct target_s *target, u32 address, u32 *value)
int target_read_u32(struct target_s *target, u32 address, u32 *value)
{
u8 value_buf[4];

int retval = target->type->read_memory(target, address, 4, 1, value_buf);
target->type->read_memory(target, address, 4, 1, value_buf);
if (retval == ERROR_OK)
{
*value = target_buffer_get_u32(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
}
*value = target_buffer_get_u32(target, value_buf);

DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
return retval;
}

void target_read_u16(struct target_s *target, u32 address, u16 *value)
int target_read_u16(struct target_s *target, u32 address, u16 *value)
{
u8 value_buf[2];
target->type->read_memory(target, address, 2, 1, value_buf);
int retval = target->type->read_memory(target, address, 2, 1, value_buf);
*value = target_buffer_get_u16(target, value_buf);

DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
if (retval == ERROR_OK)
{
*value = target_buffer_get_u16(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
}
return retval;
}

void target_read_u8(struct target_s *target, u32 address, u8 *value)
int target_read_u8(struct target_s *target, u32 address, u8 *value)
{
target->type->read_memory(target, address, 1, 1, value);
int retval = target->type->read_memory(target, address, 1, 1, value);

DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
if (retval == ERROR_OK)
{
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
}
return retval;
}

void target_write_u32(struct target_s *target, u32 address, u32 value)
int target_write_u32(struct target_s *target, u32 address, u32 value)
{
int retval;
u8 value_buf[4];

DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);

target_buffer_set_u32(target, value_buf, value);
target->type->write_memory(target, address, 4, 1, value_buf);
if ((retval = target->type->write_memory(target, address, 4, 1, value_buf)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
}
return retval;
}

void target_write_u16(struct target_s *target, u32 address, u16 value)
int target_write_u16(struct target_s *target, u32 address, u16 value)
{
int retval;
u8 value_buf[2];
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);

target_buffer_set_u16(target, value_buf, value);
target->type->write_memory(target, address, 2, 1, value_buf);
if ((retval = target->type->write_memory(target, address, 2, 1, value_buf)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
}
return retval;
}

void target_write_u8(struct target_s *target, u32 address, u8 value)
int target_write_u8(struct target_s *target, u32 address, u8 value)
{
int retval;
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);

target->type->read_memory(target, address, 1, 1, &value);
if ((retval = target->type->read_memory(target, address, 1, 1, &value)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
}
return retval;
}

int target_register_user_commands(struct command_context_s *cmd_ctx)


+ 8
- 6
src/target/target.h View File

@@ -50,6 +50,8 @@ enum daemon_startup_mode
DAEMON_RESET, /* reset target (behaviour defined by reset_mode */
};

extern enum daemon_startup_mode startup_mode;

enum target_reset_mode
{
RESET_RUN = 0, /* reset and let target run */
@@ -222,12 +224,12 @@ extern u16 target_buffer_get_u16(target_t *target, u8 *buffer);
extern void target_buffer_set_u32(target_t *target, u8 *buffer, u32 value);
extern void target_buffer_set_u16(target_t *target, u8 *buffer, u16 value);

void target_read_u32(struct target_s *target, u32 address, u32 *value);
void target_read_u16(struct target_s *target, u32 address, u16 *value);
void target_read_u8(struct target_s *target, u32 address, u8 *value);
void target_write_u32(struct target_s *target, u32 address, u32 value);
void target_write_u16(struct target_s *target, u32 address, u16 value);
void target_write_u8(struct target_s *target, u32 address, u8 value);
int target_read_u32(struct target_s *target, u32 address, u32 *value);
int target_read_u16(struct target_s *target, u32 address, u16 *value);
int target_read_u8(struct target_s *target, u32 address, u8 *value);
int target_write_u32(struct target_s *target, u32 address, u32 value);
int target_write_u16(struct target_s *target, u32 address, u16 value);
int target_write_u8(struct target_s *target, u32 address, u8 value);

#define ERROR_TARGET_INVALID (-300)
#define ERROR_TARGET_INIT_FAILED (-301)


+ 3175
- 0
src/target/xscale.c
File diff suppressed because it is too large
View File


+ 145
- 0
src/target/xscale.h View File

@@ -0,0 +1,145 @@
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef XSCALE_H
#define XSCALE_H

#include "target.h"
#include "register.h"
#include "armv4_5.h"
#include "armv4_5_mmu.h"

#define XSCALE_COMMON_MAGIC 0x58534341

typedef struct xscale_jtag_s
{
/* position in JTAG scan chain */
int chain_pos;

/* IR length and instructions */
int ir_length;
u32 dbgrx;
u32 dbgtx;
u32 ldic;
u32 dcsr;
} xscale_jtag_t;

enum xscale_debug_reason
{
XSCALE_DBG_REASON_GENERIC,
XSCALE_DBG_REASON_RESET,
XSCALE_DBG_REASON_TB_FULL,
};

typedef struct xscale_common_s
{
int common_magic;
/* XScale registers (CP15, DBG) */
reg_cache_t *reg_cache;

/* pxa250, pxa255, pxa27x, ixp42x, ... */
char *variant;

xscale_jtag_t jtag_info;
/* current state of the debug handler */
int handler_installed;
int handler_running;
u32 handler_address;
/* target-endian buffers with exception vectors */
u32 low_vectors[8];
u32 high_vectors[8];
/* static low vectors */
u8 static_low_vectors_set; /* bit field with static vectors set by the user */
u8 static_high_vectors_set; /* bit field with static vectors set by the user */
u32 static_low_vectors[8];
u32 static_high_vectors[8];

/* DCache cleaning */
u32 cache_clean_address;
/* whether hold_rst and ext_dbg_break should be set */
int hold_rst;
int external_debug_break;
/* breakpoint / watchpoint handling */
int force_hw_bkpts;
int dbr_available;
int dbr0_used;
int dbr1_used;
int ibcr_available;
int ibcr0_used;
int ibcr1_used;
u32 arm_bkpt;
u16 thumb_bkpt;
u8 vector_catch;
int trace_buffer_enabled;
int trace_buffer_fill;
int arch_debug_reason;
/* armv4/5 common stuff */
armv4_5_common_t armv4_5_common;
/* MMU/Caches */
armv4_5_mmu_common_t armv4_5_mmu;
u32 cp15_control_reg;
/* possible future enhancements that go beyond XScale common stuff */
void *arch_info;
} xscale_common_t;

typedef struct xscale_reg_s
{
int dbg_handler_number;
target_t *target;
} xscale_reg_t;

enum
{
XSCALE_MAINID, /* 0 */
XSCALE_CACHETYPE,
XSCALE_CTRL,
XSCALE_AUXCTRL,
XSCALE_TTB,
XSCALE_DAC,
XSCALE_FSR,
XSCALE_FAR,
XSCALE_PID,
XSCALE_CPACCESS,
XSCALE_IBCR0, /* 10 */
XSCALE_IBCR1,
XSCALE_DBR0,
XSCALE_DBR1,
XSCALE_DBCON,
XSCALE_TBREG,
XSCALE_CHKPT0,
XSCALE_CHKPT1,
XSCALE_DCSR,
XSCALE_TX,
XSCALE_RX, /* 20 */
XSCALE_TXRXCTRL,
};

#endif /* XSCALE_H */

+ 7
- 0
src/target/xscale/build.sh View File

@@ -0,0 +1,7 @@
arm-none-eabi-gcc -c debug_handler.S -o debug_handler.o
arm-none-eabi-ld -EL -n -Tdebug_handler.cmd debug_handler.o -o debug_handler.out
arm-none-eabi-objcopy -O binary debug_handler.out debug_handler.bin

#arm-none-eabi-gcc -mbig-endian -c debug_handler.S -o debug_handler_be.o
#arm-none-eabi-ld -EB -n -Tdebug_handler.cmd debug_handler_be.o -o debug_handler_be.out
#arm-none-eabi-objcopy -O binary debug_handler_be.out debug_handler_be.bin

+ 718
- 0
src/target/xscale/debug_handler.S View File

@@ -0,0 +1,718 @@
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "protocol.h"

.text
.align 4

@ Disable thumb mode
.code 32

@ send word to debugger
.macro m_send_to_debugger reg
1:
mrc p14, 0, r15, c14, c0, 0
bvs 1b
mcr p14, 0, \reg, c8, c0, 0
.endm

@ receive word from debugger
.macro m_receive_from_debugger reg
1:
mrc p14, 0, r15, c14, c0, 0
bpl 1b
mrc p14, 0, \reg, c9, c0, 0
.endm

@ save register on debugger, small
.macro m_small_save_reg reg
mov r0, \reg
bl send_to_debugger
.endm

@ save status register on debugger, small
.macro m_small_save_psr
mrs r0, spsr
bl send_to_debugger
.endm

@ wait for all outstanding coprocessor accesses to complete
.macro m_cpwait
mrc p15, 0, r0, c2, c0, 0
mov r0, r0
sub pc, pc, #4
.endm

.global reset_handler
.global undef_handler
.global swi_handler
.global prefetch_abort_handler
.global data_abort_handler
.global irq_handler
.global fiq_handler

.section .part1 , "ax"

reset_handler:
@ read DCSR
mrc p14, 0, r13, c10, c0
@ check if global enable bit (GE) is set
ands r13, r13, #0x80000000
bne debug_handler

@ set global enable bit (GE)
mov r13, #0xc0000000
mcr p14, 0, r13, c10, c0

debug_handler:

@ save r0 without modifying other registers
m_send_to_debugger r0

@ save lr (program PC) without branching (use macro)
m_send_to_debugger r14

@ save non-banked registers and spsr (program CPSR)
m_small_save_reg r1
m_small_save_reg r2
m_small_save_reg r3
m_small_save_reg r4
m_small_save_reg r5
m_small_save_reg r6
m_small_save_reg r7
m_small_save_psr

mrs r0, spsr

@ prepare program PSR for debug use (clear Thumb, set I/F to disable interrupts)
bic r0, r0, #PSR_T
orr r0, r0, #(PSR_I | PSR_F)

@ examine mode bits
and r1, r0, #MODE_MASK
cmp r1, #MODE_USR

bne not_user_mode
@ replace USR mode with SYS
bic r0, r0, #MODE_MASK
orr r0, r0, #MODE_SYS

not_user_mode:

b save_banked_registers

@ command loop
@ wait for command from debugger, than execute desired function
get_command:
bl receive_from_debugger
@ 0x0n - register access
cmp r0, #0x0
beq get_banked_registers

cmp r0, #0x1
beq set_banked_registers

@ 0x1n - read memory
cmp r0, #0x11
beq read_byte

cmp r0, #0x12
beq read_half_word

cmp r0, #0x14
beq read_word

@ 0x2n - write memory
cmp r0, #0x21
beq write_byte
cmp r0, #0x22
beq write_half_word
cmp r0, #0x24
beq write_word

@ 0x3n - program execution
cmp r0, #0x30
beq resume

cmp r0, #0x31
beq resume_w_trace

@ 0x4n - coprocessor access
cmp r0, #0x40
beq read_cp_reg

cmp r0, #0x41
beq write_cp_reg

@ 0x5n - cache and mmu functions
cmp r0, #0x50
beq clean_d_cache

cmp r0, #0x51
beq invalidate_d_cache
cmp r0, #0x52
beq invalidate_i_cache

cmp r0, #0x53
beq cpwait

@ 0x6n - misc functions
cmp r0, #0x60
beq clear_sa

cmp r0, #0x61
beq read_trace_buffer
cmp r0, #0x62
beq clean_trace_buffer
@ return (back to get_command)
b get_command

@ ----

@ resume program execution
resume:
@ restore CPSR (SPSR_dbg)
bl receive_from_debugger
msr spsr, r0

@ restore registers (r7 - r0)
bl receive_from_debugger @ r7
mov r7, r0
bl receive_from_debugger @ r6
mov r6, r0
bl receive_from_debugger @ r5
mov r5, r0
bl receive_from_debugger @ r4
mov r4, r0
bl receive_from_debugger @ r3
mov r3, r0
bl receive_from_debugger @ r2
mov r2, r0
bl receive_from_debugger @ r1
mov r1, r0
bl receive_from_debugger @ r0

@ resume addresss
m_receive_from_debugger lr

@ branch back to application code, restoring CPSR
subs pc, lr, #0

@ get banked registers
@ receive mode bits from host, then run into save_banked_registers to
get_banked_registers:
bl receive_from_debugger

@ save banked registers
@ r0[4:0]: desired mode bits
save_banked_registers:
@ backup CPSR
mrs r7, cpsr
msr cpsr_c, r0
nop

@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ backup banked registers
m_send_to_debugger r8
m_send_to_debugger r9
m_send_to_debugger r10
m_send_to_debugger r11
m_send_to_debugger r12
m_send_to_debugger r13
m_send_to_debugger r14

@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_save

@ backup SPSR
mrs r0, spsr
m_send_to_debugger r0

no_spsr_to_save:

@ restore CPSR for SDS
msr cpsr_c, r7
nop

@ return
b get_command

@ ----


@ set banked registers
@ receive mode bits from host, then run into save_banked_registers to
set_banked_registers:
bl receive_from_debugger

@ restore banked registers
@ r0[4:0]: desired mode bits
restore_banked_registers:
@ backup CPSR
mrs r7, cpsr
msr cpsr_c, r0
nop

@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ set banked registers
m_receive_from_debugger r8
m_receive_from_debugger r9
m_receive_from_debugger r10
m_receive_from_debugger r11
m_receive_from_debugger r12
m_receive_from_debugger r13
m_receive_from_debugger r14

@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_restore

@ set SPSR
m_receive_from_debugger r0
msr spsr, r0

no_spsr_to_restore:

@ restore CPSR for SDS
msr cpsr_c, r7
nop

@ return
b get_command

@ ----

read_byte:
@ r2: address
bl receive_from_debugger
mov r2, r0

@ r1: count
bl receive_from_debugger
mov r1, r0

rb_loop:
ldrb r0, [r2], #1
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4

bl send_to_debugger

subs r1, r1, #1
bne rb_loop
@ return
b get_command

@ ----

read_half_word:
@ r2: address
bl receive_from_debugger
mov r2, r0

@ r1: count
bl receive_from_debugger
mov r1, r0

rh_loop:
ldrh r0, [r2], #2
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4

bl send_to_debugger

subs r1, r1, #1
bne rh_loop
@ return
b get_command

@ ----

read_word:
@ r2: address
bl receive_from_debugger
mov r2, r0

@ r1: count
bl receive_from_debugger
mov r1, r0

rw_loop:
ldr r0, [r2], #4
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4

bl send_to_debugger

subs r1, r1, #1
bne rw_loop
@ return
b get_command

@ ----

write_byte:
@ r2: address
bl receive_from_debugger
mov r2, r0

@ r1: count
bl receive_from_debugger
mov r1, r0

wb_loop:
bl receive_from_debugger
strb r0, [r2], #1

@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4

subs r1, r1, #1
bne wb_loop
@ return
b get_command

@ ----

write_half_word:
@ r2: address
bl receive_from_debugger
mov r2, r0

@ r1: count
bl receive_from_debugger
mov r1, r0

wh_loop:
bl receive_from_debugger
strh r0, [r2], #2

@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4

subs r1, r1, #1
bne wh_loop
@ return
b get_command

@ ----

write_word:
@ r2: address
bl receive_from_debugger
mov r2, r0

@ r1: count
bl receive_from_debugger
mov r1, r0

ww_loop:
bl receive_from_debugger
str r0, [r2], #4

@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4

subs r1, r1, #1
bne ww_loop
@ return
b get_command

@ ----

clear_sa:
@ read DCSR
mrc p14, 0, r0, c10, c0
@ clear SA bit
bic r0, r0, #0x20

@ write DCSR
mcr p14, 0, r0, c10, c0

@ return
b get_command

@ ----

clean_d_cache:
@ r0: cache clean area
bl receive_from_debugger
mov r1, #1024
clean_loop:
mcr p15, 0, r0, c7, c2, 5
add r0, r0, #32
subs r1, r1, #1
bne clean_loop

@ return
b get_command

@ ----

invalidate_d_cache:
mcr p15, 0, r0, c7, c6, 0

@ return
b get_command

@ ----

invalidate_i_cache:
mcr p15, 0, r0, c7, c5, 0

@ return
b get_command

@ ----

cpwait:
m_cpwait

@return
b get_command

@ ----

.section .part2 , "ax"

read_cp_reg:
@ requested cp register
bl receive_from_debugger

adr r1, read_cp_table
add pc, r1, r0, lsl #3

read_cp_table:
mrc p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID
b read_cp_reg_reply
mrc p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE
b read_cp_reg_reply
mrc p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL
b read_cp_reg_reply
mrc p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL
b read_cp_reg_reply
mrc p15, 0, r0, c2, c0, 0 @ XSCALE_TTB
b read_cp_reg_reply
mrc p15, 0, r0, c3, c0, 0 @ XSCALE_DAC
b read_cp_reg_reply
mrc p15, 0, r0, c5, c0, 0 @ XSCALE_FSR
b read_cp_reg_reply
mrc p15, 0, r0, c6, c0, 0 @ XSCALE_FAR
b read_cp_reg_reply
mrc p15, 0, r0, c13, c0, 0 @ XSCALE_PID
b read_cp_reg_reply
mrc p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS
b read_cp_reg_reply
mrc p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0
b read_cp_reg_reply
mrc p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1
b read_cp_reg_reply
mrc p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0
b read_cp_reg_reply
mrc p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1
b read_cp_reg_reply
mrc p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON
b read_cp_reg_reply
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
b read_cp_reg_reply
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0
b read_cp_reg_reply
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1
b read_cp_reg_reply
mrc p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR
b read_cp_reg_reply

read_cp_reg_reply:
bl send_to_debugger

@ return
b get_command

@ ----

write_cp_reg:
@ requested cp register
bl receive_from_debugger
mov r1, r0

@ value to be written
bl receive_from_debugger

adr r2, write_cp_table
add pc, r2, r1, lsl #3

write_cp_table:
mcr p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID (0x0)
b get_command
mcr p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE (0x1)
b get_command
mcr p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL (0x2)
b get_command
mcr p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL (0x3)
b get_command
mcr p15, 0, r0, c2, c0, 0 @ XSCALE_TTB (0x4)
b get_command
mcr p15, 0, r0, c3, c0, 0 @ XSCALE_DAC (0x5)
b get_command
mcr p15, 0, r0, c5, c0, 0 @ XSCALE_FSR (0x6)
b get_command
mcr p15, 0, r0, c6, c0, 0 @ XSCALE_FAR (0x7)
b get_command
mcr p15, 0, r0, c13, c0, 0 @ XSCALE_PID (0x8)
b get_command
mcr p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS (0x9)
b get_command
mcr p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0 (0xa)
b get_command
mcr p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1 (0xb)
b get_command
mcr p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0 (0xc)
b get_command
mcr p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1 (0xd)
b get_command
mcr p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON (0xe)
b get_command
mcr p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG (0xf)
b get_command
mcr p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
b get_command
mcr p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
b get_command
mcr p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR (0x12)
b get_command

@ ----

read_trace_buffer:

@ dump 256 entries from trace buffer
mov r1, #256
read_tb_loop:
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
bl send_to_debugger
subs r1, r1, #1
bne read_tb_loop

@ dump checkpoint register 0
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
bl send_to_debugger
@ dump checkpoint register 1
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
bl send_to_debugger

@ return
b get_command
@ ----

clean_trace_buffer:

@ clean 256 entries from trace buffer
mov r1, #256
clean_tb_loop:
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
subs r1, r1, #1
bne clean_tb_loop

@ return
b get_command
@ ----


@ resume program execution with trace buffer enabled
resume_w_trace:
@ restore CPSR (SPSR_dbg)
bl receive_from_debugger
msr spsr, r0

@ restore registers (r7 - r0)
bl receive_from_debugger @ r7
mov r7, r0
bl receive_from_debugger @ r6
mov r6, r0
bl receive_from_debugger @ r5
mov r5, r0
bl receive_from_debugger @ r4
mov r4, r0
bl receive_from_debugger @ r3
mov r3, r0
bl receive_from_debugger @ r2
mov r2, r0
bl receive_from_debugger @ r1
mov r1, r0
bl receive_from_debugger @ r0

@ resume addresss
m_receive_from_debugger lr

mrc p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
orr r13, r13, #1
mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR

@ branch back to application code, restoring CPSR
subs pc, lr, #0

undef_handler:
swi_handler:
prefetch_abort_handler:
data_abort_handler:
irq_handler:
fiq_handler:
1:
b 1b

send_to_debugger:
m_send_to_debugger r0
mov pc, lr

receive_from_debugger:
m_receive_from_debugger r0
mov pc, lr


+ 49
- 0
src/target/xscale/debug_handler.cmd View File

@@ -0,0 +1,49 @@
/* identify the Entry Point */
ENTRY(reset_handler)

/* specify the mini-ICache memory areas */
MEMORY
{
mini_icache_0 (x) : ORIGIN = 0x0, LENGTH = 1024 /* first part of mini icache (sets 0-31) */
mini_icache_1 (x) : ORIGIN = 0x400, LENGTH = 1024 /* second part of mini icache (sets 0-31) */
}

/* now define the output sections */
SECTIONS
{
.part1 :
{
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
*(.part1)
} >mini_icache_0

.part2 :
{
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
*(.part2)
FILL(0x0)
} >mini_icache_1

/DISCARD/ :
{
*(.text)