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@@ -159,97 +159,6 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre |
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return retval; |
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} |
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static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP, |
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uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) |
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{ |
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int retval; |
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struct armv7a_common *armv7a = target_to_armv7a(target); |
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struct swjdp_common *swjdp = &armv7a->swjdp_info; |
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uint32_t dscr = 0; |
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/* MRC(...) to read coprocessor register into r0 */ |
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2), |
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&dscr); |
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/* Move R0 to DTRTX */ |
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cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), |
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&dscr); |
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/* Read DCCTX */ |
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retval = mem_ap_read_atomic_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DTRTX, value); |
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return retval; |
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} |
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static int cortex_a8_write_cp(struct target *target, uint32_t value, |
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uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) |
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{ |
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int retval; |
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uint32_t dscr; |
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struct armv7a_common *armv7a = target_to_armv7a(target); |
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struct swjdp_common *swjdp = &armv7a->swjdp_info; |
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LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); |
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/* Check that DCCRX is not full */ |
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retval = mem_ap_read_atomic_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DSCR, &dscr); |
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if (dscr & (1 << DSCR_DTR_RX_FULL)) |
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{ |
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LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); |
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/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ |
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), |
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&dscr); |
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} |
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/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */ |
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retval = mem_ap_write_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DTRRX, value); |
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/* Move DTRRX to r0 */ |
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); |
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/* MCR(...) to write r0 to coprocessor */ |
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return cortex_a8_exec_opcode(target, |
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ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2), |
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&dscr); |
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} |
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static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2, |
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uint32_t CRn, uint32_t CRm, uint32_t *value) |
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{ |
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return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2); |
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} |
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static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2, |
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uint32_t CRn, uint32_t CRm, uint32_t value) |
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{ |
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return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2); |
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} |
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static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) |
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{ |
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if (cpnum!=15) |
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{ |
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LOG_ERROR("Only cp15 is supported"); |
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return ERROR_FAIL; |
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} |
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return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value); |
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} |
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static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) |
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{ |
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if (cpnum!=15) |
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{ |
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LOG_ERROR("Only cp15 is supported"); |
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return ERROR_FAIL; |
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} |
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return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value); |
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} |
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static int cortex_a8_dap_read_coreregister_u32(struct target *target, |
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uint32_t *value, int regnum) |
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{ |
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@@ -421,7 +330,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, |
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retval = mem_ap_read_atomic_u32(swjdp, |
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a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); |
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LOG_DEBUG("read DCC 0x%08" PRIx32, *data); |
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//LOG_DEBUG("read DCC 0x%08" PRIx32, *data); |
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if (dscr_p) |
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*dscr_p = dscr; |
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@@ -1612,9 +1521,6 @@ static int cortex_a8_init_arch_info(struct target *target, |
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cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; |
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armv4_5->arch_info = armv7a; |
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armv4_5->mrc = cortex_a8_mrc, |
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armv4_5->mcr = cortex_a8_mcr, |
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/* prepare JTAG information for the new target */ |
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cortex_a8->jtag_info.tap = tap; |
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cortex_a8->jtag_info.scann_size = 4; |
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@@ -1645,8 +1551,6 @@ static int cortex_a8_init_arch_info(struct target *target, |
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// armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches; |
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armv7a->armv4_5_mmu.has_tiny_pages = 1; |
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armv7a->armv4_5_mmu.mmu_enabled = 0; |
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armv7a->read_cp15 = cortex_a8_read_cp15; |
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armv7a->write_cp15 = cortex_a8_write_cp15; |
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// arm7_9->handle_target_request = cortex_a8_handle_target_request; |
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