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@@ -86,6 +86,12 @@ |
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#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ |
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(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) |
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/* Load Register Word Immediate Post-Index |
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* Rd: register to load |
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* Rn: base register |
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*/ |
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#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Load Register Halfword Immediate Post-Index |
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* Rd: register to load |
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* Rn: base register |
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@@ -98,6 +104,12 @@ |
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*/ |
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#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Store register Word Immediate Post-Index |
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* Rd: register to store |
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* Rn: base register |
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*/ |
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#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Store register Halfword Immediate Post-Index |
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* Rd: register to store |
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* Rn: base register |
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