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@@ -67,7 +67,8 @@ target_type_t cortexm3_target = |
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.assert_reset = cortex_m3_assert_reset, |
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.deassert_reset = cortex_m3_deassert_reset, |
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.soft_reset_halt = cortex_m3_soft_reset_halt, |
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.prepare_reset_halt = cortex_m3_prepare_reset_halt, |
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.get_gdb_reg_list = armv7m_get_gdb_reg_list, |
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.read_memory = cortex_m3_read_memory, |
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@@ -98,7 +99,7 @@ int cortex_m3_clear_halt(target_t *target) |
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); |
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/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ |
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ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); |
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DEBUG(" NVIC_DFSR 0x%x",cortex_m3->nvic_dfsr); |
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DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); |
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return ERROR_OK; |
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} |
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@@ -128,15 +129,13 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval |
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info; |
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u32 savedram; |
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int retvalue; |
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{ |
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ahbap_read_system_u32(swjdp, 0x20000000, &savedram); |
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ahbap_write_system_u32(swjdp, 0x20000000, opcode); |
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ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); |
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cortex_m3_single_step_core(target); |
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armv7m->core_cache->reg_list[15].dirty = 1; |
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retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); |
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} |
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ahbap_read_system_u32(swjdp, 0x20000000, &savedram); |
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ahbap_write_system_u32(swjdp, 0x20000000, opcode); |
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ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); |
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cortex_m3_single_step_core(target); |
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armv7m->core_cache->reg_list[15].dirty = 1; |
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retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); |
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return retvalue; |
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} |
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@@ -167,7 +166,7 @@ int cortex_m3_endreset_event(target_t *target) |
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DEBUG(" "); |
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/* Enable debug requests */ |
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ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); |
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if (!(cortex_m3->dcb_dhcsr&C_DEBUGEN)) |
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if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) |
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ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); |
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/* Enable trace and dwt */ |
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ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); |
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@@ -207,7 +206,7 @@ int cortex_m3_examine_debug_reason(target_t *target) |
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info; |
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info; |
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/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ |
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/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ |
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/* only check the debug reason if we don't know it already */ |
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if ((target->debug_reason != DBG_REASON_DBGRQ) |
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@@ -393,21 +392,21 @@ enum target_state cortex_m3_poll(target_t *target) |
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return TARGET_UNKNOWN; |
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} |
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if (cortex_m3->dcb_dhcsr&S_RESET_ST) |
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if (cortex_m3->dcb_dhcsr & S_RESET_ST) |
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{ |
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target->state = TARGET_RESET; |
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return target->state; |
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} |
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else if (target->state==TARGET_RESET) |
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else if (target->state == TARGET_RESET) |
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{ |
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/* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */ |
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DEBUG("Exit from reset with dcb_dhcsr %x", cortex_m3->dcb_dhcsr); |
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DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr); |
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cortex_m3_endreset_event(target); |
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target->state = TARGET_RUNNING; |
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prev_target_state = TARGET_RUNNING; |
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} |
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if (cortex_m3->dcb_dhcsr&S_HALT) |
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if (cortex_m3->dcb_dhcsr & S_HALT) |
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{ |
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target->state = TARGET_HALTED; |
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@@ -429,13 +428,13 @@ enum target_state cortex_m3_poll(target_t *target) |
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} |
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/* |
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if (cortex_m3->dcb_dhcsr&S_SLEEP) |
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if (cortex_m3->dcb_dhcsr & S_SLEEP) |
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target->state = TARGET_SLEEP; |
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*/ |
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/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ |
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); |
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DEBUG("dcb_dhcsr %x, nvic_dfsr %x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); |
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DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); |
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return target->state; |
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} |
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@@ -482,13 +481,13 @@ int cortex_m3_soft_reset_halt(struct target_s *target) |
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/* registers are now invalid */ |
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armv7m_invalidate_core_regs(target); |
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while (timeout<100) |
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while (timeout < 100) |
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{ |
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retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); |
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if (retval == ERROR_OK) |
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{ |
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); |
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if ((dcb_dhcsr&S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) |
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if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) |
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{ |
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DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); |
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cortex_m3_poll(target); |
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@@ -504,6 +503,23 @@ int cortex_m3_soft_reset_halt(struct target_s *target) |
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return ERROR_OK; |
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} |
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int cortex_m3_prepare_reset_halt(struct target_s *target) |
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{ |
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armv7m_common_t *armv7m = target->arch_info; |
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info; |
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info; |
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/* Enable debug requests */ |
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ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); |
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if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) |
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ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); |
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/* Enter debug state on reset, cf. end_reset_event() */ |
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ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); |
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return ERROR_OK; |
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} |
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int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) |
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{ |
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/* get pointers to arch-specific information */ |
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@@ -584,6 +600,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand |
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/* Set/Clear C_MASKINTS in a separate operation */ |
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if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS)) |
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ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT ); |
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/* Restart core */ |
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ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr ); |
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target->debug_reason = DBG_REASON_NOTHALTED; |
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@@ -667,7 +684,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle |
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int cortex_m3_assert_reset(target_t *target) |
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{ |
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int retval; |
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DEBUG("target->state: %s", target_state_strings[target->state]); |
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if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN) |
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@@ -730,7 +747,7 @@ int cortex_m3_assert_reset(target_t *target) |
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} |
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int cortex_m3_deassert_reset(target_t *target) |
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{ |
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{ |
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DEBUG("target->state: %s", target_state_strings[target->state]); |
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/* deassert reset lines */ |
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@@ -1265,7 +1282,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta |
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target_read_u32(target, CPUID, &cpuid); |
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if (((cpuid >> 4) & 0xc3f) == 0xc23) |
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DEBUG("CORTEX-M3 processor detected"); |
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DEBUG("cpuid %x", cpuid); |
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DEBUG("cpuid: 0x%8.8x", cpuid); |
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target_read_u32(target, NVIC_ICTR, &ictr); |
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cortex_m3->intlinesnum = (ictr & 0x1F) + 1; |
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@@ -1273,7 +1290,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta |
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for (i = 0; i < cortex_m3->intlinesnum; i++) |
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{ |
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target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); |
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DEBUG("interrupt enable[%i] = 0x%x", i, cortex_m3->intsetenable[i]); |
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DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); |
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} |
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/* Setup FPB */ |
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@@ -1282,7 +1299,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta |
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cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; |
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cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; |
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cortex_m3->fp_code_available = cortex_m3->fp_num_code; |
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cortex_m3->fp_comparator_list=calloc(cortex_m3->fp_num_code+cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); |
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cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); |
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for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) |
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{ |
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cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; |
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