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91 lines
2.6 KiB

  1. if { [info exists CHIPNAME] } {
  2. set _CHIPNAME $CHIPNAME
  3. } else {
  4. set _CHIPNAME pic32mx
  5. }
  6. if { [info exists ENDIAN] } {
  7. set _ENDIAN $ENDIAN
  8. } else {
  9. set _ENDIAN little
  10. }
  11. if { [info exists CPUTAPID] } {
  12. set _CPUTAPID $CPUTAPID
  13. } else {
  14. set _CPUTAPID 0x30938053
  15. }
  16. # default working area is 16384
  17. if { [info exists WORKAREASIZE] } {
  18. set _WORKAREASIZE $WORKAREASIZE
  19. } else {
  20. set _WORKAREASIZE 0x4000
  21. }
  22. adapter_nsrst_delay 100
  23. jtag_ntrst_delay 100
  24. #jtag scan chain
  25. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  26. jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
  27. set _TARGETNAME $_CHIPNAME.cpu
  28. target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
  29. #
  30. # At reset the pic32mx does not allow code execution from RAM
  31. # we have to setup the BMX registers to allow this.
  32. # One limitation is that we loose the first 2k of RAM.
  33. #
  34. global _PIC32MX_DATASIZE
  35. global _WORKAREASIZE
  36. set _PIC32MX_DATASIZE 0x800
  37. set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
  38. $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
  39. $_TARGETNAME configure -event reset-init {
  40. #
  41. # from reset the pic32 cannot execute code in ram - enable ram execution
  42. # minimum offset from start of ram is 2k
  43. #
  44. global _PIC32MX_DATASIZE
  45. global _WORKAREASIZE
  46. # BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6
  47. mww 0xbf882000 0x001f0000
  48. # BMXDKPBA: 2k kernel data @ 0xa0000000
  49. mww 0xbf882010 $_PIC32MX_DATASIZE
  50. # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
  51. mww 0xbf882020 $_WORKAREASIZE
  52. # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
  53. mww 0xbf882030 $_WORKAREASIZE
  54. #
  55. # Set system clock to 8Mhz if the default clock configuration is set
  56. #
  57. # SYSKEY register, make sure OSCCON is locked
  58. mww 0xbf80f230 0x0
  59. # SYSKEY register, write unlock sequence
  60. mww 0xbf80f230 0xaa996655
  61. mww 0xbf80f230 0x556699aa
  62. # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
  63. mww 0xbf80f004 0x07000000
  64. # SYSKEY register, relock OSCCON
  65. mww 0xbf80f230 0x0
  66. }
  67. set _FLASHNAME $_CHIPNAME.flash0
  68. flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  69. # add virtual banks for kseg0 and kseg1
  70. flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  71. flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  72. set _FLASHNAME $_CHIPNAME.flash1
  73. flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
  74. # add virtual banks for kseg0 and kseg1
  75. flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
  76. flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME