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  1. # script for stm32f3x family
  2. #
  3. # stm32 devices support both JTAG and SWD transports.
  4. #
  5. source [find target/swj-dp.tcl]
  6. source [find mem_helper.tcl]
  7. if { [info exists CHIPNAME] } {
  8. set _CHIPNAME $CHIPNAME
  9. } else {
  10. set _CHIPNAME stm32f3x
  11. }
  12. set _ENDIAN little
  13. # Work-area is a space in RAM used for flash programming
  14. # By default use 16kB
  15. if { [info exists WORKAREASIZE] } {
  16. set _WORKAREASIZE $WORKAREASIZE
  17. } else {
  18. set _WORKAREASIZE 0x4000
  19. }
  20. # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  21. #
  22. # Since we may be running of an RC oscilator, we crank down the speed a
  23. # bit more to be on the safe side. Perhaps superstition, but if are
  24. # running off a crystal, we can run closer to the limit. Note
  25. # that there can be a pretty wide band where things are more or less stable.
  26. adapter_khz 1000
  27. adapter_nsrst_delay 100
  28. if {[using_jtag]} {
  29. jtag_ntrst_delay 100
  30. }
  31. #jtag scan chain
  32. if { [info exists CPUTAPID] } {
  33. set _CPUTAPID $CPUTAPID
  34. } else {
  35. if { [using_jtag] } {
  36. # See STM Document RM0316
  37. # Section 29.6.3 - corresponds to Cortex-M4 r0p1
  38. set _CPUTAPID 0x4ba00477
  39. } {
  40. set _CPUTAPID 0x2ba01477
  41. }
  42. }
  43. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  44. if { [info exists BSTAPID] } {
  45. set _BSTAPID $BSTAPID
  46. } else {
  47. # STM Document RM0316 rev 5 for STM32F302/303 B/C size
  48. set _BSTAPID1 0x06422041
  49. # STM Document RM0313 rev 3 for STM32F37x
  50. set _BSTAPID2 0x06432041
  51. # STM Document RM364 rev 1 for STM32F334
  52. set _BSTAPID3 0x06438041
  53. # STM Document RM316 rev 5 for STM32F303 6/8 size
  54. # STM Document RM365 rev 3 for STM32F302 6/8 size
  55. # STM Document RM366 rev 2 for STM32F301 6/8 size
  56. set _BSTAPID4 0x06439041
  57. # STM Document RM016 rev 5 for STM32F303 D/E size
  58. set _BSTAPID5 0x06446041
  59. }
  60. if {[using_jtag]} {
  61. swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  62. -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  63. -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
  64. }
  65. set _TARGETNAME $_CHIPNAME.cpu
  66. target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  67. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  68. set _FLASHNAME $_CHIPNAME.flash
  69. flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  70. reset_config srst_nogate
  71. if {![using_hla]} {
  72. # if srst is not fitted use SYSRESETREQ to
  73. # perform a soft reset
  74. cortex_m reset_config sysresetreq
  75. }
  76. proc stm32f3x_default_reset_start {} {
  77. # Reset clock is HSI (8 MHz)
  78. adapter_khz 1000
  79. }
  80. proc stm32f3x_default_examine_end {} {
  81. # Enable debug during low power modes (uses more power)
  82. mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  83. # Stop watchdog counters during halt
  84. mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
  85. }
  86. proc stm32f3x_default_reset_init {} {
  87. # Configure PLL to boost clock to HSI x 8 (64 MHz)
  88. mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
  89. mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
  90. mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
  91. sleep 10 ;# Wait for PLL to lock
  92. mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
  93. # Boost JTAG frequency
  94. adapter_khz 8000
  95. }
  96. # Default hooks
  97. $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
  98. $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
  99. $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
  100. $_TARGETNAME configure -event trace-config {
  101. # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  102. # change this value accordingly to configure trace pins
  103. # assignment
  104. mmw 0xe0042004 0x00000020 0
  105. }