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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * Copyright (C) 2007,2008 Øyvind Harboe *
  12. * oyvind.harboe@zylin.com *
  13. * *
  14. * This program is free software; you can redistribute it and/or modify *
  15. * it under the terms of the GNU General Public License as published by *
  16. * the Free Software Foundation; either version 2 of the License, or *
  17. * (at your option) any later version. *
  18. * *
  19. * This program is distributed in the hope that it will be useful, *
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  22. * GNU General Public License for more details. *
  23. * *
  24. * You should have received a copy of the GNU General Public License *
  25. * along with this program; if not, write to the *
  26. * Free Software Foundation, Inc., *
  27. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  28. * *
  29. * ARMv7-M Architecture, Application Level Reference Manual *
  30. * ARM DDI 0405C (September 2008) *
  31. * *
  32. ***************************************************************************/
  33. #ifdef HAVE_CONFIG_H
  34. #include "config.h"
  35. #endif
  36. #include "breakpoints.h"
  37. #include "armv7m.h"
  38. #include "algorithm.h"
  39. #include "register.h"
  40. #if 0
  41. #define _DEBUG_INSTRUCTION_EXECUTION_
  42. #endif
  43. static char *armv7m_exception_strings[] = {
  44. "", "Reset", "NMI", "HardFault",
  45. "MemManage", "BusFault", "UsageFault", "RESERVED",
  46. "RESERVED", "RESERVED", "RESERVED", "SVCall",
  47. "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  48. };
  49. /* PSP is used in some thread modes */
  50. const int armv7m_psp_reg_map[17] = {
  51. ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
  52. ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
  53. ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
  54. ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
  55. ARMV7M_xPSR,
  56. };
  57. /* MSP is used in handler and some thread modes */
  58. const int armv7m_msp_reg_map[17] = {
  59. ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
  60. ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
  61. ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
  62. ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
  63. ARMV7M_xPSR,
  64. };
  65. #ifdef ARMV7_GDB_HACKS
  66. uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  67. struct reg armv7m_gdb_dummy_cpsr_reg = {
  68. .name = "GDB dummy cpsr register",
  69. .value = armv7m_gdb_dummy_cpsr_value,
  70. .dirty = 0,
  71. .valid = 1,
  72. .size = 32,
  73. .arch_info = NULL,
  74. };
  75. #endif
  76. /*
  77. * These registers are not memory-mapped. The ARMv7-M profile includes
  78. * memory mapped registers too, such as for the NVIC (interrupt controller)
  79. * and SysTick (timer) modules; those can mostly be treated as peripherals.
  80. *
  81. * The ARMv6-M profile is almost identical in this respect, except that it
  82. * doesn't include basepri or faultmask registers.
  83. */
  84. static const struct {
  85. unsigned id;
  86. const char *name;
  87. unsigned bits;
  88. } armv7m_regs[] = {
  89. { ARMV7M_R0, "r0", 32 },
  90. { ARMV7M_R1, "r1", 32 },
  91. { ARMV7M_R2, "r2", 32 },
  92. { ARMV7M_R3, "r3", 32 },
  93. { ARMV7M_R4, "r4", 32 },
  94. { ARMV7M_R5, "r5", 32 },
  95. { ARMV7M_R6, "r6", 32 },
  96. { ARMV7M_R7, "r7", 32 },
  97. { ARMV7M_R8, "r8", 32 },
  98. { ARMV7M_R9, "r9", 32 },
  99. { ARMV7M_R10, "r10", 32 },
  100. { ARMV7M_R11, "r11", 32 },
  101. { ARMV7M_R12, "r12", 32 },
  102. { ARMV7M_R13, "sp", 32 },
  103. { ARMV7M_R14, "lr", 32 },
  104. { ARMV7M_PC, "pc", 32 },
  105. { ARMV7M_xPSR, "xPSR", 32 },
  106. { ARMV7M_MSP, "msp", 32 },
  107. { ARMV7M_PSP, "psp", 32 },
  108. { ARMV7M_PRIMASK, "primask", 1 },
  109. { ARMV7M_BASEPRI, "basepri", 8 },
  110. { ARMV7M_FAULTMASK, "faultmask", 1 },
  111. { ARMV7M_CONTROL, "control", 2 },
  112. };
  113. #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
  114. /**
  115. * Restores target context using the cache of core registers set up
  116. * by armv7m_build_reg_cache(), calling optional core-specific hooks.
  117. */
  118. int armv7m_restore_context(struct target *target)
  119. {
  120. int i;
  121. struct armv7m_common *armv7m = target_to_armv7m(target);
  122. struct reg_cache *cache = armv7m->arm.core_cache;
  123. LOG_DEBUG(" ");
  124. if (armv7m->pre_restore_context)
  125. armv7m->pre_restore_context(target);
  126. for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
  127. if (cache->reg_list[i].dirty) {
  128. uint32_t value = buf_get_u32(cache->reg_list[i].value, 0, 32);
  129. armv7m->arm.write_core_reg(target, &cache->reg_list[i], i, ARM_MODE_ANY, value);
  130. }
  131. }
  132. return ERROR_OK;
  133. }
  134. /* Core state functions */
  135. /**
  136. * Maps ISR number (from xPSR) to name.
  137. * Note that while names and meanings for the first sixteen are standardized
  138. * (with zero not a true exception), external interrupts are only numbered.
  139. * They are assigned by vendors, which generally assign different numbers to
  140. * peripherals (such as UART0 or a USB peripheral controller).
  141. */
  142. char *armv7m_exception_string(int number)
  143. {
  144. static char enamebuf[32];
  145. if ((number < 0) | (number > 511))
  146. return "Invalid exception";
  147. if (number < 16)
  148. return armv7m_exception_strings[number];
  149. sprintf(enamebuf, "External Interrupt(%i)", number - 16);
  150. return enamebuf;
  151. }
  152. static int armv7m_get_core_reg(struct reg *reg)
  153. {
  154. int retval;
  155. struct arm_reg *armv7m_reg = reg->arch_info;
  156. struct target *target = armv7m_reg->target;
  157. struct arm *arm = target_to_arm(target);
  158. if (target->state != TARGET_HALTED)
  159. return ERROR_TARGET_NOT_HALTED;
  160. retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode);
  161. return retval;
  162. }
  163. static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
  164. {
  165. struct arm_reg *armv7m_reg = reg->arch_info;
  166. struct target *target = armv7m_reg->target;
  167. uint32_t value = buf_get_u32(buf, 0, 32);
  168. if (target->state != TARGET_HALTED)
  169. return ERROR_TARGET_NOT_HALTED;
  170. buf_set_u32(reg->value, 0, 32, value);
  171. reg->dirty = 1;
  172. reg->valid = 1;
  173. return ERROR_OK;
  174. }
  175. static int armv7m_read_core_reg(struct target *target, struct reg *r,
  176. int num, enum arm_mode mode)
  177. {
  178. uint32_t reg_value;
  179. int retval;
  180. struct arm_reg *armv7m_core_reg;
  181. struct armv7m_common *armv7m = target_to_armv7m(target);
  182. assert(num < (int)armv7m->arm.core_cache->num_regs);
  183. armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
  184. retval = armv7m->load_core_reg_u32(target,
  185. armv7m_core_reg->num, &reg_value);
  186. buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
  187. armv7m->arm.core_cache->reg_list[num].valid = 1;
  188. armv7m->arm.core_cache->reg_list[num].dirty = 0;
  189. return retval;
  190. }
  191. static int armv7m_write_core_reg(struct target *target, struct reg *r,
  192. int num, enum arm_mode mode, uint32_t value)
  193. {
  194. int retval;
  195. uint32_t reg_value;
  196. struct arm_reg *armv7m_core_reg;
  197. struct armv7m_common *armv7m = target_to_armv7m(target);
  198. assert(num < (int)armv7m->arm.core_cache->num_regs);
  199. reg_value = buf_get_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32);
  200. armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
  201. retval = armv7m->store_core_reg_u32(target,
  202. armv7m_core_reg->num,
  203. reg_value);
  204. if (retval != ERROR_OK) {
  205. LOG_ERROR("JTAG failure");
  206. armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
  207. return ERROR_JTAG_DEVICE_ERROR;
  208. }
  209. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
  210. armv7m->arm.core_cache->reg_list[num].valid = 1;
  211. armv7m->arm.core_cache->reg_list[num].dirty = 0;
  212. return ERROR_OK;
  213. }
  214. /**
  215. * Returns generic ARM userspace registers to GDB.
  216. * GDB doesn't quite understand that most ARMs don't have floating point
  217. * hardware, so this also fakes a set of long-obsolete FPA registers that
  218. * are not used in EABI based software stacks.
  219. */
  220. int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
  221. {
  222. struct armv7m_common *armv7m = target_to_armv7m(target);
  223. int i;
  224. *reg_list_size = 26;
  225. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  226. /*
  227. * GDB register packet format for ARM:
  228. * - the first 16 registers are r0..r15
  229. * - (obsolete) 8 FPA registers
  230. * - (obsolete) FPA status
  231. * - CPSR
  232. */
  233. for (i = 0; i < 16; i++)
  234. (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
  235. for (i = 16; i < 24; i++)
  236. (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
  237. (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
  238. #ifdef ARMV7_GDB_HACKS
  239. /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
  240. (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
  241. /* ARMV7M is always in thumb mode, try to make GDB understand this
  242. * if it does not support this arch */
  243. *((char *)armv7m->arm.pc->value) |= 1;
  244. #else
  245. (*reg_list)[25] = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
  246. #endif
  247. return ERROR_OK;
  248. }
  249. /** Runs a Thumb algorithm in the target. */
  250. int armv7m_run_algorithm(struct target *target,
  251. int num_mem_params, struct mem_param *mem_params,
  252. int num_reg_params, struct reg_param *reg_params,
  253. uint32_t entry_point, uint32_t exit_point,
  254. int timeout_ms, void *arch_info)
  255. {
  256. int retval;
  257. retval = armv7m_start_algorithm(target,
  258. num_mem_params, mem_params,
  259. num_reg_params, reg_params,
  260. entry_point, exit_point,
  261. arch_info);
  262. if (retval == ERROR_OK)
  263. retval = armv7m_wait_algorithm(target,
  264. num_mem_params, mem_params,
  265. num_reg_params, reg_params,
  266. exit_point, timeout_ms,
  267. arch_info);
  268. return retval;
  269. }
  270. /** Starts a Thumb algorithm in the target. */
  271. int armv7m_start_algorithm(struct target *target,
  272. int num_mem_params, struct mem_param *mem_params,
  273. int num_reg_params, struct reg_param *reg_params,
  274. uint32_t entry_point, uint32_t exit_point,
  275. void *arch_info)
  276. {
  277. struct armv7m_common *armv7m = target_to_armv7m(target);
  278. struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
  279. enum arm_mode core_mode = armv7m->arm.core_mode;
  280. int retval = ERROR_OK;
  281. /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
  282. * at the exit point */
  283. if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
  284. LOG_ERROR("current target isn't an ARMV7M target");
  285. return ERROR_TARGET_INVALID;
  286. }
  287. if (target->state != TARGET_HALTED) {
  288. LOG_WARNING("target not halted");
  289. return ERROR_TARGET_NOT_HALTED;
  290. }
  291. /* refresh core register cache
  292. * Not needed if core register cache is always consistent with target process state */
  293. for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
  294. armv7m_algorithm_info->context[i] = buf_get_u32(
  295. armv7m->arm.core_cache->reg_list[i].value,
  296. 0,
  297. 32);
  298. }
  299. for (int i = 0; i < num_mem_params; i++) {
  300. /* TODO: Write only out params */
  301. retval = target_write_buffer(target, mem_params[i].address,
  302. mem_params[i].size,
  303. mem_params[i].value);
  304. if (retval != ERROR_OK)
  305. return retval;
  306. }
  307. for (int i = 0; i < num_reg_params; i++) {
  308. struct reg *reg =
  309. register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
  310. /* uint32_t regvalue; */
  311. if (!reg) {
  312. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  313. return ERROR_COMMAND_SYNTAX_ERROR;
  314. }
  315. if (reg->size != reg_params[i].size) {
  316. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
  317. reg_params[i].reg_name);
  318. return ERROR_COMMAND_SYNTAX_ERROR;
  319. }
  320. /* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
  321. armv7m_set_core_reg(reg, reg_params[i].value);
  322. }
  323. if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
  324. armv7m_algorithm_info->core_mode != core_mode) {
  325. /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
  326. if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
  327. armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
  328. LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
  329. }
  330. LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
  331. buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
  332. 0, 1, armv7m_algorithm_info->core_mode);
  333. armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
  334. armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
  335. }
  336. /* save previous core mode */
  337. armv7m_algorithm_info->core_mode = core_mode;
  338. retval = target_resume(target, 0, entry_point, 1, 1);
  339. return retval;
  340. }
  341. /** Waits for an algorithm in the target. */
  342. int armv7m_wait_algorithm(struct target *target,
  343. int num_mem_params, struct mem_param *mem_params,
  344. int num_reg_params, struct reg_param *reg_params,
  345. uint32_t exit_point, int timeout_ms,
  346. void *arch_info)
  347. {
  348. struct armv7m_common *armv7m = target_to_armv7m(target);
  349. struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
  350. int retval = ERROR_OK;
  351. uint32_t pc;
  352. /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
  353. * at the exit point */
  354. if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
  355. LOG_ERROR("current target isn't an ARMV7M target");
  356. return ERROR_TARGET_INVALID;
  357. }
  358. retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
  359. /* If the target fails to halt due to the breakpoint, force a halt */
  360. if (retval != ERROR_OK || target->state != TARGET_HALTED) {
  361. retval = target_halt(target);
  362. if (retval != ERROR_OK)
  363. return retval;
  364. retval = target_wait_state(target, TARGET_HALTED, 500);
  365. if (retval != ERROR_OK)
  366. return retval;
  367. return ERROR_TARGET_TIMEOUT;
  368. }
  369. armv7m->load_core_reg_u32(target, 15, &pc);
  370. if (exit_point && (pc != exit_point)) {
  371. LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32,
  372. pc,
  373. exit_point);
  374. return ERROR_TARGET_TIMEOUT;
  375. }
  376. /* Read memory values to mem_params[] */
  377. for (int i = 0; i < num_mem_params; i++) {
  378. if (mem_params[i].direction != PARAM_OUT) {
  379. retval = target_read_buffer(target, mem_params[i].address,
  380. mem_params[i].size,
  381. mem_params[i].value);
  382. if (retval != ERROR_OK)
  383. return retval;
  384. }
  385. }
  386. /* Copy core register values to reg_params[] */
  387. for (int i = 0; i < num_reg_params; i++) {
  388. if (reg_params[i].direction != PARAM_OUT) {
  389. struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
  390. reg_params[i].reg_name,
  391. 0);
  392. if (!reg) {
  393. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  394. return ERROR_COMMAND_SYNTAX_ERROR;
  395. }
  396. if (reg->size != reg_params[i].size) {
  397. LOG_ERROR(
  398. "BUG: register '%s' size doesn't match reg_params[i].size",
  399. reg_params[i].reg_name);
  400. return ERROR_COMMAND_SYNTAX_ERROR;
  401. }
  402. buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
  403. }
  404. }
  405. for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
  406. uint32_t regvalue;
  407. regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
  408. if (regvalue != armv7m_algorithm_info->context[i]) {
  409. LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
  410. armv7m->arm.core_cache->reg_list[i].name,
  411. armv7m_algorithm_info->context[i]);
  412. buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
  413. 0, 32, armv7m_algorithm_info->context[i]);
  414. armv7m->arm.core_cache->reg_list[i].valid = 1;
  415. armv7m->arm.core_cache->reg_list[i].dirty = 1;
  416. }
  417. }
  418. /* restore previous core mode */
  419. if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
  420. LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
  421. buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
  422. 0, 1, armv7m_algorithm_info->core_mode);
  423. armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
  424. armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
  425. }
  426. armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
  427. return retval;
  428. }
  429. /** Logs summary of ARMv7-M state for a halted target. */
  430. int armv7m_arch_state(struct target *target)
  431. {
  432. struct armv7m_common *armv7m = target_to_armv7m(target);
  433. struct arm *arm = &armv7m->arm;
  434. uint32_t ctrl, sp;
  435. ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
  436. sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
  437. LOG_USER("target halted due to %s, current mode: %s %s\n"
  438. "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
  439. debug_reason_name(target),
  440. arm_mode_name(arm->core_mode),
  441. armv7m_exception_string(armv7m->exception_number),
  442. buf_get_u32(arm->cpsr->value, 0, 32),
  443. buf_get_u32(arm->pc->value, 0, 32),
  444. (ctrl & 0x02) ? 'p' : 'm',
  445. sp,
  446. arm->is_semihosting ? ", semihosting" : "");
  447. return ERROR_OK;
  448. }
  449. static const struct reg_arch_type armv7m_reg_type = {
  450. .get = armv7m_get_core_reg,
  451. .set = armv7m_set_core_reg,
  452. };
  453. /** Builds cache of architecturally defined registers. */
  454. struct reg_cache *armv7m_build_reg_cache(struct target *target)
  455. {
  456. struct armv7m_common *armv7m = target_to_armv7m(target);
  457. struct arm *arm = &armv7m->arm;
  458. int num_regs = ARMV7M_NUM_REGS;
  459. struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
  460. struct reg_cache *cache = malloc(sizeof(struct reg_cache));
  461. struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
  462. struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
  463. int i;
  464. #ifdef ARMV7_GDB_HACKS
  465. register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
  466. #endif
  467. /* Build the process context cache */
  468. cache->name = "arm v7m registers";
  469. cache->next = NULL;
  470. cache->reg_list = reg_list;
  471. cache->num_regs = num_regs;
  472. (*cache_p) = cache;
  473. for (i = 0; i < num_regs; i++) {
  474. arch_info[i].num = armv7m_regs[i].id;
  475. arch_info[i].target = target;
  476. arch_info[i].arm = arm;
  477. reg_list[i].name = armv7m_regs[i].name;
  478. reg_list[i].size = armv7m_regs[i].bits;
  479. reg_list[i].value = calloc(1, 4);
  480. reg_list[i].dirty = 0;
  481. reg_list[i].valid = 0;
  482. reg_list[i].type = &armv7m_reg_type;
  483. reg_list[i].arch_info = &arch_info[i];
  484. }
  485. arm->cpsr = reg_list + ARMV7M_xPSR;
  486. arm->pc = reg_list + ARMV7M_PC;
  487. arm->core_cache = cache;
  488. return cache;
  489. }
  490. static int armv7m_setup_semihosting(struct target *target, int enable)
  491. {
  492. /* nothing todo for armv7m */
  493. return ERROR_OK;
  494. }
  495. /** Sets up target as a generic ARMv7-M core */
  496. int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
  497. {
  498. struct arm *arm = &armv7m->arm;
  499. armv7m->common_magic = ARMV7M_COMMON_MAGIC;
  500. armv7m->fp_feature = FP_NONE;
  501. arm->core_type = ARM_MODE_THREAD;
  502. arm->arch_info = armv7m;
  503. arm->setup_semihosting = armv7m_setup_semihosting;
  504. arm->read_core_reg = armv7m_read_core_reg;
  505. arm->write_core_reg = armv7m_write_core_reg;
  506. return arm_init_arch_info(target, arm);
  507. }
  508. /** Generates a CRC32 checksum of a memory region. */
  509. int armv7m_checksum_memory(struct target *target,
  510. uint32_t address, uint32_t count, uint32_t *checksum)
  511. {
  512. struct working_area *crc_algorithm;
  513. struct armv7m_algorithm armv7m_info;
  514. struct reg_param reg_params[2];
  515. int retval;
  516. /* see contrib/loaders/checksum/armv7m_crc.s for src */
  517. static const uint8_t cortex_m3_crc_code[] = {
  518. /* main: */
  519. 0x02, 0x46, /* mov r2, r0 */
  520. 0x00, 0x20, /* movs r0, #0 */
  521. 0xC0, 0x43, /* mvns r0, r0 */
  522. 0x0A, 0x4E, /* ldr r6, CRC32XOR */
  523. 0x0B, 0x46, /* mov r3, r1 */
  524. 0x00, 0x24, /* movs r4, #0 */
  525. 0x0D, 0xE0, /* b ncomp */
  526. /* nbyte: */
  527. 0x11, 0x5D, /* ldrb r1, [r2, r4] */
  528. 0x09, 0x06, /* lsls r1, r1, #24 */
  529. 0x48, 0x40, /* eors r0, r0, r1 */
  530. 0x00, 0x25, /* movs r5, #0 */
  531. /* loop: */
  532. 0x00, 0x28, /* cmp r0, #0 */
  533. 0x02, 0xDA, /* bge notset */
  534. 0x40, 0x00, /* lsls r0, r0, #1 */
  535. 0x70, 0x40, /* eors r0, r0, r6 */
  536. 0x00, 0xE0, /* b cont */
  537. /* notset: */
  538. 0x40, 0x00, /* lsls r0, r0, #1 */
  539. /* cont: */
  540. 0x01, 0x35, /* adds r5, r5, #1 */
  541. 0x08, 0x2D, /* cmp r5, #8 */
  542. 0xF6, 0xD1, /* bne loop */
  543. 0x01, 0x34, /* adds r4, r4, #1 */
  544. /* ncomp: */
  545. 0x9C, 0x42, /* cmp r4, r3 */
  546. 0xEF, 0xD1, /* bne nbyte */
  547. 0x00, 0xBE, /* bkpt #0 */
  548. 0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */
  549. };
  550. retval = target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm);
  551. if (retval != ERROR_OK)
  552. return retval;
  553. retval = target_write_buffer(target, crc_algorithm->address,
  554. sizeof(cortex_m3_crc_code), (uint8_t *)cortex_m3_crc_code);
  555. if (retval != ERROR_OK)
  556. goto cleanup;
  557. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  558. armv7m_info.core_mode = ARM_MODE_THREAD;
  559. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
  560. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  561. buf_set_u32(reg_params[0].value, 0, 32, address);
  562. buf_set_u32(reg_params[1].value, 0, 32, count);
  563. int timeout = 20000 * (1 + (count / (1024 * 1024)));
  564. retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
  565. crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6),
  566. timeout, &armv7m_info);
  567. if (retval == ERROR_OK)
  568. *checksum = buf_get_u32(reg_params[0].value, 0, 32);
  569. else
  570. LOG_ERROR("error executing cortex_m3 crc algorithm");
  571. destroy_reg_param(&reg_params[0]);
  572. destroy_reg_param(&reg_params[1]);
  573. cleanup:
  574. target_free_working_area(target, crc_algorithm);
  575. return retval;
  576. }
  577. /** Checks whether a memory region is zeroed. */
  578. int armv7m_blank_check_memory(struct target *target,
  579. uint32_t address, uint32_t count, uint32_t *blank)
  580. {
  581. struct working_area *erase_check_algorithm;
  582. struct reg_param reg_params[3];
  583. struct armv7m_algorithm armv7m_info;
  584. int retval;
  585. /* see contrib/loaders/erase_check/armv7m_erase_check.s for src */
  586. static const uint8_t erase_check_code[] = {
  587. /* loop: */
  588. 0x03, 0x78, /* ldrb r3, [r0] */
  589. 0x01, 0x30, /* adds r0, #1 */
  590. 0x1A, 0x40, /* ands r2, r2, r3 */
  591. 0x01, 0x39, /* subs r1, r1, #1 */
  592. 0xFA, 0xD1, /* bne loop */
  593. 0x00, 0xBE /* bkpt #0 */
  594. };
  595. /* make sure we have a working area */
  596. if (target_alloc_working_area(target, sizeof(erase_check_code),
  597. &erase_check_algorithm) != ERROR_OK)
  598. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  599. retval = target_write_buffer(target, erase_check_algorithm->address,
  600. sizeof(erase_check_code), (uint8_t *)erase_check_code);
  601. if (retval != ERROR_OK)
  602. return retval;
  603. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  604. armv7m_info.core_mode = ARM_MODE_THREAD;
  605. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  606. buf_set_u32(reg_params[0].value, 0, 32, address);
  607. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  608. buf_set_u32(reg_params[1].value, 0, 32, count);
  609. init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
  610. buf_set_u32(reg_params[2].value, 0, 32, 0xff);
  611. retval = target_run_algorithm(target,
  612. 0,
  613. NULL,
  614. 3,
  615. reg_params,
  616. erase_check_algorithm->address,
  617. erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
  618. 10000,
  619. &armv7m_info);
  620. if (retval == ERROR_OK)
  621. *blank = buf_get_u32(reg_params[2].value, 0, 32);
  622. destroy_reg_param(&reg_params[0]);
  623. destroy_reg_param(&reg_params[1]);
  624. destroy_reg_param(&reg_params[2]);
  625. target_free_working_area(target, erase_check_algorithm);
  626. return retval;
  627. }
  628. int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
  629. {
  630. struct armv7m_common *armv7m = target_to_armv7m(target);
  631. struct reg *r = armv7m->arm.pc;
  632. bool result = false;
  633. /* if we halted last time due to a bkpt instruction
  634. * then we have to manually step over it, otherwise
  635. * the core will break again */
  636. if (target->debug_reason == DBG_REASON_BREAKPOINT) {
  637. uint16_t op;
  638. uint32_t pc = buf_get_u32(r->value, 0, 32);
  639. pc &= ~1;
  640. if (target_read_u16(target, pc, &op) == ERROR_OK) {
  641. if ((op & 0xFF00) == 0xBE00) {
  642. pc = buf_get_u32(r->value, 0, 32) + 2;
  643. buf_set_u32(r->value, 0, 32, pc);
  644. r->dirty = true;
  645. r->valid = true;
  646. result = true;
  647. LOG_DEBUG("Skipping over BKPT instruction");
  648. }
  649. }
  650. }
  651. if (inst_found)
  652. *inst_found = result;
  653. return ERROR_OK;
  654. }
  655. const struct command_registration armv7m_command_handlers[] = {
  656. {
  657. .chain = arm_command_handlers,
  658. },
  659. {
  660. .chain = dap_command_handlers,
  661. },
  662. COMMAND_REGISTRATION_DONE
  663. };