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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Duane Ellis *
  3. * openocd@duaneellis.com *
  4. * *
  5. * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
  6. * olaf@uni-paderborn.de *
  7. * *
  8. * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
  9. * (at91sam3x* & at91sam4 support)* *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
  19. * GNU General public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ****************************************************************************/
  26. /* Some of the the lower level code was based on code supplied by
  27. * ATMEL under this copyright. */
  28. /* BEGIN ATMEL COPYRIGHT */
  29. /* ----------------------------------------------------------------------------
  30. * ATMEL Microcontroller Software Support
  31. * ----------------------------------------------------------------------------
  32. * Copyright (c) 2009, Atmel Corporation
  33. *
  34. * All rights reserved.
  35. *
  36. * Redistribution and use in source and binary forms, with or without
  37. * modification, are permitted provided that the following conditions are met:
  38. *
  39. * - Redistributions of source code must retain the above copyright notice,
  40. * this list of conditions and the disclaimer below.
  41. *
  42. * Atmel's name may not be used to endorse or promote products derived from
  43. * this software without specific prior written permission.
  44. *
  45. * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  46. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  47. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  48. * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  49. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  50. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  51. * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  52. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  53. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  54. * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  55. * ----------------------------------------------------------------------------
  56. */
  57. /* END ATMEL COPYRIGHT */
  58. #ifdef HAVE_CONFIG_H
  59. #include "config.h"
  60. #endif
  61. #include "imp.h"
  62. #include <helper/time_support.h>
  63. #define REG_NAME_WIDTH (12)
  64. /* at91sam4s/at91sam4e series (has always one flash bank)*/
  65. #define FLASH_BANK_BASE_S 0x00400000
  66. /* at91sam4sd series (two one flash banks), first bank address */
  67. #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
  68. /* at91sam4sd16x, second bank address */
  69. #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
  70. /* at91sam4sd32x, second bank address */
  71. #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
  72. #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
  73. #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
  74. #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
  75. #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
  76. #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
  77. #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
  78. /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
  79. /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
  80. #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
  81. #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
  82. #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
  83. #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
  84. #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
  85. #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
  86. #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
  87. #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
  88. #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
  89. #define offset_EFC_FMR 0
  90. #define offset_EFC_FCR 4
  91. #define offset_EFC_FSR 8
  92. #define offset_EFC_FRR 12
  93. extern struct flash_driver at91sam4_flash;
  94. static float _tomhz(uint32_t freq_hz)
  95. {
  96. float f;
  97. f = ((float)(freq_hz)) / 1000000.0;
  98. return f;
  99. }
  100. /* How the chip is configured. */
  101. struct sam4_cfg {
  102. uint32_t unique_id[4];
  103. uint32_t slow_freq;
  104. uint32_t rc_freq;
  105. uint32_t mainosc_freq;
  106. uint32_t plla_freq;
  107. uint32_t mclk_freq;
  108. uint32_t cpu_freq;
  109. uint32_t fclk_freq;
  110. uint32_t pclk0_freq;
  111. uint32_t pclk1_freq;
  112. uint32_t pclk2_freq;
  113. #define SAM4_CHIPID_CIDR (0x400E0740)
  114. uint32_t CHIPID_CIDR;
  115. #define SAM4_CHIPID_EXID (0x400E0744)
  116. uint32_t CHIPID_EXID;
  117. #define SAM4_PMC_BASE (0x400E0400)
  118. #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
  119. uint32_t PMC_SCSR;
  120. #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
  121. uint32_t PMC_PCSR;
  122. #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
  123. uint32_t CKGR_UCKR;
  124. #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
  125. uint32_t CKGR_MOR;
  126. #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
  127. uint32_t CKGR_MCFR;
  128. #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
  129. uint32_t CKGR_PLLAR;
  130. #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
  131. uint32_t PMC_MCKR;
  132. #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
  133. uint32_t PMC_PCK0;
  134. #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
  135. uint32_t PMC_PCK1;
  136. #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
  137. uint32_t PMC_PCK2;
  138. #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
  139. uint32_t PMC_SR;
  140. #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
  141. uint32_t PMC_IMR;
  142. #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
  143. uint32_t PMC_FSMR;
  144. #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
  145. uint32_t PMC_FSPR;
  146. };
  147. struct sam4_bank_private {
  148. int probed;
  149. /* DANGER: THERE ARE DRAGONS HERE.. */
  150. /* NOTE: If you add more 'ghost' pointers */
  151. /* be aware that you must *manually* update */
  152. /* these pointers in the function sam4_GetDetails() */
  153. /* See the comment "Here there be dragons" */
  154. /* so we can find the chip we belong to */
  155. struct sam4_chip *pChip;
  156. /* so we can find the original bank pointer */
  157. struct flash_bank *pBank;
  158. unsigned bank_number;
  159. uint32_t controller_address;
  160. uint32_t base_address;
  161. uint32_t flash_wait_states;
  162. bool present;
  163. unsigned size_bytes;
  164. unsigned nsectors;
  165. unsigned sector_size;
  166. unsigned page_size;
  167. };
  168. struct sam4_chip_details {
  169. /* THERE ARE DRAGONS HERE.. */
  170. /* note: If you add pointers here */
  171. /* be careful about them as they */
  172. /* may need to be updated inside */
  173. /* the function: "sam4_GetDetails() */
  174. /* which copy/overwrites the */
  175. /* 'runtime' copy of this structure */
  176. uint32_t chipid_cidr;
  177. const char *name;
  178. unsigned n_gpnvms;
  179. #define SAM4_N_NVM_BITS 3
  180. unsigned gpnvm[SAM4_N_NVM_BITS];
  181. unsigned total_flash_size;
  182. unsigned total_sram_size;
  183. unsigned n_banks;
  184. #define SAM4_MAX_FLASH_BANKS 2
  185. /* these are "initialized" from the global const data */
  186. struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
  187. };
  188. struct sam4_chip {
  189. struct sam4_chip *next;
  190. int probed;
  191. /* this is "initialized" from the global const structure */
  192. struct sam4_chip_details details;
  193. struct target *target;
  194. struct sam4_cfg cfg;
  195. };
  196. struct sam4_reg_list {
  197. uint32_t address; size_t struct_offset; const char *name;
  198. void (*explain_func)(struct sam4_chip *pInfo);
  199. };
  200. static struct sam4_chip *all_sam4_chips;
  201. static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
  202. {
  203. struct target *t;
  204. static struct sam4_chip *p;
  205. t = get_current_target(cmd_ctx);
  206. if (!t) {
  207. command_print(cmd_ctx, "No current target?");
  208. return NULL;
  209. }
  210. p = all_sam4_chips;
  211. if (!p) {
  212. /* this should not happen */
  213. /* the command is not registered until the chip is created? */
  214. command_print(cmd_ctx, "No SAM4 chips exist?");
  215. return NULL;
  216. }
  217. while (p) {
  218. if (p->target == t)
  219. return p;
  220. p = p->next;
  221. }
  222. command_print(cmd_ctx, "Cannot find SAM4 chip?");
  223. return NULL;
  224. }
  225. /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
  226. /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
  227. /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
  228. /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
  229. /* these are used to *initialize* the "pChip->details" structure. */
  230. static const struct sam4_chip_details all_sam4_details[] = {
  231. /* Start at91sam4e* series */
  232. /*atsam4e16e - LQFP144/LFBGA144*/
  233. {
  234. .chipid_cidr = 0xA3CC0CE0,
  235. .name = "at91sam4e16e",
  236. .total_flash_size = 1024 * 1024,
  237. .total_sram_size = 128 * 1024,
  238. .n_gpnvms = 2,
  239. .n_banks = 1,
  240. {
  241. /* .bank[0] = {*/
  242. {
  243. .probed = 0,
  244. .pChip = NULL,
  245. .pBank = NULL,
  246. .bank_number = 0,
  247. .base_address = FLASH_BANK_BASE_S,
  248. .controller_address = 0x400e0a00,
  249. .flash_wait_states = 6, /* workaround silicon bug */
  250. .present = 1,
  251. .size_bytes = 1024 * 1024,
  252. .nsectors = 128,
  253. .sector_size = 8192,
  254. .page_size = 512,
  255. },
  256. /* .bank[1] = {*/
  257. {
  258. .present = 0,
  259. .probed = 0,
  260. .bank_number = 1,
  261. },
  262. },
  263. },
  264. /* Start at91sam4n* series */
  265. /*atsam4n8a - LQFP48/QFN48*/
  266. {
  267. .chipid_cidr = 0x293B0AE0,
  268. .name = "at91sam4n8a",
  269. .total_flash_size = 512 * 1024,
  270. .total_sram_size = 64 * 1024,
  271. .n_gpnvms = 2,
  272. .n_banks = 1,
  273. {
  274. /* .bank[0] = {*/
  275. {
  276. .probed = 0,
  277. .pChip = NULL,
  278. .pBank = NULL,
  279. .bank_number = 0,
  280. .base_address = FLASH_BANK_BASE_S,
  281. .controller_address = 0x400e0a00,
  282. .flash_wait_states = 6, /* workaround silicon bug */
  283. .present = 1,
  284. .size_bytes = 512 * 1024,
  285. .nsectors = 64,
  286. .sector_size = 8192,
  287. .page_size = 512,
  288. },
  289. /* .bank[1] = {*/
  290. {
  291. .present = 0,
  292. .probed = 0,
  293. .bank_number = 1,
  294. },
  295. },
  296. },
  297. /*atsam4n8b - LQFP64/QFN64*/
  298. {
  299. .chipid_cidr = 0x294B0AE0,
  300. .name = "at91sam4n8b",
  301. .total_flash_size = 512 * 1024,
  302. .total_sram_size = 64 * 1024,
  303. .n_gpnvms = 2,
  304. .n_banks = 1,
  305. {
  306. /* .bank[0] = {*/
  307. {
  308. .probed = 0,
  309. .pChip = NULL,
  310. .pBank = NULL,
  311. .bank_number = 0,
  312. .base_address = FLASH_BANK_BASE_S,
  313. .controller_address = 0x400e0a00,
  314. .flash_wait_states = 6, /* workaround silicon bug */
  315. .present = 1,
  316. .size_bytes = 512 * 1024,
  317. .nsectors = 64,
  318. .sector_size = 8192,
  319. .page_size = 512,
  320. },
  321. /* .bank[1] = {*/
  322. {
  323. .present = 0,
  324. .probed = 0,
  325. .bank_number = 1,
  326. },
  327. },
  328. },
  329. /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
  330. {
  331. .chipid_cidr = 0x295B0AE0,
  332. .name = "at91sam4n8c",
  333. .total_flash_size = 512 * 1024,
  334. .total_sram_size = 64 * 1024,
  335. .n_gpnvms = 2,
  336. .n_banks = 1,
  337. {
  338. /* .bank[0] = {*/
  339. {
  340. .probed = 0,
  341. .pChip = NULL,
  342. .pBank = NULL,
  343. .bank_number = 0,
  344. .base_address = FLASH_BANK_BASE_S,
  345. .controller_address = 0x400e0a00,
  346. .flash_wait_states = 6, /* workaround silicon bug */
  347. .present = 1,
  348. .size_bytes = 512 * 1024,
  349. .nsectors = 64,
  350. .sector_size = 8192,
  351. .page_size = 512,
  352. },
  353. /* .bank[1] = {*/
  354. {
  355. .present = 0,
  356. .probed = 0,
  357. .bank_number = 1,
  358. },
  359. },
  360. },
  361. /*atsam4n16b - LQFP64/QFN64*/
  362. {
  363. .chipid_cidr = 0x29460CE0,
  364. .name = "at91sam4n16b",
  365. .total_flash_size = 1024 * 1024,
  366. .total_sram_size = 80 * 1024,
  367. .n_gpnvms = 2,
  368. .n_banks = 1,
  369. {
  370. /* .bank[0] = {*/
  371. {
  372. .probed = 0,
  373. .pChip = NULL,
  374. .pBank = NULL,
  375. .bank_number = 0,
  376. .base_address = FLASH_BANK_BASE_S,
  377. .controller_address = 0x400e0a00,
  378. .flash_wait_states = 6, /* workaround silicon bug */
  379. .present = 1,
  380. .size_bytes = 1024 * 1024,
  381. .nsectors = 128,
  382. .sector_size = 8192,
  383. .page_size = 512,
  384. },
  385. /* .bank[1] = {*/
  386. {
  387. .present = 0,
  388. .probed = 0,
  389. .bank_number = 1,
  390. },
  391. },
  392. },
  393. /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
  394. {
  395. .chipid_cidr = 0x29560CE0,
  396. .name = "at91sam4n16c",
  397. .total_flash_size = 1024 * 1024,
  398. .total_sram_size = 80 * 1024,
  399. .n_gpnvms = 2,
  400. .n_banks = 1,
  401. {
  402. /* .bank[0] = {*/
  403. {
  404. .probed = 0,
  405. .pChip = NULL,
  406. .pBank = NULL,
  407. .bank_number = 0,
  408. .base_address = FLASH_BANK_BASE_S,
  409. .controller_address = 0x400e0a00,
  410. .flash_wait_states = 6, /* workaround silicon bug */
  411. .present = 1,
  412. .size_bytes = 1024 * 1024,
  413. .nsectors = 128,
  414. .sector_size = 8192,
  415. .page_size = 512,
  416. },
  417. /* .bank[1] = {*/
  418. {
  419. .present = 0,
  420. .probed = 0,
  421. .bank_number = 1,
  422. },
  423. },
  424. },
  425. /* Start at91sam4s* series */
  426. /*atsam4s16c - LQFP100/BGA100*/
  427. {
  428. .chipid_cidr = 0x28AC0CE0,
  429. .name = "at91sam4s16c",
  430. .total_flash_size = 1024 * 1024,
  431. .total_sram_size = 128 * 1024,
  432. .n_gpnvms = 2,
  433. .n_banks = 1,
  434. {
  435. /* .bank[0] = {*/
  436. {
  437. .probed = 0,
  438. .pChip = NULL,
  439. .pBank = NULL,
  440. .bank_number = 0,
  441. .base_address = FLASH_BANK_BASE_S,
  442. .controller_address = 0x400e0a00,
  443. .flash_wait_states = 6, /* workaround silicon bug */
  444. .present = 1,
  445. .size_bytes = 1024 * 1024,
  446. .nsectors = 128,
  447. .sector_size = 8192,
  448. .page_size = 512,
  449. },
  450. /* .bank[1] = {*/
  451. {
  452. .present = 0,
  453. .probed = 0,
  454. .bank_number = 1,
  455. },
  456. },
  457. },
  458. /*atsam4s16b - LQFP64/QFN64*/
  459. {
  460. .chipid_cidr = 0x289C0CE0,
  461. .name = "at91sam4s16b",
  462. .total_flash_size = 1024 * 1024,
  463. .total_sram_size = 128 * 1024,
  464. .n_gpnvms = 2,
  465. .n_banks = 1,
  466. {
  467. /* .bank[0] = {*/
  468. {
  469. .probed = 0,
  470. .pChip = NULL,
  471. .pBank = NULL,
  472. .bank_number = 0,
  473. .base_address = FLASH_BANK_BASE_S,
  474. .controller_address = 0x400e0a00,
  475. .flash_wait_states = 6, /* workaround silicon bug */
  476. .present = 1,
  477. .size_bytes = 1024 * 1024,
  478. .nsectors = 128,
  479. .sector_size = 8192,
  480. .page_size = 512,
  481. },
  482. /* .bank[1] = {*/
  483. {
  484. .present = 0,
  485. .probed = 0,
  486. .bank_number = 1,
  487. },
  488. },
  489. },
  490. /*atsam4sa16b - LQFP64/QFN64*/
  491. {
  492. .chipid_cidr = 0x28970CE0,
  493. .name = "at91sam4sa16b",
  494. .total_flash_size = 1024 * 1024,
  495. .total_sram_size = 160 * 1024,
  496. .n_gpnvms = 2,
  497. .n_banks = 1,
  498. {
  499. /* .bank[0] = {*/
  500. {
  501. .probed = 0,
  502. .pChip = NULL,
  503. .pBank = NULL,
  504. .bank_number = 0,
  505. .base_address = FLASH_BANK_BASE_S,
  506. .controller_address = 0x400e0a00,
  507. .flash_wait_states = 6, /* workaround silicon bug */
  508. .present = 1,
  509. .size_bytes = 1024 * 1024,
  510. .nsectors = 128,
  511. .sector_size = 8192,
  512. .page_size = 512,
  513. },
  514. /* .bank[1] = {*/
  515. {
  516. .present = 0,
  517. .probed = 0,
  518. .bank_number = 1,
  519. },
  520. },
  521. },
  522. /*atsam4s16a - LQFP48/QFN48*/
  523. {
  524. .chipid_cidr = 0x288C0CE0,
  525. .name = "at91sam4s16a",
  526. .total_flash_size = 1024 * 1024,
  527. .total_sram_size = 128 * 1024,
  528. .n_gpnvms = 2,
  529. .n_banks = 1,
  530. {
  531. /* .bank[0] = {*/
  532. {
  533. .probed = 0,
  534. .pChip = NULL,
  535. .pBank = NULL,
  536. .bank_number = 0,
  537. .base_address = FLASH_BANK_BASE_S,
  538. .controller_address = 0x400e0a00,
  539. .flash_wait_states = 6, /* workaround silicon bug */
  540. .present = 1,
  541. .size_bytes = 1024 * 1024,
  542. .nsectors = 128,
  543. .sector_size = 8192,
  544. .page_size = 512,
  545. },
  546. /* .bank[1] = {*/
  547. {
  548. .present = 0,
  549. .probed = 0,
  550. .bank_number = 1,
  551. },
  552. },
  553. },
  554. /*atsam4s8c - LQFP100/BGA100*/
  555. {
  556. .chipid_cidr = 0x28AC0AE0,
  557. .name = "at91sam4s8c",
  558. .total_flash_size = 512 * 1024,
  559. .total_sram_size = 128 * 1024,
  560. .n_gpnvms = 2,
  561. .n_banks = 1,
  562. {
  563. /* .bank[0] = {*/
  564. {
  565. .probed = 0,
  566. .pChip = NULL,
  567. .pBank = NULL,
  568. .bank_number = 0,
  569. .base_address = FLASH_BANK_BASE_S,
  570. .controller_address = 0x400e0a00,
  571. .flash_wait_states = 6, /* workaround silicon bug */
  572. .present = 1,
  573. .size_bytes = 512 * 1024,
  574. .nsectors = 64,
  575. .sector_size = 8192,
  576. .page_size = 512,
  577. },
  578. /* .bank[1] = {*/
  579. {
  580. .present = 0,
  581. .probed = 0,
  582. .bank_number = 1,
  583. },
  584. },
  585. },
  586. /*atsam4s8b - LQFP64/BGA64*/
  587. {
  588. .chipid_cidr = 0x289C0AE0,
  589. .name = "at91sam4s8b",
  590. .total_flash_size = 512 * 1024,
  591. .total_sram_size = 128 * 1024,
  592. .n_gpnvms = 2,
  593. .n_banks = 1,
  594. {
  595. /* .bank[0] = {*/
  596. {
  597. .probed = 0,
  598. .pChip = NULL,
  599. .pBank = NULL,
  600. .bank_number = 0,
  601. .base_address = FLASH_BANK_BASE_S,
  602. .controller_address = 0x400e0a00,
  603. .flash_wait_states = 6, /* workaround silicon bug */
  604. .present = 1,
  605. .size_bytes = 512 * 1024,
  606. .nsectors = 64,
  607. .sector_size = 8192,
  608. .page_size = 512,
  609. },
  610. /* .bank[1] = {*/
  611. {
  612. .present = 0,
  613. .probed = 0,
  614. .bank_number = 1,
  615. },
  616. },
  617. },
  618. /*atsam4s8a - LQFP48/BGA48*/
  619. {
  620. .chipid_cidr = 0x288C0AE0,
  621. .name = "at91sam4s8a",
  622. .total_flash_size = 512 * 1024,
  623. .total_sram_size = 128 * 1024,
  624. .n_gpnvms = 2,
  625. .n_banks = 1,
  626. {
  627. /* .bank[0] = {*/
  628. {
  629. .probed = 0,
  630. .pChip = NULL,
  631. .pBank = NULL,
  632. .bank_number = 0,
  633. .base_address = FLASH_BANK_BASE_S,
  634. .controller_address = 0x400e0a00,
  635. .flash_wait_states = 6, /* workaround silicon bug */
  636. .present = 1,
  637. .size_bytes = 512 * 1024,
  638. .nsectors = 64,
  639. .sector_size = 8192,
  640. .page_size = 512,
  641. },
  642. /* .bank[1] = {*/
  643. {
  644. .present = 0,
  645. .probed = 0,
  646. .bank_number = 1,
  647. },
  648. },
  649. },
  650. /*atsam4s4a - LQFP48/BGA48*/
  651. {
  652. .chipid_cidr = 0x288b09e0,
  653. .name = "at91sam4s4a",
  654. .total_flash_size = 256 * 1024,
  655. .total_sram_size = 64 * 1024,
  656. .n_gpnvms = 2,
  657. .n_banks = 1,
  658. {
  659. /* .bank[0] = {*/
  660. {
  661. .probed = 0,
  662. .pChip = NULL,
  663. .pBank = NULL,
  664. .bank_number = 0,
  665. .base_address = FLASH_BANK_BASE_S,
  666. .controller_address = 0x400e0a00,
  667. .flash_wait_states = 6, /* workaround silicon bug */
  668. .present = 1,
  669. .size_bytes = 256 * 1024,
  670. .nsectors = 32,
  671. .sector_size = 8192,
  672. .page_size = 512,
  673. },
  674. /* .bank[1] = {*/
  675. {
  676. .present = 0,
  677. .probed = 0,
  678. .bank_number = 1,
  679. },
  680. },
  681. },
  682. /*at91sam4sd32c*/
  683. {
  684. .chipid_cidr = 0x29a70ee0,
  685. .name = "at91sam4sd32c",
  686. .total_flash_size = 2048 * 1024,
  687. .total_sram_size = 160 * 1024,
  688. .n_gpnvms = 3,
  689. .n_banks = 2,
  690. /* .bank[0] = { */
  691. {
  692. {
  693. .probed = 0,
  694. .pChip = NULL,
  695. .pBank = NULL,
  696. .bank_number = 0,
  697. .base_address = FLASH_BANK0_BASE_SD,
  698. .controller_address = 0x400e0a00,
  699. .flash_wait_states = 6, /* workaround silicon bug */
  700. .present = 1,
  701. .size_bytes = 1024 * 1024,
  702. .nsectors = 128,
  703. .sector_size = 8192,
  704. .page_size = 512,
  705. },
  706. /* .bank[1] = { */
  707. {
  708. .probed = 0,
  709. .pChip = NULL,
  710. .pBank = NULL,
  711. .bank_number = 1,
  712. .base_address = FLASH_BANK1_BASE_2048K_SD,
  713. .controller_address = 0x400e0c00,
  714. .flash_wait_states = 6, /* workaround silicon bug */
  715. .present = 1,
  716. .size_bytes = 1024 * 1024,
  717. .nsectors = 128,
  718. .sector_size = 8192,
  719. .page_size = 512,
  720. },
  721. },
  722. },
  723. /*at91sam4sd16c*/
  724. {
  725. .chipid_cidr = 0x29a70ce0,
  726. .name = "at91sam4sd16c",
  727. .total_flash_size = 1024 * 1024,
  728. .total_sram_size = 160 * 1024,
  729. .n_gpnvms = 3,
  730. .n_banks = 2,
  731. /* .bank[0] = { */
  732. {
  733. {
  734. .probed = 0,
  735. .pChip = NULL,
  736. .pBank = NULL,
  737. .bank_number = 0,
  738. .base_address = FLASH_BANK0_BASE_SD,
  739. .controller_address = 0x400e0a00,
  740. .flash_wait_states = 6, /* workaround silicon bug */
  741. .present = 1,
  742. .size_bytes = 512 * 1024,
  743. .nsectors = 64,
  744. .sector_size = 8192,
  745. .page_size = 512,
  746. },
  747. /* .bank[1] = { */
  748. {
  749. .probed = 0,
  750. .pChip = NULL,
  751. .pBank = NULL,
  752. .bank_number = 1,
  753. .base_address = FLASH_BANK1_BASE_1024K_SD,
  754. .controller_address = 0x400e0c00,
  755. .flash_wait_states = 6, /* workaround silicon bug */
  756. .present = 1,
  757. .size_bytes = 512 * 1024,
  758. .nsectors = 64,
  759. .sector_size = 8192,
  760. .page_size = 512,
  761. },
  762. },
  763. },
  764. /*at91sam4sa16c*/
  765. {
  766. .chipid_cidr = 0x28a70ce0,
  767. .name = "at91sam4sa16c",
  768. .total_flash_size = 1024 * 1024,
  769. .total_sram_size = 160 * 1024,
  770. .n_gpnvms = 3,
  771. .n_banks = 2,
  772. /* .bank[0] = { */
  773. {
  774. {
  775. .probed = 0,
  776. .pChip = NULL,
  777. .pBank = NULL,
  778. .bank_number = 0,
  779. .base_address = FLASH_BANK0_BASE_SD,
  780. .controller_address = 0x400e0a00,
  781. .flash_wait_states = 6, /* workaround silicon bug */
  782. .present = 1,
  783. .size_bytes = 512 * 1024,
  784. .nsectors = 64,
  785. .sector_size = 8192,
  786. .page_size = 512,
  787. },
  788. /* .bank[1] = { */
  789. {
  790. .probed = 0,
  791. .pChip = NULL,
  792. .pBank = NULL,
  793. .bank_number = 1,
  794. .base_address = FLASH_BANK1_BASE_1024K_SD,
  795. .controller_address = 0x400e0c00,
  796. .flash_wait_states = 6, /* workaround silicon bug */
  797. .present = 1,
  798. .size_bytes = 512 * 1024,
  799. .nsectors = 64,
  800. .sector_size = 8192,
  801. .page_size = 512,
  802. },
  803. },
  804. },
  805. /* at91samg53n19 */
  806. {
  807. .chipid_cidr = 0x247e0ae0,
  808. .name = "at91samg53n19",
  809. .total_flash_size = 512 * 1024,
  810. .total_sram_size = 96 * 1024,
  811. .n_gpnvms = 2,
  812. .n_banks = 1,
  813. /* .bank[0] = {*/
  814. {
  815. {
  816. .probed = 0,
  817. .pChip = NULL,
  818. .pBank = NULL,
  819. .bank_number = 0,
  820. .base_address = FLASH_BANK_BASE_S,
  821. .controller_address = 0x400e0a00,
  822. .flash_wait_states = 6, /* workaround silicon bug */
  823. .present = 1,
  824. .size_bytes = 512 * 1024,
  825. .nsectors = 64,
  826. .sector_size = 8192,
  827. .page_size = 512,
  828. },
  829. /* .bank[1] = {*/
  830. {
  831. .present = 0,
  832. .probed = 0,
  833. .bank_number = 1,
  834. },
  835. }
  836. },
  837. /* terminate */
  838. {
  839. .chipid_cidr = 0,
  840. .name = NULL,
  841. }
  842. };
  843. /* Globals above */
  844. /***********************************************************************
  845. **********************************************************************
  846. **********************************************************************
  847. **********************************************************************
  848. **********************************************************************
  849. **********************************************************************/
  850. /* *ATMEL* style code - from the SAM4 driver code */
  851. /**
  852. * Get the current status of the EEFC and
  853. * the value of some status bits (LOCKE, PROGE).
  854. * @param pPrivate - info about the bank
  855. * @param v - result goes here
  856. */
  857. static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
  858. {
  859. int r;
  860. r = target_read_u32(pPrivate->pChip->target,
  861. pPrivate->controller_address + offset_EFC_FSR,
  862. v);
  863. LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
  864. (unsigned int)(*v),
  865. ((unsigned int)((*v >> 2) & 1)),
  866. ((unsigned int)((*v >> 1) & 1)),
  867. ((unsigned int)((*v >> 0) & 1)));
  868. return r;
  869. }
  870. /**
  871. * Get the result of the last executed command.
  872. * @param pPrivate - info about the bank
  873. * @param v - result goes here
  874. */
  875. static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
  876. {
  877. int r;
  878. uint32_t rv;
  879. r = target_read_u32(pPrivate->pChip->target,
  880. pPrivate->controller_address + offset_EFC_FRR,
  881. &rv);
  882. if (v)
  883. *v = rv;
  884. LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
  885. return r;
  886. }
  887. static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
  888. unsigned command, unsigned argument)
  889. {
  890. uint32_t n, v;
  891. int r;
  892. int retry;
  893. retry = 0;
  894. do_retry:
  895. /* Check command & argument */
  896. switch (command) {
  897. case AT91C_EFC_FCMD_WP:
  898. case AT91C_EFC_FCMD_WPL:
  899. case AT91C_EFC_FCMD_EWP:
  900. case AT91C_EFC_FCMD_EWPL:
  901. /* case AT91C_EFC_FCMD_EPL: */
  902. case AT91C_EFC_FCMD_EPA:
  903. case AT91C_EFC_FCMD_SLB:
  904. case AT91C_EFC_FCMD_CLB:
  905. n = (pPrivate->size_bytes / pPrivate->page_size);
  906. if (argument >= n)
  907. LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
  908. break;
  909. case AT91C_EFC_FCMD_SFB:
  910. case AT91C_EFC_FCMD_CFB:
  911. if (argument >= pPrivate->pChip->details.n_gpnvms) {
  912. LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
  913. pPrivate->pChip->details.n_gpnvms);
  914. }
  915. break;
  916. case AT91C_EFC_FCMD_GETD:
  917. case AT91C_EFC_FCMD_EA:
  918. case AT91C_EFC_FCMD_GLB:
  919. case AT91C_EFC_FCMD_GFB:
  920. case AT91C_EFC_FCMD_STUI:
  921. case AT91C_EFC_FCMD_SPUI:
  922. if (argument != 0)
  923. LOG_ERROR("Argument is meaningless for cmd: %d", command);
  924. break;
  925. default:
  926. LOG_ERROR("Unknown command %d", command);
  927. break;
  928. }
  929. if (command == AT91C_EFC_FCMD_SPUI) {
  930. /* this is a very special situation. */
  931. /* Situation (1) - error/retry - see below */
  932. /* And we are being called recursively */
  933. /* Situation (2) - normal, finished reading unique id */
  934. } else {
  935. /* it should be "ready" */
  936. EFC_GetStatus(pPrivate, &v);
  937. if (v & 1) {
  938. /* then it is ready */
  939. /* we go on */
  940. } else {
  941. if (retry) {
  942. /* we have done this before */
  943. /* the controller is not responding. */
  944. LOG_ERROR("flash controller(%d) is not ready! Error",
  945. pPrivate->bank_number);
  946. return ERROR_FAIL;
  947. } else {
  948. retry++;
  949. LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
  950. pPrivate->bank_number);
  951. /* we do that by issuing the *STOP* command */
  952. EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
  953. /* above is recursive, and further recursion is blocked by */
  954. /* if (command == AT91C_EFC_FCMD_SPUI) above */
  955. goto do_retry;
  956. }
  957. }
  958. }
  959. v = (0x5A << 24) | (argument << 8) | command;
  960. LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
  961. r = target_write_u32(pPrivate->pBank->target,
  962. pPrivate->controller_address + offset_EFC_FCR, v);
  963. if (r != ERROR_OK)
  964. LOG_DEBUG("Error Write failed");
  965. return r;
  966. }
  967. /**
  968. * Performs the given command and wait until its completion (or an error).
  969. * @param pPrivate - info about the bank
  970. * @param command - Command to perform.
  971. * @param argument - Optional command argument.
  972. * @param status - put command status bits here
  973. */
  974. static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
  975. unsigned command,
  976. unsigned argument,
  977. uint32_t *status)
  978. {
  979. int r;
  980. uint32_t v;
  981. long long ms_now, ms_end;
  982. /* default */
  983. if (status)
  984. *status = 0;
  985. r = EFC_StartCommand(pPrivate, command, argument);
  986. if (r != ERROR_OK)
  987. return r;
  988. ms_end = 10000 + timeval_ms();
  989. do {
  990. r = EFC_GetStatus(pPrivate, &v);
  991. if (r != ERROR_OK)
  992. return r;
  993. ms_now = timeval_ms();
  994. if (ms_now > ms_end) {
  995. /* error */
  996. LOG_ERROR("Command timeout");
  997. return ERROR_FAIL;
  998. }
  999. } while ((v & 1) == 0);
  1000. /* error bits.. */
  1001. if (status)
  1002. *status = (v & 0x6);
  1003. return ERROR_OK;
  1004. }
  1005. /**
  1006. * Read the unique ID.
  1007. * @param pPrivate - info about the bank
  1008. * The unique ID is stored in the 'pPrivate' structure.
  1009. */
  1010. static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
  1011. {
  1012. int r;
  1013. uint32_t v;
  1014. int x;
  1015. /* assume 0 */
  1016. pPrivate->pChip->cfg.unique_id[0] = 0;
  1017. pPrivate->pChip->cfg.unique_id[1] = 0;
  1018. pPrivate->pChip->cfg.unique_id[2] = 0;
  1019. pPrivate->pChip->cfg.unique_id[3] = 0;
  1020. LOG_DEBUG("Begin");
  1021. r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
  1022. if (r < 0)
  1023. return r;
  1024. for (x = 0; x < 4; x++) {
  1025. r = target_read_u32(pPrivate->pChip->target,
  1026. pPrivate->pBank->base + (x * 4),
  1027. &v);
  1028. if (r < 0)
  1029. return r;
  1030. pPrivate->pChip->cfg.unique_id[x] = v;
  1031. }
  1032. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
  1033. LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
  1034. r,
  1035. (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
  1036. (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
  1037. (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
  1038. (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
  1039. return r;
  1040. }
  1041. /**
  1042. * Erases the entire flash.
  1043. * @param pPrivate - the info about the bank.
  1044. */
  1045. static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
  1046. {
  1047. LOG_DEBUG("Here");
  1048. return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
  1049. }
  1050. /**
  1051. * Erases the entire flash.
  1052. * @param pPrivate - the info about the bank.
  1053. */
  1054. static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
  1055. int firstPage,
  1056. int numPages,
  1057. uint32_t *status)
  1058. {
  1059. LOG_DEBUG("Here");
  1060. uint8_t erasePages;
  1061. switch (numPages) {
  1062. case 4:
  1063. erasePages = 0x00;
  1064. break;
  1065. case 8:
  1066. erasePages = 0x01;
  1067. break;
  1068. case 16:
  1069. erasePages = 0x02;
  1070. break;
  1071. case 32:
  1072. erasePages = 0x03;
  1073. break;
  1074. default:
  1075. erasePages = 0x00;
  1076. break;
  1077. }
  1078. /* AT91C_EFC_FCMD_EPA
  1079. * According to the datasheet FARG[15:2] defines the page from which
  1080. * the erase will start.This page must be modulo 4, 8, 16 or 32
  1081. * according to the number of pages to erase. FARG[1:0] defines the
  1082. * number of pages to be erased. Previously (firstpage << 2) was used
  1083. * to conform to this, seems it should not be shifted...
  1084. */
  1085. return EFC_PerformCommand(pPrivate,
  1086. /* send Erase Page */
  1087. AT91C_EFC_FCMD_EPA,
  1088. (firstPage) | erasePages,
  1089. status);
  1090. }
  1091. /**
  1092. * Gets current GPNVM state.
  1093. * @param pPrivate - info about the bank.
  1094. * @param gpnvm - GPNVM bit index.
  1095. * @param puthere - result stored here.
  1096. */
  1097. /* ------------------------------------------------------------------------------ */
  1098. static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
  1099. {
  1100. uint32_t v;
  1101. int r;
  1102. LOG_DEBUG("Here");
  1103. if (pPrivate->bank_number != 0) {
  1104. LOG_ERROR("GPNVM only works with Bank0");
  1105. return ERROR_FAIL;
  1106. }
  1107. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  1108. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  1109. gpnvm, pPrivate->pChip->details.n_gpnvms);
  1110. return ERROR_FAIL;
  1111. }
  1112. /* Get GPNVMs status */
  1113. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
  1114. if (r != ERROR_OK) {
  1115. LOG_ERROR("Failed");
  1116. return r;
  1117. }
  1118. r = EFC_GetResult(pPrivate, &v);
  1119. if (puthere) {
  1120. /* Check if GPNVM is set */
  1121. /* get the bit and make it a 0/1 */
  1122. *puthere = (v >> gpnvm) & 1;
  1123. }
  1124. return r;
  1125. }
  1126. /**
  1127. * Clears the selected GPNVM bit.
  1128. * @param pPrivate info about the bank
  1129. * @param gpnvm GPNVM index.
  1130. * @returns 0 if successful; otherwise returns an error code.
  1131. */
  1132. static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
  1133. {
  1134. int r;
  1135. unsigned v;
  1136. LOG_DEBUG("Here");
  1137. if (pPrivate->bank_number != 0) {
  1138. LOG_ERROR("GPNVM only works with Bank0");
  1139. return ERROR_FAIL;
  1140. }
  1141. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  1142. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  1143. gpnvm, pPrivate->pChip->details.n_gpnvms);
  1144. return ERROR_FAIL;
  1145. }
  1146. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  1147. if (r != ERROR_OK) {
  1148. LOG_DEBUG("Failed: %d", r);
  1149. return r;
  1150. }
  1151. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
  1152. LOG_DEBUG("End: %d", r);
  1153. return r;
  1154. }
  1155. /**
  1156. * Sets the selected GPNVM bit.
  1157. * @param pPrivate info about the bank
  1158. * @param gpnvm GPNVM index.
  1159. */
  1160. static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
  1161. {
  1162. int r;
  1163. unsigned v;
  1164. if (pPrivate->bank_number != 0) {
  1165. LOG_ERROR("GPNVM only works with Bank0");
  1166. return ERROR_FAIL;
  1167. }
  1168. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  1169. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  1170. gpnvm, pPrivate->pChip->details.n_gpnvms);
  1171. return ERROR_FAIL;
  1172. }
  1173. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  1174. if (r != ERROR_OK)
  1175. return r;
  1176. if (v) {
  1177. /* already set */
  1178. r = ERROR_OK;
  1179. } else {
  1180. /* set it */
  1181. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
  1182. }
  1183. return r;
  1184. }
  1185. /**
  1186. * Returns a bit field (at most 64) of locked regions within a page.
  1187. * @param pPrivate info about the bank
  1188. * @param v where to store locked bits
  1189. */
  1190. static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
  1191. {
  1192. int r;
  1193. LOG_DEBUG("Here");
  1194. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
  1195. if (r == ERROR_OK) {
  1196. EFC_GetResult(pPrivate, v);
  1197. EFC_GetResult(pPrivate, v);
  1198. EFC_GetResult(pPrivate, v);
  1199. r = EFC_GetResult(pPrivate, v);
  1200. }
  1201. LOG_DEBUG("End: %d", r);
  1202. return r;
  1203. }
  1204. /**
  1205. * Unlocks all the regions in the given address range.
  1206. * @param pPrivate info about the bank
  1207. * @param start_sector first sector to unlock
  1208. * @param end_sector last (inclusive) to unlock
  1209. */
  1210. static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
  1211. unsigned start_sector,
  1212. unsigned end_sector)
  1213. {
  1214. int r;
  1215. uint32_t status;
  1216. uint32_t pg;
  1217. uint32_t pages_per_sector;
  1218. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  1219. /* Unlock all pages */
  1220. while (start_sector <= end_sector) {
  1221. pg = start_sector * pages_per_sector;
  1222. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
  1223. if (r != ERROR_OK)
  1224. return r;
  1225. start_sector++;
  1226. }
  1227. return ERROR_OK;
  1228. }
  1229. /**
  1230. * Locks regions
  1231. * @param pPrivate - info about the bank
  1232. * @param start_sector - first sector to lock
  1233. * @param end_sector - last sector (inclusive) to lock
  1234. */
  1235. static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
  1236. unsigned start_sector,
  1237. unsigned end_sector)
  1238. {
  1239. uint32_t status;
  1240. uint32_t pg;
  1241. uint32_t pages_per_sector;
  1242. int r;
  1243. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  1244. /* Lock all pages */
  1245. while (start_sector <= end_sector) {
  1246. pg = start_sector * pages_per_sector;
  1247. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
  1248. if (r != ERROR_OK)
  1249. return r;
  1250. start_sector++;
  1251. }
  1252. return ERROR_OK;
  1253. }
  1254. /****** END SAM4 CODE ********/
  1255. /* begin helpful debug code */
  1256. /* print the fieldname, the field value, in dec & hex, and return field value */
  1257. static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
  1258. const char *regname,
  1259. uint32_t value,
  1260. unsigned shift,
  1261. unsigned width)
  1262. {
  1263. uint32_t v;
  1264. int hwidth, dwidth;
  1265. /* extract the field */
  1266. v = value >> shift;
  1267. v = v & ((1 << width)-1);
  1268. if (width <= 16) {
  1269. hwidth = 4;
  1270. dwidth = 5;
  1271. } else {
  1272. hwidth = 8;
  1273. dwidth = 12;
  1274. }
  1275. /* show the basics */
  1276. LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
  1277. REG_NAME_WIDTH, regname,
  1278. dwidth, v,
  1279. hwidth, v);
  1280. return v;
  1281. }
  1282. static const char _unknown[] = "unknown";
  1283. static const char *const eproc_names[] = {
  1284. _unknown, /* 0 */
  1285. "arm946es", /* 1 */
  1286. "arm7tdmi", /* 2 */
  1287. "cortex-m3", /* 3 */
  1288. "arm920t", /* 4 */
  1289. "arm926ejs", /* 5 */
  1290. "cortex-a5", /* 6 */
  1291. "cortex-m4", /* 7 */
  1292. _unknown, /* 8 */
  1293. _unknown, /* 9 */
  1294. _unknown, /* 10 */
  1295. _unknown, /* 11 */
  1296. _unknown, /* 12 */
  1297. _unknown, /* 13 */
  1298. _unknown, /* 14 */
  1299. _unknown, /* 15 */
  1300. };
  1301. #define nvpsize2 nvpsize /* these two tables are identical */
  1302. static const char *const nvpsize[] = {
  1303. "none", /* 0 */
  1304. "8K bytes", /* 1 */
  1305. "16K bytes", /* 2 */
  1306. "32K bytes", /* 3 */
  1307. _unknown, /* 4 */
  1308. "64K bytes", /* 5 */
  1309. _unknown, /* 6 */
  1310. "128K bytes", /* 7 */
  1311. _unknown, /* 8 */
  1312. "256K bytes", /* 9 */
  1313. "512K bytes", /* 10 */
  1314. _unknown, /* 11 */
  1315. "1024K bytes", /* 12 */
  1316. _unknown, /* 13 */
  1317. "2048K bytes", /* 14 */
  1318. _unknown, /* 15 */
  1319. };
  1320. static const char *const sramsize[] = {
  1321. "48K Bytes", /* 0 */
  1322. "1K Bytes", /* 1 */
  1323. "2K Bytes", /* 2 */
  1324. "6K Bytes", /* 3 */
  1325. "112K Bytes", /* 4 */
  1326. "4K Bytes", /* 5 */
  1327. "80K Bytes", /* 6 */
  1328. "160K Bytes", /* 7 */
  1329. "8K Bytes", /* 8 */
  1330. "16K Bytes", /* 9 */
  1331. "32K Bytes", /* 10 */
  1332. "64K Bytes", /* 11 */
  1333. "128K Bytes", /* 12 */
  1334. "256K Bytes", /* 13 */
  1335. "96K Bytes", /* 14 */
  1336. "512K Bytes", /* 15 */
  1337. };
  1338. static const struct archnames { unsigned value; const char *name; } archnames[] = {
  1339. { 0x19, "AT91SAM9xx Series" },
  1340. { 0x29, "AT91SAM9XExx Series" },
  1341. { 0x34, "AT91x34 Series" },
  1342. { 0x37, "CAP7 Series" },
  1343. { 0x39, "CAP9 Series" },
  1344. { 0x3B, "CAP11 Series" },
  1345. { 0x3C, "ATSAM4E" },
  1346. { 0x40, "AT91x40 Series" },
  1347. { 0x42, "AT91x42 Series" },
  1348. { 0x43, "SAMG51 Series"
  1349. },
  1350. { 0x47, "SAMG53 Series"
  1351. },
  1352. { 0x55, "AT91x55 Series" },
  1353. { 0x60, "AT91SAM7Axx Series" },
  1354. { 0x61, "AT91SAM7AQxx Series" },
  1355. { 0x63, "AT91x63 Series" },
  1356. { 0x70, "AT91SAM7Sxx Series" },
  1357. { 0x71, "AT91SAM7XCxx Series" },
  1358. { 0x72, "AT91SAM7SExx Series" },
  1359. { 0x73, "AT91SAM7Lxx Series" },
  1360. { 0x75, "AT91SAM7Xxx Series" },
  1361. { 0x76, "AT91SAM7SLxx Series" },
  1362. { 0x80, "ATSAM3UxC Series (100-pin version)" },
  1363. { 0x81, "ATSAM3UxE Series (144-pin version)" },
  1364. { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
  1365. { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
  1366. { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
  1367. { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
  1368. { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
  1369. { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
  1370. { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
  1371. { 0x92, "AT91x92 Series" },
  1372. { 0x93, "ATSAM3NxA Series (48-pin version)" },
  1373. { 0x94, "ATSAM3NxB Series (64-pin version)" },
  1374. { 0x95, "ATSAM3NxC Series (100-pin version)" },
  1375. { 0x98, "ATSAM3SDxA Series (48-pin version)" },
  1376. { 0x99, "ATSAM3SDxB Series (64-pin version)" },
  1377. { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
  1378. { 0xA5, "ATSAM5A" },
  1379. { 0xF0, "AT75Cxx Series" },
  1380. { -1, NULL },
  1381. };
  1382. static const char *const nvptype[] = {
  1383. "rom", /* 0 */
  1384. "romless or onchip flash", /* 1 */
  1385. "embedded flash memory",/* 2 */
  1386. "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
  1387. "sram emulating flash", /* 4 */
  1388. _unknown, /* 5 */
  1389. _unknown, /* 6 */
  1390. _unknown, /* 7 */
  1391. };
  1392. static const char *_yes_or_no(uint32_t v)
  1393. {
  1394. if (v)
  1395. return "YES";
  1396. else
  1397. return "NO";
  1398. }
  1399. static const char *const _rc_freq[] = {
  1400. "4 MHz", "8 MHz", "12 MHz", "reserved"
  1401. };
  1402. static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
  1403. {
  1404. uint32_t v;
  1405. uint32_t rcen;
  1406. v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
  1407. LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
  1408. v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
  1409. LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
  1410. rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
  1411. LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
  1412. v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
  1413. LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
  1414. pChip->cfg.rc_freq = 0;
  1415. if (rcen) {
  1416. switch (v) {
  1417. default:
  1418. pChip->cfg.rc_freq = 0;
  1419. break;
  1420. case 0:
  1421. pChip->cfg.rc_freq = 4 * 1000 * 1000;
  1422. break;
  1423. case 1:
  1424. pChip->cfg.rc_freq = 8 * 1000 * 1000;
  1425. break;
  1426. case 2:
  1427. pChip->cfg.rc_freq = 12 * 1000 * 1000;
  1428. break;
  1429. }
  1430. }
  1431. v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
  1432. LOG_USER("(startup clks, time= %f uSecs)",
  1433. ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
  1434. v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
  1435. LOG_USER("(mainosc source: %s)",
  1436. v ? "external xtal" : "internal RC");
  1437. v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
  1438. LOG_USER("(clock failure enabled: %s)",
  1439. _yes_or_no(v));
  1440. }
  1441. static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
  1442. {
  1443. int x;
  1444. uint32_t v;
  1445. const char *cp;
  1446. sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
  1447. LOG_USER_N("\n");
  1448. v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
  1449. LOG_USER("%s", eproc_names[v]);
  1450. v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
  1451. LOG_USER("%s", nvpsize[v]);
  1452. v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
  1453. LOG_USER("%s", nvpsize2[v]);
  1454. v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
  1455. LOG_USER("%s", sramsize[v]);
  1456. v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
  1457. cp = _unknown;
  1458. for (x = 0; archnames[x].name; x++) {
  1459. if (v == archnames[x].value) {
  1460. cp = archnames[x].name;
  1461. break;
  1462. }
  1463. }
  1464. LOG_USER("%s", cp);
  1465. v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
  1466. LOG_USER("%s", nvptype[v]);
  1467. v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
  1468. LOG_USER("(exists: %s)", _yes_or_no(v));
  1469. }
  1470. static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
  1471. {
  1472. uint32_t v;
  1473. v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
  1474. LOG_USER("(main ready: %s)", _yes_or_no(v));
  1475. v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
  1476. v = (v * pChip->cfg.slow_freq) / 16;
  1477. pChip->cfg.mainosc_freq = v;
  1478. LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
  1479. _tomhz(v),
  1480. (uint32_t)(pChip->cfg.slow_freq / 1000),
  1481. (uint32_t)(pChip->cfg.slow_freq % 1000));
  1482. }
  1483. static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
  1484. {
  1485. uint32_t mula, diva;
  1486. diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
  1487. LOG_USER_N("\n");
  1488. mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
  1489. LOG_USER_N("\n");
  1490. pChip->cfg.plla_freq = 0;
  1491. if (mula == 0)
  1492. LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
  1493. else if (diva == 0)
  1494. LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
  1495. else if (diva >= 1) {
  1496. pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
  1497. LOG_USER("\tPLLA Freq: %3.03f MHz",
  1498. _tomhz(pChip->cfg.plla_freq));
  1499. }
  1500. }
  1501. static void sam4_explain_mckr(struct sam4_chip *pChip)
  1502. {
  1503. uint32_t css, pres, fin = 0;
  1504. int pdiv = 0;
  1505. const char *cp = NULL;
  1506. css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
  1507. switch (css & 3) {
  1508. case 0:
  1509. fin = pChip->cfg.slow_freq;
  1510. cp = "slowclk";
  1511. break;
  1512. case 1:
  1513. fin = pChip->cfg.mainosc_freq;
  1514. cp = "mainosc";
  1515. break;
  1516. case 2:
  1517. fin = pChip->cfg.plla_freq;
  1518. cp = "plla";
  1519. break;
  1520. case 3:
  1521. if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
  1522. fin = 480 * 1000 * 1000;
  1523. cp = "upll";
  1524. } else {
  1525. fin = 0;
  1526. cp = "upll (*ERROR* UPLL is disabled)";
  1527. }
  1528. break;
  1529. default:
  1530. assert(0);
  1531. break;
  1532. }
  1533. LOG_USER("%s (%3.03f Mhz)",
  1534. cp,
  1535. _tomhz(fin));
  1536. pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
  1537. switch (pres & 0x07) {
  1538. case 0:
  1539. pdiv = 1;
  1540. cp = "selected clock";
  1541. break;
  1542. case 1:
  1543. pdiv = 2;
  1544. cp = "clock/2";
  1545. break;
  1546. case 2:
  1547. pdiv = 4;
  1548. cp = "clock/4";
  1549. break;
  1550. case 3:
  1551. pdiv = 8;
  1552. cp = "clock/8";
  1553. break;
  1554. case 4:
  1555. pdiv = 16;
  1556. cp = "clock/16";
  1557. break;
  1558. case 5:
  1559. pdiv = 32;
  1560. cp = "clock/32";
  1561. break;
  1562. case 6:
  1563. pdiv = 64;
  1564. cp = "clock/64";
  1565. break;
  1566. case 7:
  1567. pdiv = 6;
  1568. cp = "clock/6";
  1569. break;
  1570. default:
  1571. assert(0);
  1572. break;
  1573. }
  1574. LOG_USER("(%s)", cp);
  1575. fin = fin / pdiv;
  1576. /* sam4 has a *SINGLE* clock - */
  1577. /* other at91 series parts have divisors for these. */
  1578. pChip->cfg.cpu_freq = fin;
  1579. pChip->cfg.mclk_freq = fin;
  1580. pChip->cfg.fclk_freq = fin;
  1581. LOG_USER("\t\tResult CPU Freq: %3.03f",
  1582. _tomhz(fin));
  1583. }
  1584. #if 0
  1585. static struct sam4_chip *target2sam4(struct target *pTarget)
  1586. {
  1587. struct sam4_chip *pChip;
  1588. if (pTarget == NULL)
  1589. return NULL;
  1590. pChip = all_sam4_chips;
  1591. while (pChip) {
  1592. if (pChip->target == pTarget)
  1593. break; /* return below */
  1594. else
  1595. pChip = pChip->next;
  1596. }
  1597. return pChip;
  1598. }
  1599. #endif
  1600. static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
  1601. {
  1602. /* this function exists to help */
  1603. /* keep funky offsetof() errors */
  1604. /* and casting from causing bugs */
  1605. /* By using prototypes - we can detect what would */
  1606. /* be casting errors. */
  1607. return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
  1608. }
  1609. #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
  1610. struct sam4_cfg, \
  1611. NAME), # NAME, FUNC }
  1612. static const struct sam4_reg_list sam4_all_regs[] = {
  1613. SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
  1614. SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
  1615. SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
  1616. SAM4_ENTRY(CKGR_UCKR, NULL),
  1617. SAM4_ENTRY(PMC_FSMR, NULL),
  1618. SAM4_ENTRY(PMC_FSPR, NULL),
  1619. SAM4_ENTRY(PMC_IMR, NULL),
  1620. SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
  1621. SAM4_ENTRY(PMC_PCK0, NULL),
  1622. SAM4_ENTRY(PMC_PCK1, NULL),
  1623. SAM4_ENTRY(PMC_PCK2, NULL),
  1624. SAM4_ENTRY(PMC_PCSR, NULL),
  1625. SAM4_ENTRY(PMC_SCSR, NULL),
  1626. SAM4_ENTRY(PMC_SR, NULL),
  1627. SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
  1628. SAM4_ENTRY(CHIPID_EXID, NULL),
  1629. /* TERMINATE THE LIST */
  1630. { .name = NULL }
  1631. };
  1632. #undef SAM4_ENTRY
  1633. static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
  1634. {
  1635. return bank->driver_priv;
  1636. }
  1637. /**
  1638. * Given a pointer to where it goes in the structure,
  1639. * determine the register name, address from the all registers table.
  1640. */
  1641. static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
  1642. {
  1643. const struct sam4_reg_list *pReg;
  1644. pReg = &(sam4_all_regs[0]);
  1645. while (pReg->name) {
  1646. uint32_t *pPossible;
  1647. /* calculate where this one go.. */
  1648. /* it is "possibly" this register. */
  1649. pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
  1650. /* well? Is it this register */
  1651. if (pPossible == goes_here) {
  1652. /* Jump for joy! */
  1653. return pReg;
  1654. }
  1655. /* next... */
  1656. pReg++;
  1657. }
  1658. /* This is *TOTAL*PANIC* - we are totally screwed. */
  1659. LOG_ERROR("INVALID SAM4 REGISTER");
  1660. return NULL;
  1661. }
  1662. static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
  1663. {
  1664. const struct sam4_reg_list *pReg;
  1665. int r;
  1666. pReg = sam4_GetReg(pChip, goes_here);
  1667. if (!pReg)
  1668. return ERROR_FAIL;
  1669. r = target_read_u32(pChip->target, pReg->address, goes_here);
  1670. if (r != ERROR_OK) {
  1671. LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
  1672. pReg->name, (unsigned)(pReg->address), r);
  1673. }
  1674. return r;
  1675. }
  1676. static int sam4_ReadAllRegs(struct sam4_chip *pChip)
  1677. {
  1678. int r;
  1679. const struct sam4_reg_list *pReg;
  1680. pReg = &(sam4_all_regs[0]);
  1681. while (pReg->name) {
  1682. r = sam4_ReadThisReg(pChip,
  1683. sam4_get_reg_ptr(&(pChip->cfg), pReg));
  1684. if (r != ERROR_OK) {
  1685. LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
  1686. pReg->name, ((unsigned)(pReg->address)), r);
  1687. return r;
  1688. }
  1689. pReg++;
  1690. }
  1691. return ERROR_OK;
  1692. }
  1693. static int sam4_GetInfo(struct sam4_chip *pChip)
  1694. {
  1695. const struct sam4_reg_list *pReg;
  1696. uint32_t regval;
  1697. pReg = &(sam4_all_regs[0]);
  1698. while (pReg->name) {
  1699. /* display all regs */
  1700. LOG_DEBUG("Start: %s", pReg->name);
  1701. regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
  1702. LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
  1703. REG_NAME_WIDTH,
  1704. pReg->name,
  1705. pReg->address,
  1706. regval);
  1707. if (pReg->explain_func)
  1708. (*(pReg->explain_func))(pChip);
  1709. LOG_DEBUG("End: %s", pReg->name);
  1710. pReg++;
  1711. }
  1712. LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
  1713. LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
  1714. LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
  1715. LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
  1716. LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
  1717. LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
  1718. pChip->cfg.unique_id[0],
  1719. pChip->cfg.unique_id[1],
  1720. pChip->cfg.unique_id[2],
  1721. pChip->cfg.unique_id[3]);
  1722. return ERROR_OK;
  1723. }
  1724. static int sam4_protect_check(struct flash_bank *bank)
  1725. {
  1726. int r;
  1727. uint32_t v[4] = {0};
  1728. unsigned x;
  1729. struct sam4_bank_private *pPrivate;
  1730. LOG_DEBUG("Begin");
  1731. if (bank->target->state != TARGET_HALTED) {
  1732. LOG_ERROR("Target not halted");
  1733. return ERROR_TARGET_NOT_HALTED;
  1734. }
  1735. pPrivate = get_sam4_bank_private(bank);
  1736. if (!pPrivate) {
  1737. LOG_ERROR("no private for this bank?");
  1738. return ERROR_FAIL;
  1739. }
  1740. if (!(pPrivate->probed))
  1741. return ERROR_FLASH_BANK_NOT_PROBED;
  1742. r = FLASHD_GetLockBits(pPrivate, v);
  1743. if (r != ERROR_OK) {
  1744. LOG_DEBUG("Failed: %d", r);
  1745. return r;
  1746. }
  1747. for (x = 0; x < pPrivate->nsectors; x++)
  1748. bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
  1749. LOG_DEBUG("Done");
  1750. return ERROR_OK;
  1751. }
  1752. FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
  1753. {
  1754. struct sam4_chip *pChip;
  1755. pChip = all_sam4_chips;
  1756. /* is this an existing chip? */
  1757. while (pChip) {
  1758. if (pChip->target == bank->target)
  1759. break;
  1760. pChip = pChip->next;
  1761. }
  1762. if (!pChip) {
  1763. /* this is a *NEW* chip */
  1764. pChip = calloc(1, sizeof(struct sam4_chip));
  1765. if (!pChip) {
  1766. LOG_ERROR("NO RAM!");
  1767. return ERROR_FAIL;
  1768. }
  1769. pChip->target = bank->target;
  1770. /* insert at head */
  1771. pChip->next = all_sam4_chips;
  1772. all_sam4_chips = pChip;
  1773. pChip->target = bank->target;
  1774. /* assumption is this runs at 32khz */
  1775. pChip->cfg.slow_freq = 32768;
  1776. pChip->probed = 0;
  1777. }
  1778. switch (bank->base) {
  1779. default:
  1780. LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
  1781. "[at91sam4s series] )",
  1782. ((unsigned int)(bank->base)),
  1783. ((unsigned int)(FLASH_BANK_BASE_S)));
  1784. return ERROR_FAIL;
  1785. break;
  1786. /* at91sam4s series only has bank 0*/
  1787. /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
  1788. case FLASH_BANK_BASE_S:
  1789. bank->driver_priv = &(pChip->details.bank[0]);
  1790. bank->bank_number = 0;
  1791. pChip->details.bank[0].pChip = pChip;
  1792. pChip->details.bank[0].pBank = bank;
  1793. break;
  1794. /* Bank 1 of at91sam4sd series */
  1795. case FLASH_BANK1_BASE_1024K_SD:
  1796. case FLASH_BANK1_BASE_2048K_SD:
  1797. bank->driver_priv = &(pChip->details.bank[1]);
  1798. bank->bank_number = 1;
  1799. pChip->details.bank[1].pChip = pChip;
  1800. pChip->details.bank[1].pBank = bank;
  1801. break;
  1802. }
  1803. /* we initialize after probing. */
  1804. return ERROR_OK;
  1805. }
  1806. static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
  1807. {
  1808. const struct sam4_chip_details *pDetails;
  1809. struct sam4_chip *pChip;
  1810. struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
  1811. unsigned x;
  1812. LOG_DEBUG("Begin");
  1813. pDetails = all_sam4_details;
  1814. while (pDetails->name) {
  1815. /* Compare cidr without version bits */
  1816. if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
  1817. break;
  1818. else
  1819. pDetails++;
  1820. }
  1821. if (pDetails->name == NULL) {
  1822. LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
  1823. (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
  1824. /* Help the victim, print details about the chip */
  1825. LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
  1826. pPrivate->pChip->cfg.CHIPID_CIDR);
  1827. sam4_explain_chipid_cidr(pPrivate->pChip);
  1828. return ERROR_FAIL;
  1829. }
  1830. /* DANGER: THERE ARE DRAGONS HERE */
  1831. /* get our pChip - it is going */
  1832. /* to be over-written shortly */
  1833. pChip = pPrivate->pChip;
  1834. /* Note that, in reality: */
  1835. /* */
  1836. /* pPrivate = &(pChip->details.bank[0]) */
  1837. /* or pPrivate = &(pChip->details.bank[1]) */
  1838. /* */
  1839. /* save the "bank" pointers */
  1840. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
  1841. saved_banks[x] = pChip->details.bank[x].pBank;
  1842. /* Overwrite the "details" structure. */
  1843. memcpy(&(pPrivate->pChip->details),
  1844. pDetails,
  1845. sizeof(pPrivate->pChip->details));
  1846. /* now fix the ghosted pointers */
  1847. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
  1848. pChip->details.bank[x].pChip = pChip;
  1849. pChip->details.bank[x].pBank = saved_banks[x];
  1850. }
  1851. /* update the *BANK*SIZE* */
  1852. LOG_DEBUG("End");
  1853. return ERROR_OK;
  1854. }
  1855. static int _sam4_probe(struct flash_bank *bank, int noise)
  1856. {
  1857. unsigned x;
  1858. int r;
  1859. struct sam4_bank_private *pPrivate;
  1860. LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
  1861. if (bank->target->state != TARGET_HALTED) {
  1862. LOG_ERROR("Target not halted");
  1863. return ERROR_TARGET_NOT_HALTED;
  1864. }
  1865. pPrivate = get_sam4_bank_private(bank);
  1866. if (!pPrivate) {
  1867. LOG_ERROR("Invalid/unknown bank number");
  1868. return ERROR_FAIL;
  1869. }
  1870. r = sam4_ReadAllRegs(pPrivate->pChip);
  1871. if (r != ERROR_OK)
  1872. return r;
  1873. LOG_DEBUG("Here");
  1874. if (pPrivate->pChip->probed)
  1875. r = sam4_GetInfo(pPrivate->pChip);
  1876. else
  1877. r = sam4_GetDetails(pPrivate);
  1878. if (r != ERROR_OK)
  1879. return r;
  1880. /* update the flash bank size */
  1881. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
  1882. if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
  1883. bank->size = pPrivate->pChip->details.bank[x].size_bytes;
  1884. break;
  1885. }
  1886. }
  1887. if (bank->sectors == NULL) {
  1888. bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
  1889. if (bank->sectors == NULL) {
  1890. LOG_ERROR("No memory!");
  1891. return ERROR_FAIL;
  1892. }
  1893. bank->num_sectors = pPrivate->nsectors;
  1894. for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
  1895. bank->sectors[x].size = pPrivate->sector_size;
  1896. bank->sectors[x].offset = x * (pPrivate->sector_size);
  1897. /* mark as unknown */
  1898. bank->sectors[x].is_erased = -1;
  1899. bank->sectors[x].is_protected = -1;
  1900. }
  1901. }
  1902. pPrivate->probed = 1;
  1903. r = sam4_protect_check(bank);
  1904. if (r != ERROR_OK)
  1905. return r;
  1906. LOG_DEBUG("Bank = %d, nbanks = %d",
  1907. pPrivate->bank_number, pPrivate->pChip->details.n_banks);
  1908. if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
  1909. /* read unique id, */
  1910. /* it appears to be associated with the *last* flash bank. */
  1911. FLASHD_ReadUniqueID(pPrivate);
  1912. }
  1913. return r;
  1914. }
  1915. static int sam4_probe(struct flash_bank *bank)
  1916. {
  1917. return _sam4_probe(bank, 1);
  1918. }
  1919. static int sam4_auto_probe(struct flash_bank *bank)
  1920. {
  1921. return _sam4_probe(bank, 0);
  1922. }
  1923. static int sam4_erase(struct flash_bank *bank, int first, int last)
  1924. {
  1925. struct sam4_bank_private *pPrivate;
  1926. int r;
  1927. int i;
  1928. int pageCount;
  1929. /*16 pages equals 8KB - Same size as a lock region*/
  1930. pageCount = 16;
  1931. uint32_t status;
  1932. LOG_DEBUG("Here");
  1933. if (bank->target->state != TARGET_HALTED) {
  1934. LOG_ERROR("Target not halted");
  1935. return ERROR_TARGET_NOT_HALTED;
  1936. }
  1937. r = sam4_auto_probe(bank);
  1938. if (r != ERROR_OK) {
  1939. LOG_DEBUG("Here,r=%d", r);
  1940. return r;
  1941. }
  1942. pPrivate = get_sam4_bank_private(bank);
  1943. if (!(pPrivate->probed))
  1944. return ERROR_FLASH_BANK_NOT_PROBED;
  1945. if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
  1946. /* whole chip */
  1947. LOG_DEBUG("Here");
  1948. return FLASHD_EraseEntireBank(pPrivate);
  1949. }
  1950. LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
  1951. LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
  1952. for (i = first; i <= last; i++) {
  1953. /*16 pages equals 8KB - Same size as a lock region*/
  1954. r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
  1955. LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
  1956. if (r != ERROR_OK)
  1957. LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
  1958. (unsigned int)(i));
  1959. if (status & (1 << 2)) {
  1960. LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
  1961. return ERROR_FAIL;
  1962. }
  1963. if (status & (1 << 1)) {
  1964. LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
  1965. return ERROR_FAIL;
  1966. }
  1967. }
  1968. return ERROR_OK;
  1969. }
  1970. static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
  1971. {
  1972. struct sam4_bank_private *pPrivate;
  1973. int r;
  1974. LOG_DEBUG("Here");
  1975. if (bank->target->state != TARGET_HALTED) {
  1976. LOG_ERROR("Target not halted");
  1977. return ERROR_TARGET_NOT_HALTED;
  1978. }
  1979. pPrivate = get_sam4_bank_private(bank);
  1980. if (!(pPrivate->probed))
  1981. return ERROR_FLASH_BANK_NOT_PROBED;
  1982. if (set)
  1983. r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
  1984. else
  1985. r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
  1986. LOG_DEBUG("End: r=%d", r);
  1987. return r;
  1988. }
  1989. static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  1990. {
  1991. uint32_t adr;
  1992. int r;
  1993. adr = pagenum * pPrivate->page_size;
  1994. adr = adr + pPrivate->base_address;
  1995. r = target_read_memory(pPrivate->pChip->target,
  1996. adr,
  1997. 4, /* THIS*MUST*BE* in 32bit values */
  1998. pPrivate->page_size / 4,
  1999. buf);
  2000. if (r != ERROR_OK)
  2001. LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
  2002. (unsigned int)(adr));
  2003. return r;
  2004. }
  2005. static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
  2006. {
  2007. uint32_t adr;
  2008. uint32_t status;
  2009. uint32_t fmr; /* EEFC Flash Mode Register */
  2010. int r;
  2011. adr = pagenum * pPrivate->page_size;
  2012. adr = (adr + pPrivate->base_address);
  2013. /* Get flash mode register value */
  2014. r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
  2015. if (r != ERROR_OK)
  2016. LOG_DEBUG("Error Read failed: read flash mode register");
  2017. /* Clear flash wait state field */
  2018. fmr &= 0xfffff0ff;
  2019. /* set FWS (flash wait states) field in the FMR (flash mode register) */
  2020. fmr |= (pPrivate->flash_wait_states << 8);
  2021. LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
  2022. r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
  2023. if (r != ERROR_OK)
  2024. LOG_DEBUG("Error Write failed: set flash mode register");
  2025. /* 1st sector 8kBytes - page 0 - 15*/
  2026. /* 2nd sector 8kBytes - page 16 - 30*/
  2027. /* 3rd sector 48kBytes - page 31 - 127*/
  2028. LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
  2029. r = target_write_memory(pPrivate->pChip->target,
  2030. adr,
  2031. 4, /* THIS*MUST*BE* in 32bit values */
  2032. pPrivate->page_size / 4,
  2033. buf);
  2034. if (r != ERROR_OK) {
  2035. LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
  2036. (unsigned int)(adr));
  2037. return r;
  2038. }
  2039. r = EFC_PerformCommand(pPrivate,
  2040. /* send Erase & Write Page */
  2041. AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
  2042. pagenum,
  2043. &status);
  2044. if (r != ERROR_OK)
  2045. LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
  2046. (unsigned int)(adr));
  2047. if (status & (1 << 2)) {
  2048. LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
  2049. return ERROR_FAIL;
  2050. }
  2051. if (status & (1 << 1)) {
  2052. LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
  2053. return ERROR_FAIL;
  2054. }
  2055. return ERROR_OK;
  2056. }
  2057. static int sam4_write(struct flash_bank *bank,
  2058. const uint8_t *buffer,
  2059. uint32_t offset,
  2060. uint32_t count)
  2061. {
  2062. int n;
  2063. unsigned page_cur;
  2064. unsigned page_end;
  2065. int r;
  2066. unsigned page_offset;
  2067. struct sam4_bank_private *pPrivate;
  2068. uint8_t *pagebuffer;
  2069. /* incase we bail further below, set this to null */
  2070. pagebuffer = NULL;
  2071. /* ignore dumb requests */
  2072. if (count == 0) {
  2073. r = ERROR_OK;
  2074. goto done;
  2075. }
  2076. if (bank->target->state != TARGET_HALTED) {
  2077. LOG_ERROR("Target not halted");
  2078. r = ERROR_TARGET_NOT_HALTED;
  2079. goto done;
  2080. }
  2081. pPrivate = get_sam4_bank_private(bank);
  2082. if (!(pPrivate->probed)) {
  2083. r = ERROR_FLASH_BANK_NOT_PROBED;
  2084. goto done;
  2085. }
  2086. if ((offset + count) > pPrivate->size_bytes) {
  2087. LOG_ERROR("Flash write error - past end of bank");
  2088. LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
  2089. (unsigned int)(offset),
  2090. (unsigned int)(count),
  2091. (unsigned int)(pPrivate->size_bytes));
  2092. r = ERROR_FAIL;
  2093. goto done;
  2094. }
  2095. pagebuffer = malloc(pPrivate->page_size);
  2096. if (!pagebuffer) {
  2097. LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
  2098. r = ERROR_FAIL;
  2099. goto done;
  2100. }
  2101. /* what page do we start & end in? */
  2102. page_cur = offset / pPrivate->page_size;
  2103. page_end = (offset + count - 1) / pPrivate->page_size;
  2104. LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
  2105. LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
  2106. /* Special case: all one page */
  2107. /* */
  2108. /* Otherwise: */
  2109. /* (1) non-aligned start */
  2110. /* (2) body pages */
  2111. /* (3) non-aligned end. */
  2112. /* Handle special case - all one page. */
  2113. if (page_cur == page_end) {
  2114. LOG_DEBUG("Special case, all in one page");
  2115. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  2116. if (r != ERROR_OK)
  2117. goto done;
  2118. page_offset = (offset & (pPrivate->page_size-1));
  2119. memcpy(pagebuffer + page_offset,
  2120. buffer,
  2121. count);
  2122. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  2123. if (r != ERROR_OK)
  2124. goto done;
  2125. r = ERROR_OK;
  2126. goto done;
  2127. }
  2128. /* non-aligned start */
  2129. page_offset = offset & (pPrivate->page_size - 1);
  2130. if (page_offset) {
  2131. LOG_DEBUG("Not-Aligned start");
  2132. /* read the partial */
  2133. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  2134. if (r != ERROR_OK)
  2135. goto done;
  2136. /* over-write with new data */
  2137. n = (pPrivate->page_size - page_offset);
  2138. memcpy(pagebuffer + page_offset,
  2139. buffer,
  2140. n);
  2141. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  2142. if (r != ERROR_OK)
  2143. goto done;
  2144. count -= n;
  2145. offset += n;
  2146. buffer += n;
  2147. page_cur++;
  2148. }
  2149. /* By checking that offset is correct here, we also
  2150. fix a clang warning */
  2151. assert(offset % pPrivate->page_size == 0);
  2152. /* intermediate large pages */
  2153. /* also - the final *terminal* */
  2154. /* if that terminal page is a full page */
  2155. LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
  2156. (int)page_cur, (int)page_end, (unsigned int)(count));
  2157. while ((page_cur < page_end) &&
  2158. (count >= pPrivate->page_size)) {
  2159. r = sam4_page_write(pPrivate, page_cur, buffer);
  2160. if (r != ERROR_OK)
  2161. goto done;
  2162. count -= pPrivate->page_size;
  2163. buffer += pPrivate->page_size;
  2164. page_cur += 1;
  2165. }
  2166. /* terminal partial page? */
  2167. if (count) {
  2168. LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
  2169. /* we have a partial page */
  2170. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  2171. if (r != ERROR_OK)
  2172. goto done;
  2173. /* data goes at start */
  2174. memcpy(pagebuffer, buffer, count);
  2175. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  2176. if (r != ERROR_OK)
  2177. goto done;
  2178. }
  2179. LOG_DEBUG("Done!");
  2180. r = ERROR_OK;
  2181. done:
  2182. if (pagebuffer)
  2183. free(pagebuffer);
  2184. return r;
  2185. }
  2186. COMMAND_HANDLER(sam4_handle_info_command)
  2187. {
  2188. struct sam4_chip *pChip;
  2189. pChip = get_current_sam4(CMD_CTX);
  2190. if (!pChip)
  2191. return ERROR_OK;
  2192. unsigned x;
  2193. int r;
  2194. /* bank0 must exist before we can do anything */
  2195. if (pChip->details.bank[0].pBank == NULL) {
  2196. x = 0;
  2197. need_define:
  2198. command_print(CMD_CTX,
  2199. "Please define bank %d via command: flash bank %s ... ",
  2200. x,
  2201. at91sam4_flash.name);
  2202. return ERROR_FAIL;
  2203. }
  2204. /* if bank 0 is not probed, then probe it */
  2205. if (!(pChip->details.bank[0].probed)) {
  2206. r = sam4_auto_probe(pChip->details.bank[0].pBank);
  2207. if (r != ERROR_OK)
  2208. return ERROR_FAIL;
  2209. }
  2210. /* above guarantees the "chip details" structure is valid */
  2211. /* and thus, bank private areas are valid */
  2212. /* and we have a SAM4 chip, what a concept! */
  2213. /* auto-probe other banks, 0 done above */
  2214. for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
  2215. /* skip banks not present */
  2216. if (!(pChip->details.bank[x].present))
  2217. continue;
  2218. if (pChip->details.bank[x].pBank == NULL)
  2219. goto need_define;
  2220. if (pChip->details.bank[x].probed)
  2221. continue;
  2222. r = sam4_auto_probe(pChip->details.bank[x].pBank);
  2223. if (r != ERROR_OK)
  2224. return r;
  2225. }
  2226. r = sam4_GetInfo(pChip);
  2227. if (r != ERROR_OK) {
  2228. LOG_DEBUG("Sam4Info, Failed %d", r);
  2229. return r;
  2230. }
  2231. return ERROR_OK;
  2232. }
  2233. COMMAND_HANDLER(sam4_handle_gpnvm_command)
  2234. {
  2235. unsigned x, v;
  2236. int r, who;
  2237. struct sam4_chip *pChip;
  2238. pChip = get_current_sam4(CMD_CTX);
  2239. if (!pChip)
  2240. return ERROR_OK;
  2241. if (pChip->target->state != TARGET_HALTED) {
  2242. LOG_ERROR("sam4 - target not halted");
  2243. return ERROR_TARGET_NOT_HALTED;
  2244. }
  2245. if (pChip->details.bank[0].pBank == NULL) {
  2246. command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
  2247. at91sam4_flash.name);
  2248. return ERROR_FAIL;
  2249. }
  2250. if (!pChip->details.bank[0].probed) {
  2251. r = sam4_auto_probe(pChip->details.bank[0].pBank);
  2252. if (r != ERROR_OK)
  2253. return r;
  2254. }
  2255. switch (CMD_ARGC) {
  2256. default:
  2257. return ERROR_COMMAND_SYNTAX_ERROR;
  2258. break;
  2259. case 0:
  2260. goto showall;
  2261. break;
  2262. case 1:
  2263. who = -1;
  2264. break;
  2265. case 2:
  2266. if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
  2267. who = -1;
  2268. else {
  2269. uint32_t v32;
  2270. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
  2271. who = v32;
  2272. }
  2273. break;
  2274. }
  2275. if (0 == strcmp("show", CMD_ARGV[0])) {
  2276. if (who == -1) {
  2277. showall:
  2278. r = ERROR_OK;
  2279. for (x = 0; x < pChip->details.n_gpnvms; x++) {
  2280. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
  2281. if (r != ERROR_OK)
  2282. break;
  2283. command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
  2284. }
  2285. return r;
  2286. }
  2287. if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
  2288. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
  2289. command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
  2290. return r;
  2291. } else {
  2292. command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
  2293. return ERROR_COMMAND_SYNTAX_ERROR;
  2294. }
  2295. }
  2296. if (who == -1) {
  2297. command_print(CMD_CTX, "Missing GPNVM number");
  2298. return ERROR_COMMAND_SYNTAX_ERROR;
  2299. }
  2300. if (0 == strcmp("set", CMD_ARGV[0]))
  2301. r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
  2302. else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
  2303. (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
  2304. r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
  2305. else {
  2306. command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
  2307. r = ERROR_COMMAND_SYNTAX_ERROR;
  2308. }
  2309. return r;
  2310. }
  2311. COMMAND_HANDLER(sam4_handle_slowclk_command)
  2312. {
  2313. struct sam4_chip *pChip;
  2314. pChip = get_current_sam4(CMD_CTX);
  2315. if (!pChip)
  2316. return ERROR_OK;
  2317. switch (CMD_ARGC) {
  2318. case 0:
  2319. /* show */
  2320. break;
  2321. case 1:
  2322. {
  2323. /* set */
  2324. uint32_t v;
  2325. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
  2326. if (v > 200000) {
  2327. /* absurd slow clock of 200Khz? */
  2328. command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
  2329. return ERROR_COMMAND_SYNTAX_ERROR;
  2330. }
  2331. pChip->cfg.slow_freq = v;
  2332. break;
  2333. }
  2334. default:
  2335. /* error */
  2336. command_print(CMD_CTX, "Too many parameters");
  2337. return ERROR_COMMAND_SYNTAX_ERROR;
  2338. break;
  2339. }
  2340. command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
  2341. (int)(pChip->cfg.slow_freq / 1000),
  2342. (int)(pChip->cfg.slow_freq % 1000));
  2343. return ERROR_OK;
  2344. }
  2345. static const struct command_registration at91sam4_exec_command_handlers[] = {
  2346. {
  2347. .name = "gpnvm",
  2348. .handler = sam4_handle_gpnvm_command,
  2349. .mode = COMMAND_EXEC,
  2350. .usage = "[('clr'|'set'|'show') bitnum]",
  2351. .help = "Without arguments, shows all bits in the gpnvm "
  2352. "register. Otherwise, clears, sets, or shows one "
  2353. "General Purpose Non-Volatile Memory (gpnvm) bit.",
  2354. },
  2355. {
  2356. .name = "info",
  2357. .handler = sam4_handle_info_command,
  2358. .mode = COMMAND_EXEC,
  2359. .help = "Print information about the current at91sam4 chip"
  2360. "and its flash configuration.",
  2361. },
  2362. {
  2363. .name = "slowclk",
  2364. .handler = sam4_handle_slowclk_command,
  2365. .mode = COMMAND_EXEC,
  2366. .usage = "[clock_hz]",
  2367. .help = "Display or set the slowclock frequency "
  2368. "(default 32768 Hz).",
  2369. },
  2370. COMMAND_REGISTRATION_DONE
  2371. };
  2372. static const struct command_registration at91sam4_command_handlers[] = {
  2373. {
  2374. .name = "at91sam4",
  2375. .mode = COMMAND_ANY,
  2376. .help = "at91sam4 flash command group",
  2377. .usage = "",
  2378. .chain = at91sam4_exec_command_handlers,
  2379. },
  2380. COMMAND_REGISTRATION_DONE
  2381. };
  2382. struct flash_driver at91sam4_flash = {
  2383. .name = "at91sam4",
  2384. .commands = at91sam4_command_handlers,
  2385. .flash_bank_command = sam4_flash_bank_command,
  2386. .erase = sam4_erase,
  2387. .protect = sam4_protect,
  2388. .write = sam4_write,
  2389. .read = default_flash_read,
  2390. .probe = sam4_probe,
  2391. .auto_probe = sam4_auto_probe,
  2392. .erase_check = default_flash_blank_check,
  2393. .protect_check = sam4_protect_check,
  2394. };