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Author	SHA1	Message	Date
Jim Paris	431f387b55	Fix line endings	2013-06-12 18:40:40 -04:00
jim	b95491274d	Set up 128 KHz 12-bit ADC sampling with DMA, and send to UART at 0.5 Mbps. Seems to work well. Next step is to process ADC data at 128 KHz to determine DAC stepping, and send DAC + ADC to PC at 8 KHz. git-svn-id: https://bucket.mit.edu/svn/nilm/zoom@5931 ddd99763-3ecb-0310-9145-efcb8ce7c51f	2008-02-12 05:24:34 +00:00
jim	136fb77276	Start refactoring timer stuff for internal ADC git-svn-id: https://bucket.mit.edu/svn/nilm/zoom@5928 ddd99763-3ecb-0310-9145-efcb8ce7c51f	2008-02-12 02:58:54 +00:00

Author

SHA1

Message

Date

Jim Paris

431f387b55

Fix line endings

2013-06-12 18:40:40 -04:00

jim

b95491274d

Set up 128 KHz 12-bit ADC sampling with DMA, and send to UART at 0.5 Mbps.

Seems to work well.
Next step is to process ADC data at 128 KHz to determine DAC stepping,
and send DAC + ADC to PC at 8 KHz.




git-svn-id: https://bucket.mit.edu/svn/nilm/zoom@5931 ddd99763-3ecb-0310-9145-efcb8ce7c51f

2008-02-12 05:24:34 +00:00

jim

136fb77276

Start refactoring timer stuff for internal ADC

git-svn-id: https://bucket.mit.edu/svn/nilm/zoom@5928 ddd99763-3ecb-0310-9145-efcb8ce7c51f

2008-02-12 02:58:54 +00:00

3 Commits