Browse Source

Remove whitespace at end of lines, step 1.

- Replace '\s*$' with ''.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
tags/v0.2.0
zwelch 13 years ago
parent
commit
2e77919853
37 changed files with 858 additions and 858 deletions
  1. +21
    -21
      src/flash/aduc702x.c
  2. +21
    -21
      src/flash/at91sam7.c
  3. +7
    -7
      src/flash/cfi.c
  4. +23
    -23
      src/flash/flash.c
  5. +14
    -14
      src/flash/flash.h
  6. +14
    -14
      src/flash/mflash.c
  7. +3
    -3
      src/flash/nand.c
  8. +1
    -1
      src/flash/ocl/at91sam7x/samflash.c
  9. +7
    -7
      src/flash/pic32mx.c
  10. +13
    -13
      src/flash/stellaris.c
  11. +94
    -94
      src/flash/str7x.c
  12. +10
    -10
      src/flash/tms470.c
  13. +1
    -1
      src/target/algorithm.h
  14. +5
    -5
      src/target/arm11.c
  15. +3
    -3
      src/target/arm926ejs.h
  16. +1
    -1
      src/target/arm9tdmi.h
  17. +1
    -1
      src/target/arm_adi_v5.h
  18. +195
    -195
      src/target/arm_disassembler.c
  19. +15
    -15
      src/target/arm_disassembler.h
  20. +1
    -1
      src/target/arm_jtag.c
  21. +57
    -57
      src/target/arm_simulator.c
  22. +3
    -3
      src/target/armv4_5.c
  23. +7
    -7
      src/target/armv7m.c
  24. +16
    -16
      src/target/armv7m.h
  25. +22
    -22
      src/target/breakpoints.c
  26. +6
    -6
      src/target/cortex_m3.h
  27. +15
    -15
      src/target/feroceon.c
  28. +56
    -56
      src/target/mips32.c
  29. +3
    -3
      src/target/mips32.h
  30. +1
    -1
      src/target/mips32_dmaacc.c
  31. +89
    -89
      src/target/mips32_pracc.c
  32. +17
    -17
      src/target/mips_ejtag.c
  33. +19
    -19
      src/target/mips_m4k.c
  34. +65
    -65
      src/target/target.c
  35. +15
    -15
      src/target/trace.c
  36. +14
    -14
      src/target/xscale.h
  37. +3
    -3
      src/target/xscale/protocol.h

+ 21
- 21
src/flash/aduc702x.c View File

@@ -109,10 +109,10 @@ static int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *
static int aduc702x_build_sector_list(struct flash_bank_s *bank)
{
//aduc7026_flash_bank_t *aduc7026_info = bank->driver_priv;
int i = 0;
uint32_t offset = 0;
// sector size is 512
bank->num_sectors = bank->size / 512;
bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
@@ -203,7 +203,7 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
reg_param_t reg_params[6];
armv4_5_algorithm_t armv4_5_info;
int retval = ERROR_OK;
/* parameters:

r0 - address of source data (absolute)
@@ -240,7 +240,7 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
//<done>:
0xeafffffe // b 1003c <done>
};
/* flash write code */
if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
&aduc702x_info->write_algorithm) != ERROR_OK)
@@ -248,8 +248,8 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
target_write_buffer(target, aduc702x_info->write_algorithm->address,
target_write_buffer(target, aduc702x_info->write_algorithm->address,
sizeof(aduc702x_flash_write_code), (uint8_t*)aduc702x_flash_write_code);

/* memory buffer */
@@ -261,26 +261,26 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
if (aduc702x_info->write_algorithm)
target_free_working_area(target, aduc702x_info->write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
while (count > 0)
{
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
target_write_buffer(target, source->address, thisrun_count * 2, buffer);

buf_set_u32(reg_params[0].value, 0, 32, source->address);
@@ -288,16 +288,16 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);

if ((retval = target_run_algorithm(target, 0, NULL, 5,
reg_params, aduc702x_info->write_algorithm->address,
aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
if ((retval = target_run_algorithm(target, 0, NULL, 5,
reg_params, aduc702x_info->write_algorithm->address,
aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
10000, &armv4_5_info)) != ERROR_OK)
{
LOG_ERROR("error executing aduc702x flash write algorithm");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
retval = ERROR_FLASH_OPERATION_FAILED;
break;
@@ -310,24 +310,24 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint

target_free_working_area(target, source);
target_free_working_area(target, aduc702x_info->write_algorithm);
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);
destroy_reg_param(&reg_params[2]);
destroy_reg_param(&reg_params[3]);
destroy_reg_param(&reg_params[4]);
return retval;
}

/* All-JTAG, single-access method. Very slow. Used only if there is no
/* All-JTAG, single-access method. Very slow. Used only if there is no
* working area available. */
static int aduc702x_write_single(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
uint32_t x;
uint8_t b;
target_t *target = bank->target;
aduc702x_set_write_enable(target, 1);

for (x = 0; x < count; x += 2) {
@@ -373,13 +373,13 @@ int aduc702x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset,
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
/* if block write failed (no sufficient working area),
* use normal (slow) JTAG method */
* use normal (slow) JTAG method */
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");

if ((retval = aduc702x_write_single(bank, buffer, offset, count)) != ERROR_OK)
{
LOG_ERROR("slow write failed");
return ERROR_FLASH_OPERATION_FAILED;
return ERROR_FLASH_OPERATION_FAILED;
}
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)


+ 21
- 21
src/flash/at91sam7.c View File

@@ -57,7 +57,7 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

flash_driver_t at91sam7_flash =
@@ -85,8 +85,8 @@ static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","AR
static long SRAMSIZ[16] = {
-1,
0x0400, /* 1K */
0x0800, /* 2K */
-1,
0x0800, /* 2K */
-1,
0x1c000, /* 112K */
0x1000, /* 4K */
0x14000, /* 80K */
@@ -135,10 +135,10 @@ static void at91sam7_read_clock_info(flash_bank_t *bank)
target_read_u32(target, PMC_MCKR, &mckr);
/* Read Clock Generator PLL Register */
target_read_u32(target, CKGR_PLLR, &pllr);
at91sam7_info->mck_valid = 0;
at91sam7_info->mck_freq = 0;
switch (mckr & PMC_MCKR_CSS)
switch (mckr & PMC_MCKR_CSS)
{
case 0: /* Slow Clock */
at91sam7_info->mck_valid = 1;
@@ -146,7 +146,7 @@ static void at91sam7_read_clock_info(flash_bank_t *bank)
break;

case 1: /* Main Clock */
if ((mcfr & CKGR_MCFR_MAINRDY) &&
if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
{
at91sam7_info->mck_valid = 1;
@@ -163,8 +163,8 @@ static void at91sam7_read_clock_info(flash_bank_t *bank)
break;

case 3: /* PLL Clock */
if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
{
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
@@ -280,7 +280,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;

fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);

@@ -294,7 +294,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
return ERROR_OK;
}

if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
{
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -635,7 +635,7 @@ static int at91sam7_erase_check(struct flash_bank_s *bank)
}

/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);

fast_check = 1;
@@ -892,7 +892,7 @@ static int at91sam7_erase(struct flash_bank_s *bank, int first, int last)

if (erase_all)
{
if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -1079,13 +1079,13 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
buf += printed;
buf_size -= printed;

printed = snprintf(buf,
printed = snprintf(buf,
buf_size,
" Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
at91sam7_info->cidr,
at91sam7_info->cidr_arch,
at91sam7_info->cidr,
at91sam7_info->cidr_arch,
EPROC[at91sam7_info->cidr_eproc],
at91sam7_info->cidr_version,
at91sam7_info->cidr_version,
bank->size);

buf += printed;
@@ -1117,10 +1117,10 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
return ERROR_OK;
}

/*
* On AT91SAM7S: When the gpnvm bits are set with
/*
* On AT91SAM7S: When the gpnvm bits are set with
* > at91sam7 gpnvm bitnr set
* the changes are not visible in the flash controller status register MC_FSR
* the changes are not visible in the flash controller status register MC_FSR
* until the processor has been reset.
* On the Olimex board this requires a power cycle.
* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
@@ -1191,7 +1191,7 @@ static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
@@ -1203,6 +1203,6 @@ static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char

/* check protect state */
at91sam7_protect_check(bank);
return ERROR_OK;
}

+ 7
- 7
src/flash/cfi.c View File

@@ -378,9 +378,9 @@ static int cfi_read_intel_pri_ext(flash_bank_t *bank)
pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);

LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
pri_ext->blk_status_reg_mask);

pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
@@ -1597,7 +1597,7 @@ static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, uint3
/* Check for valid range */
if (address & buffermask)
{
LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -2279,9 +2279,9 @@ static int cfi_probe(struct flash_bank_s *bank)
for (i = 0; i < cfi_info->num_erase_regions; i++)
{
cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
(cfi_info->erase_region_info[i] >> 16) * 256);
}
}


+ 23
- 23
src/flash/flash.c View File

@@ -92,7 +92,7 @@ static int flash_driver_write(struct flash_bank_s *bank, uint8_t *buffer, uint32
retval = bank->driver->write(bank, buffer, offset, count);
if (retval != ERROR_OK)
{
LOG_ERROR("error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32 " (%d)",
LOG_ERROR("error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32 " (%d)",
bank->base, offset, retval);
}

@@ -350,13 +350,13 @@ static int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cm
if ((retval = p->driver->auto_probe(p)) != ERROR_OK)
return retval;

command_print(cmd_ctx,
command_print(cmd_ctx,
"#%" PRIi32 " : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", buswidth %i, chipwidth %i",
i,
p->driver->name,
p->base,
p->size,
p->bus_width,
p->driver->name,
p->base,
p->size,
p->bus_width,
p->chip_width);
for (j = 0; j < p->num_sectors; j++)
{
@@ -369,11 +369,11 @@ static int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cm
else
protect_state = "protection state unknown";

command_print(cmd_ctx,
command_print(cmd_ctx,
"\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
j,
p->sectors[j].offset,
p->sectors[j].size,
p->sectors[j].offset,
p->sectors[j].size,
p->sectors[j].size >> 10,
protect_state);
}
@@ -462,9 +462,9 @@ static int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, c

command_print(cmd_ctx,
"\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
j,
p->sectors[j].offset,
p->sectors[j].size,
j,
p->sectors[j].offset,
p->sectors[j].size,
p->sectors[j].size >> 10,
erase_state);
}
@@ -708,10 +708,10 @@ static int handle_flash_write_image_command(struct command_context_s *cmd_ctx, c
}
if (retval == ERROR_OK)
{
command_print(cmd_ctx,
command_print(cmd_ctx,
"wrote %" PRIu32 " byte from file %s in %s (%f kb/s)",
written,
args[0],
args[0],
duration_text,
(float)written / 1024.0 / ((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0)));
}
@@ -813,7 +813,7 @@ static int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cm
{
if (readback[i]!=chunk[i])
{
LOG_ERROR("Verfication error address 0x%08" PRIx32 ", read back 0x%02x, expected 0x%02x",
LOG_ERROR("Verfication error address 0x%08" PRIx32 ", read back 0x%02x, expected 0x%02x",
address + wrote + i, readback[i], chunk[i]);
return ERROR_FAIL;
}
@@ -831,10 +831,10 @@ static int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cm
float speed;
speed = wrote / 1024.0;
speed/=((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0));
command_print(cmd_ctx,
command_print(cmd_ctx,
"wrote %" PRId32 " bytes to 0x%8.8" PRIx32 " in %s (%f kb/s)",
count*wordsize,
address,
count*wordsize,
address,
duration_text,
speed);
}
@@ -896,12 +896,12 @@ static int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, ch
}
if (retval == ERROR_OK)
{
command_print(cmd_ctx,
command_print(cmd_ctx,
"wrote %lld byte from file %s to flash bank %li at offset 0x%8.8" PRIx32 " in %s (%f kb/s)",
fileio.size,
args[1],
strtoul(args[0], NULL, 0),
offset,
fileio.size,
args[1],
strtoul(args[0], NULL, 0),
offset,
duration_text,
(float)fileio.size / 1024.0 / ((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0)));
}


+ 14
- 14
src/flash/flash.h View File

@@ -81,13 +81,13 @@ struct flash_bank_s;
*/
typedef struct flash_driver_s
{
/**
/**
* Gives a human-readable name of this flash driver,
* This field is used to select and initialize the driver.
*/
char *name;

/**
/**
* Registers driver-specific commands. When called (during the
* "flash bank" command), the driver may register addition
* commands to support new flash chip functions.
@@ -96,12 +96,12 @@ typedef struct flash_driver_s
*/
int (*register_commands)(struct command_context_s *cmd_ctx);

/**
/**
* Finish the "flash bank" command for @a bank. The
* @a bank parameter will have been filled in by the core flash
* layer when this routine is called, and the driver can store
* additional information in its flash_bank_t::driver_priv field.
*
*
* @param cmd_ctx - the command context
* @param cmd - the command, in this case 'flash'
* @param args - parameters, see below
@@ -112,7 +112,7 @@ typedef struct flash_driver_s
* @code
* args[0] = bank
* args[1] = drivername {name above}
* args[2] = baseaddress
* args[2] = baseaddress
* args[3] = lengthbytes
* args[4] = chip_width_in bytes
* args[5] = bus_width_bytes
@@ -129,7 +129,7 @@ typedef struct flash_driver_s
*/
int (*flash_bank_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);

/**
/**
* Bank/sector erase routine (target-specific). When
* called, the flash driver should erase the specified sectors
* using whatever means are at its disposal.
@@ -141,7 +141,7 @@ typedef struct flash_driver_s
*/
int (*erase)(struct flash_bank_s *bank, int first, int last);

/**
/**
* Bank/sector protection routine (target-specific).
* When called, the driver should disable 'flash write' bits (or
* enable 'erase protection' bits) for the given @a bank and @a
@@ -155,7 +155,7 @@ typedef struct flash_driver_s
*/
int (*protect)(struct flash_bank_s *bank, int set, int first, int last);

/**
/**
* Program data into the flash. Note CPU address will be
* "bank->base + offset", while the physical address is
* dependent upon current target MMU mappings.
@@ -168,7 +168,7 @@ typedef struct flash_driver_s
*/
int (*write)(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);

/**
/**
* Probe to determine what kind of flash is present.
* This is invoked by the "probe" script command.
*
@@ -176,8 +176,8 @@ typedef struct flash_driver_s
* @returns ERROR_OK if successful; otherwise, an error code.
*/
int (*probe)(struct flash_bank_s *bank);
/**
/**
* Check the erasure status of a flash bank.
* When called, the driver routine must perform the required
* checks and then set the @c flash_sector_s::is_erased field
@@ -209,7 +209,7 @@ typedef struct flash_driver_s
* @param char - where to put the text for the human to read
* @param buf_size - the size of the human buffer.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
*/
int (*info)(struct flash_bank_s *bank, char *buf, int buf_size);

/**
@@ -228,7 +228,7 @@ typedef struct flash_driver_s
int (*auto_probe)(struct flash_bank_s *bank);
} flash_driver_t;

/**
/**
* Provides details of a flash bank, available either on-chip or through
* a major interface.
*
@@ -276,7 +276,7 @@ extern int flash_init_drivers(struct command_context_s *cmd_ctx);
extern int flash_erase_address_range(struct target_s *target, uint32_t addr, uint32_t length);
/**
* Writes @a image into the @a target flash. The @a written parameter
* will contain the
* will contain the
* @param target The target with the flash to be programmed.
* @param image The image that will be programmed to flash.
* @param written On return, contains the number of bytes written.


+ 14
- 14
src/flash/mflash.c View File

@@ -474,7 +474,7 @@ static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt
residue = sect_cnt % 256;

for (i = 0; i < quotient; i++) {
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : 0x%0lx", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : 0x%0lx", sect_num,
(unsigned long)buff_ptr);
ret = mg_mflash_do_read_sects(buff_ptr, sect_num, 256);
if (ret != ERROR_OK)
@@ -485,7 +485,7 @@ static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt
}

if (residue) {
LOG_DEBUG("mflash: sect num : %" PRIx32 " buff : %0lx", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIx32 " buff : %0lx", sect_num,
(unsigned long)buff_ptr);
return mg_mflash_do_read_sects(buff_ptr, sect_num, residue);
}
@@ -517,7 +517,7 @@ static int mg_mflash_do_write_sects(void *buff, uint32_t sect_num, uint32_t sect
ret = target_write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
if (ret != ERROR_OK)
return ret;
buff_ptr += MG_MFLASH_SECTOR_SIZE;

ret = target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_write);
@@ -552,7 +552,7 @@ static int mg_mflash_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cn
residue = sect_cnt % 256;

for (i = 0; i < quotient; i++) {
LOG_DEBUG("mflash: sect num : %" PRIu32 "buff : %p", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIu32 "buff : %p", sect_num,
buff_ptr);
ret = mg_mflash_do_write_sects(buff_ptr, sect_num, 256, mg_io_cmd_write);
if (ret != ERROR_OK)
@@ -563,7 +563,7 @@ static int mg_mflash_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cn
}

if (residue) {
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p", sect_num,
buff_ptr);
return mg_mflash_do_write_sects(buff_ptr, sect_num, residue, mg_io_cmd_write);
}
@@ -741,10 +741,10 @@ static int mg_write_cmd(struct command_context_s *cmd_ctx, char *cmd, char **arg
goto mg_write_cmd_err;
address += MG_FILEIO_CHUNK;
}
if (res) {
if ((ret = fileio_read(&fileio, res, buffer, &buf_cnt)) != ERROR_OK)
goto mg_write_cmd_err;
goto mg_write_cmd_err;
if ((ret = mg_mflash_write(address, buffer, res)) != ERROR_OK)
goto mg_write_cmd_err;
}
@@ -789,7 +789,7 @@ static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args
ret = fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY);
if (ret != ERROR_OK)
return ret;
buffer = malloc(MG_FILEIO_CHUNK);
if (!buffer) {
fileio_close(&fileio);
@@ -798,7 +798,7 @@ static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args

cnt = size / MG_FILEIO_CHUNK;
res = size % MG_FILEIO_CHUNK;
duration_start_measure(&duration);

for (i = 0; i < cnt; i++) {
@@ -809,7 +809,7 @@ static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args
goto mg_dump_cmd_err;
address += MG_FILEIO_CHUNK;
}
if (res) {
if ((ret = mg_mflash_read(address, buffer, res)) != ERROR_OK)
goto mg_dump_cmd_err;
@@ -834,8 +834,8 @@ mg_dump_cmd_err:
free(duration_text);
free(buffer);
fileio_close(&fileio);
return ret;
return ret;
}

static int mg_set_feature(mg_feature_id feature, mg_feature_val config)
@@ -1229,7 +1229,7 @@ int mg_config_cmd(struct command_context_s *cmd_ctx, char *cmd,

switch (argc) {
case 2:
if (!strcmp(args[1], "boot"))
if (!strcmp(args[1], "boot"))
return mg_boot_config();
else if (!strcmp(args[1], "storage"))
return mg_storage_config();
@@ -1252,7 +1252,7 @@ int mg_config_cmd(struct command_context_s *cmd_ctx, char *cmd,
return ERROR_MG_INVALID_PLL;
}

LOG_INFO("mflash: Fout=%" PRIu32 " Hz, feedback=%u,"
LOG_INFO("mflash: Fout=%" PRIu32 " Hz, feedback=%u,"
"indiv=%u, outdiv=%u, lock=%u",
(uint32_t)fout, pll.feedback_div,
pll.input_div, pll.output_div,


+ 3
- 3
src/flash/nand.c View File

@@ -1138,12 +1138,12 @@ static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd
else
bad_state = " (block condition unknown)";

command_print(cmd_ctx,
command_print(cmd_ctx,
"\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
j,
p->blocks[j].offset,
p->blocks[j].offset,
p->blocks[j].size / 1024,
erase_state,
erase_state,
bad_state);
}
}


+ 1
- 1
src/flash/ocl/at91sam7x/samflash.c View File

@@ -174,7 +174,7 @@ int flash_erase_plane(int efc_ofs)
int flash_erase_all(void)
{
int result;
if ((result = flash_erase_plane(0)) != FLASH_STAT_OK) return result;

/* the second flash controller, if any */


+ 7
- 7
src/flash/pic32mx.c View File

@@ -603,10 +603,10 @@ static int pic32mx_probe(struct flash_bank_s *bank)
pic32mx_info->probed = 0;

device_id = ejtag_info->idcode;
LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%02x, ver 0x%03x)",
LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%02x, ver 0x%03x)",
device_id,
(unsigned)((device_id >> 1)&0x7ff),
(unsigned)((device_id >> 12)&0xff),
(unsigned)((device_id >> 1)&0x7ff),
(unsigned)((device_id >> 12)&0xff),
(unsigned)((device_id >> 20)&0xfff));

if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
@@ -698,9 +698,9 @@ static int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)
device_id = ejtag_info->idcode;

if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
snprintf(buf, buf_size,
"Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
(unsigned)((device_id >> 1)&0x7ff),
snprintf(buf, buf_size,
"Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
(unsigned)((device_id >> 1)&0x7ff),
PIC32MX_MANUF_ID);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -715,7 +715,7 @@ static int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)
}
buf += printed;
buf_size -= printed;
printed = snprintf(buf, buf_size, " Ver: 0x%03x",
printed = snprintf(buf, buf_size, " Ver: 0x%03x",
(unsigned)((device_id >> 20)&0xfff));

return ERROR_OK;


+ 13
- 13
src/flash/stellaris.c View File

@@ -292,32 +292,32 @@ static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
device_class = 0;
}
printed = snprintf(buf,
printed = snprintf(buf,
buf_size,
"\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
device_class,
StellarisClassname[device_class],
device_class,
StellarisClassname[device_class],
stellaris_info->target_name,
(int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
(int)((stellaris_info->did0) & 0xFF));
buf += printed;
buf_size -= printed;

printed = snprintf(buf,
buf_size,
printed = snprintf(buf,
buf_size,
"did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32 ", eproc: %s, ramsize:%ik, flashsize: %ik\n",
stellaris_info->did1,
stellaris_info->did1,
"ARMV7M",
stellaris_info->did1,
stellaris_info->did1,
"ARMV7M",
(int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
(int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
buf += printed;
buf_size -= printed;

printed = snprintf(buf,
printed = snprintf(buf,
buf_size,
"master clock(estimated): %ikHz, rcc is 0x%" PRIx32 " \n",
(int)(stellaris_info->mck_freq / 1000),
(int)(stellaris_info->mck_freq / 1000),
stellaris_info->rcc);
buf += printed;
buf_size -= printed;
@@ -326,9 +326,9 @@ static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
printed = snprintf(buf,
buf_size,
"pagesize: %" PRIi32 ", lockbits: %i 0x%4.4" PRIx32 ", pages in lock region: %i \n",
stellaris_info->pagesize,
stellaris_info->num_lockbits,
"pagesize: %" PRIi32 ", lockbits: %i 0x%4.4" PRIx32 ", pages in lock region: %i \n",
stellaris_info->pagesize,
stellaris_info->num_lockbits,
stellaris_info->lockbits,
(int)(stellaris_info->num_pages/stellaris_info->num_lockbits));
buf += printed;


+ 94
- 94
src/flash/str7x.c View File

@@ -75,10 +75,10 @@ flash_driver_t str7x_flash =
static int str7x_register_commands(struct command_context_s *cmd_ctx)
{
command_t *str7x_cmd = register_command(cmd_ctx, NULL, "str7x", NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, str7x_cmd, "disable_jtag", str7x_handle_disable_jtag_command, COMMAND_EXEC,
"disable jtag access");
return ERROR_OK;
}

@@ -95,7 +95,7 @@ static int str7x_build_block_list(struct flash_bank_s *bank)
int i;
int num_sectors;
int b0_sectors = 0, b1_sectors = 0;
switch (bank->size)
{
case 16 * 1024:
@@ -114,15 +114,15 @@ static int str7x_build_block_list(struct flash_bank_s *bank)
LOG_ERROR("BUG: unknown bank->size encountered");
exit(-1);
}
num_sectors = b0_sectors + b1_sectors;
bank->num_sectors = num_sectors;
bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
num_sectors = 0;
for (i = 0; i < b0_sectors; i++)
{
bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
@@ -131,7 +131,7 @@ static int str7x_build_block_list(struct flash_bank_s *bank)
bank->sectors[num_sectors].is_protected = 1;
str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
}
for (i = 0; i < b1_sectors; i++)
{
bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
@@ -140,7 +140,7 @@ static int str7x_build_block_list(struct flash_bank_s *bank)
bank->sectors[num_sectors].is_protected = 1;
str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
}
return ERROR_OK;
}

@@ -149,20 +149,20 @@ static int str7x_build_block_list(struct flash_bank_s *bank)
static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
str7x_flash_bank_t *str7x_info;
if (argc < 7)
{
LOG_WARNING("incomplete flash_bank str7x configuration");
return ERROR_FLASH_BANK_INVALID;
}
str7x_info = malloc(sizeof(str7x_flash_bank_t));
bank->driver_priv = str7x_info;
/* set default bits for str71x flash */
str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
str7x_info->disable_bit = (1 << 1);
if (strcmp(args[6], "STR71x") == 0)
{
str7x_info->register_base = 0x40100000;
@@ -185,9 +185,9 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
}

str7x_build_block_list(bank);
str7x_info->write_algorithm = NULL;
return ERROR_OK;
}

@@ -207,7 +207,7 @@ static uint32_t str7x_result(struct flash_bank_s *bank)
uint32_t retval;

target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
return retval;
}

@@ -215,7 +215,7 @@ static int str7x_protect_check(struct flash_bank_s *bank)
{
str7x_flash_bank_t *str7x_info = bank->driver_priv;
target_t *target = bank->target;
int i;
uint32_t retval;

@@ -242,12 +242,12 @@ static int str7x_erase(struct flash_bank_s *bank, int first, int last)
{
str7x_flash_bank_t *str7x_info = bank->driver_priv;
target_t *target = bank->target;
int i;
uint32_t cmd;
uint32_t retval;
uint32_t sectors = 0;
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
@@ -258,33 +258,33 @@ static int str7x_erase(struct flash_bank_s *bank, int first, int last)
{
sectors |= str7x_info->sector_bits[i];
}
LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
/* clear FLASH_ER register */
/* clear FLASH_ER register */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
cmd = FLASH_SER;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
cmd = sectors;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
cmd = FLASH_SER | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)) {
alive_sleep(1);
}
retval = str7x_result(bank);
if (retval)
{
LOG_ERROR("error erasing flash bank, FLASH_ER: 0x%" PRIx32 "", retval);
return ERROR_FLASH_OPERATION_FAILED;
}
for (i = first; i <= last; i++)
bank->sectors[i].is_erased = 1;

@@ -299,13 +299,13 @@ static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last
uint32_t cmd;
uint32_t retval;
uint32_t protect_blocks;
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
protect_blocks = 0xFFFFFFFF;

if (set)
@@ -313,30 +313,30 @@ static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last
for (i = first; i <= last; i++)
protect_blocks &= ~(str7x_info->sector_bits[i]);
}
/* clear FLASH_ER register */
/* clear FLASH_ER register */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);

cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
cmd = protect_blocks;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)) {
alive_sleep(1);
}
retval = str7x_result(bank);
LOG_DEBUG("retval: 0x%8.8" PRIx32 "", retval);
if (retval & FLASH_ERER)
return ERROR_FLASH_SECTOR_NOT_ERASED;
else if (retval & FLASH_WPF)
@@ -355,7 +355,7 @@ static int str7x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_
reg_param_t reg_params[6];
armv4_5_algorithm_t armv4_5_info;
int retval = ERROR_OK;
uint32_t str7x_flash_write_code[] = {
/* write: */
0xe3a04201, /* mov r4, #0x10000000 */
@@ -381,14 +381,14 @@ static int str7x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_
/* exit: */
0xeafffffe, /* b exit */
};
/* flash write code */
if (target_alloc_working_area(target, 4 * 20, &str7x_info->write_algorithm) != ERROR_OK)
{
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, (uint8_t*)str7x_flash_write_code);

/* memory buffer */
@@ -400,63 +400,63 @@ static int str7x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
if (str7x_info->write_algorithm)
target_free_working_area(target, str7x_info->write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
while (count > 0)
{
uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
target_write_buffer(target, source->address, thisrun_count * 8, buffer);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
{
LOG_ERROR("error executing str7x flash write algorithm");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
{
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
buffer += thisrun_count * 8;
address += thisrun_count * 8;
count -= thisrun_count;
}
target_free_working_area(target, source);
target_free_working_area(target, str7x_info->write_algorithm);
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);
destroy_reg_param(&reg_params[2]);
destroy_reg_param(&reg_params[3]);
destroy_reg_param(&reg_params[4]);
destroy_reg_param(&reg_params[5]);
return retval;
}

@@ -472,7 +472,7 @@ static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offs
int retval;
uint32_t check_address = offset;
int i;
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
@@ -484,12 +484,12 @@ static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offs
LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
for (i = 0; i < bank->num_sectors; i++)
{
uint32_t sec_start = bank->sectors[i].offset;
uint32_t sec_end = sec_start + bank->sectors[i].size;
/* check if destination falls within the current sector */
if ((check_address >= sec_start) && (check_address < sec_end))
{
@@ -500,15 +500,15 @@ static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offs
check_address = sec_end;
}
}
if (check_address != offset + count)
return ERROR_FLASH_DST_OUT_OF_BANK;
/* clear FLASH_ER register */
/* clear FLASH_ER register */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);

/* multiple dwords (8-byte) to be programmed? */
if (dwords_remaining > 0)
if (dwords_remaining > 0)
{
/* try using a block write */
if ((retval = str7x_write_block(bank, buffer, offset, dwords_remaining)) != ERROR_OK)
@@ -516,14 +516,14 @@ static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offs
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
/* if block write failed (no sufficient working area),
* we use normal (slow) single dword accesses */
* we use normal (slow) single dword accesses */
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)
{
/* if an error occured, we examine the reason, and quit */
retval = str7x_result(bank);
LOG_ERROR("flash writing failed with error code: 0x%x", retval);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -541,29 +541,29 @@ static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offs
/* command */
cmd = FLASH_DWPG;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
/* address */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
bytes_written += 4;
/* data word 2 */
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
bytes_written += 4;
/* start programming cycle */
cmd = FLASH_DWPG | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
{
alive_sleep(1);
}
retval = str7x_result(bank);
if (retval & FLASH_PGER)
return ERROR_FLASH_OPERATION_FAILED;
else if (retval & FLASH_WPF)
@@ -572,51 +572,51 @@ static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offs
dwords_remaining--;
address += 8;
}
if (bytes_remaining)
{
uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
int i = 0;
while (bytes_remaining > 0)
{
last_dword[i++] = *(buffer + bytes_written);
last_dword[i++] = *(buffer + bytes_written);
bytes_remaining--;
bytes_written++;
}
/* command */
cmd = FLASH_DWPG;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
/* address */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
bytes_written += 4;
/* data word 2 */
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
bytes_written += 4;
/* start programming cycle */
cmd = FLASH_DWPG | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
{
alive_sleep(1);
}
retval = str7x_result(bank);
if (retval & FLASH_PGER)
return ERROR_FLASH_OPERATION_FAILED;
else if (retval & FLASH_WPF)
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
}

@@ -643,35 +643,35 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
flash_bank_t *bank;
target_t *target = NULL;
str7x_flash_bank_t *str7x_info = NULL;
uint32_t flash_cmd;
uint32_t retval;
uint16_t ProtectionLevel = 0;
uint16_t ProtectionRegs;
if (argc < 1)
{
command_print(cmd_ctx, "str7x disable_jtag <bank>");
return ERROR_OK;
return ERROR_OK;
}
bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
if (!bank)
{
command_print(cmd_ctx, "str7x disable_jtag <bank> ok");
return ERROR_OK;
}
str7x_info = bank->driver_priv;
target = bank->target;
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* first we get protection status */
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &retval);

@@ -679,7 +679,7 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
{
ProtectionLevel = 1;
}
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &retval);
ProtectionRegs = ~(retval >> 16);

@@ -688,7 +688,7 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
ProtectionRegs >>= 1;
ProtectionLevel++;
}
if (ProtectionLevel == 0)
{
flash_cmd = FLASH_SPR;
@@ -707,6 +707,6 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
flash_cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
}
return ERROR_OK;
}

+ 10
- 10
src/flash/tms470.c View File

@@ -49,7 +49,7 @@ flash_driver_t tms470_flash = {
.info = tms470_info
};

/* ----------------------------------------------------------------------
/* ----------------------------------------------------------------------
Internal Support, Helpers
---------------------------------------------------------------------- */

@@ -288,10 +288,10 @@ static int tms470_read_part_info(struct flash_bank_s *bank)
bank->chip_width = 32;
bank->bus_width = 32;

LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
part_name,
(int)(silicon_version),
(technology_family ? "1.8v" : "3.3v"),
(technology_family ? "1.8v" : "3.3v"),
(rom_flash ? "rom" : "flash"));

tms470_info->device_ident_reg = device_ident_reg;
@@ -347,7 +347,7 @@ static int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx,

if (keysSet)
{
command_print(cmd_ctx, "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
command_print(cmd_ctx, "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
}
else
@@ -488,7 +488,7 @@ static int tms470_try_flash_keys(target_t * target, const uint32_t * key_set)

if (ERROR_OK == tms470_check_flash_unlocked(target))
{
/*
/*
* There seems to be a side-effect of reading the FMPKEY
* register in that it re-enables the protection. So we
* re-enable it.
@@ -754,7 +754,7 @@ static int tms470_erase_sector(struct flash_bank_s *bank, int sector)
uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
int result = ERROR_OK;

/*
/*
* Set the bit GLBCTRL4 of the GLBCTRL register (in the System
* module) to enable writing to the flash registers }.
*/
@@ -787,8 +787,8 @@ static int tms470_erase_sector(struct flash_bank_s *bank, int sector)
}
bank->sectors[sector].is_protected = 0;

/*
* clear status regiser, sent erase command, kickoff erase
/*
* clear status regiser, sent erase command, kickoff erase
*/
target_write_u16(target, flashAddr, 0x0040);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
@@ -838,7 +838,7 @@ static int tms470_erase_sector(struct flash_bank_s *bank, int sector)
return result;
}

/* ----------------------------------------------------------------------
/* ----------------------------------------------------------------------
Implementation of Flash Driver Interfaces
---------------------------------------------------------------------- */

@@ -1115,7 +1115,7 @@ static int tms470_erase_check(struct flash_bank_s *bank)
target_read_u32(target, 0xFFE88004, &fmbac2);
target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);

/*
/*
* The TI primitives inspect the flash memory by reading one 32-bit
* word at a time. Here we read an entire sector and inspect it in
* an attempt to reduce the JTAG overhead.


+ 1
- 1
src/target/algorithm.h View File

@@ -35,7 +35,7 @@ typedef struct mem_param_s
uint32_t size;
uint8_t *value;
enum param_direction direction;
} mem_param_t;
} mem_param_t;

typedef struct reg_param_s
{


+ 5
- 5
src/target/arm11.c View File

@@ -1888,7 +1888,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (values[i] > arm11_coproc_instruction_limits[i])
{
LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
(long)(i + 2),
(long)(i + 2),
arm11_coproc_instruction_limits[i],
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
@@ -1913,10 +1913,10 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);

LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
(int)(values[0]),
(int)(values[1]),
(int)(values[2]),
(int)(values[3]),
(int)(values[0]),
(int)(values[1]),
(int)(values[2]),
(int)(values[3]),
(int)(values[4]), result, result);
}
else


+ 3
- 3
src/target/arm926ejs.h View File

@@ -39,9 +39,9 @@ typedef struct arm926ejs_common_s
} arm926ejs_common_t;

extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap);
extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
extern int arm926ejs_arch_state(struct target_s *target);
extern int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
extern int arm926ejs_arch_state(struct target_s *target);
extern int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
extern int arm926ejs_soft_reset_halt(struct target_s *target);

#endif /* ARM926EJS_H */

+ 1
- 1
src/target/arm9tdmi.h View File

@@ -59,7 +59,7 @@ extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);

extern int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed);
extern int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in);
extern int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be);
extern int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be);
extern void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]);
extern void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]);



+ 1
- 1
src/target/arm_adi_v5.h View File

@@ -104,7 +104,7 @@ typedef struct swjdp_common_s

} swjdp_common_t;

/* Accessor function for currently selected DAP-AP number */
/* Accessor function for currently selected DAP-AP number */
static inline uint8_t dap_ap_get_select(swjdp_common_t *swjdp)
{
return (uint8_t)(swjdp ->apsel >> 24);


+ 195
- 195
src/target/arm_disassembler.c
File diff suppressed because it is too large
View File


+ 15
- 15
src/target/arm_disassembler.h View File

@@ -25,13 +25,13 @@
enum arm_instruction_type
{
ARM_UNKNOWN_INSTUCTION,
/* Branch instructions */
ARM_B,
ARM_BL,
ARM_BX,
ARM_BLX,
/* Data processing instructions */
ARM_AND,
ARM_EOR,
@@ -49,32 +49,32 @@ enum arm_instruction_type
ARM_MOV,
ARM_BIC,
ARM_MVN,
/* Load/store instructions */
ARM_LDR,
ARM_LDRB,
ARM_LDRT,
ARM_LDRBT,
ARM_LDRH,
ARM_LDRSB,
ARM_LDRSH,
ARM_LDM,

ARM_STR,
ARM_STRB,
ARM_STRT,
ARM_STRBT,
ARM_STRH,
ARM_STM,
/* Status register access instructions */
ARM_MRS,
ARM_MSR,
/* Multiply instructions */
ARM_MUL,
ARM_MLA,
@@ -82,25 +82,25 @@ enum arm_instruction_type
ARM_SMLAL,
ARM_UMULL,
ARM_UMLAL,
/* Miscellaneous instructions */
ARM_CLZ,
/* Exception generating instructions */
ARM_BKPT,
ARM_SWI,
/* Coprocessor instructions */
ARM_CDP,
ARM_LDC,
ARM_STC,
ARM_MCR,
ARM_MRC,
/* Semaphore instructions */
ARM_SWP,
ARM_SWPB,
/* Enhanced DSP extensions */
ARM_MCRR,
ARM_MRRC,
@@ -184,7 +184,7 @@ typedef struct arm_instruction_s
enum arm_instruction_type type;
char text[128];
uint32_t opcode;
union {
arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
arm_data_proc_instr_t data_proc;


+ 1
- 1
src/target/arm_jtag.c View File

@@ -48,7 +48,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, uint32_t new_instr, void *no_veri
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.in_value = NULL;


if (no_verify_capture == NULL)


+ 57
- 57
src/target/arm_simulator.c View File

@@ -35,7 +35,7 @@ uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *c
{
uint32_t return_value = 0;
shift_amount &= 0xff;
if (shift == 0x0) /* LSL */
{
if ((shift_amount > 0) && (shift_amount <= 32))
@@ -118,7 +118,7 @@ uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *c
Rm |= 0x80000000;
*carry = Rm & 0x1;
}
return return_value;
}

@@ -126,14 +126,14 @@ uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_s
{
uint32_t return_value;
int instruction_size;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
instruction_size = 4;
else
instruction_size = 2;
*shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
if (variant == 0) /* 32-bit immediate */
{
return_value = shifter_operand.immediate.immediate;
@@ -141,22 +141,22 @@ uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_s
else if (variant == 1) /* immediate shift */
{
uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32);
/* adjust RM in case the PC is being read */
if (shifter_operand.immediate_shift.Rm == 15)
Rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out);
}
else if (variant == 2) /* register shift */
{
uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32);
uint32_t Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32);
/* adjust RM in case the PC is being read */
if (shifter_operand.register_shift.Rm == 15)
Rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out);
}
else
@@ -164,7 +164,7 @@ uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_s
LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff;
}
return return_value;
}

@@ -251,16 +251,16 @@ int pass_condition(uint32_t cpsr, uint32_t opcode)
case 0xe:
case 0xf:
return 1;
}
LOG_ERROR("BUG: should never get here");
return 0;
}

int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
{
return pass_condition(cpsr, (opcode & 0x0f00) << 20);
return pass_condition(cpsr, (opcode & 0x0f00) << 20);
}

/* simulate a single step (if possible)
@@ -274,11 +274,11 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
arm_instruction_t instruction;
int instruction_size;
int retval = ERROR_OK;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
uint32_t opcode;
/* get current instruction, and identify it */
if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
{
@@ -289,7 +289,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
return retval;
}
instruction_size = 4;
/* check condition code (for all instructions) */
if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
{
@@ -301,14 +301,14 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
}
return ERROR_OK;
}
}
else
{
uint16_t opcode;
if ((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
{
return retval;
@@ -318,7 +318,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
return retval;
}
instruction_size = 2;
/* check condition code (only for branch instructions) */
if ((!thumb_pass_branch_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) &&
(instruction.type == ARM_B))
@@ -331,33 +331,33 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
}
return ERROR_OK;
}
}
/* examine instruction type */

/* branch instructions */
if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
{
uint32_t target;
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
{
target = instruction.info.b_bl_bx_blx.target_address;
}
else
{
target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
if (instruction.info.b_bl_bx_blx.reg_operand == 15)
{
target += 2 * instruction_size;
}
}
if (dry_run_pc)
{
{
*dry_run_pc = target;
return ERROR_OK;
}
@@ -400,7 +400,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
}
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
}
return ERROR_OK;
}
}
@@ -411,7 +411,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
uint32_t Rd, Rn, shifter_operand;
uint8_t C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
uint8_t carry_out;
Rd = 0x0;
/* ARM_MOV and ARM_MVN does not use Rn */
if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
@@ -424,7 +424,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
/* adjust Rn in case the PC is being read */
if (instruction.info.data_proc.Rn == 15)
Rn += 2 * instruction_size;
if (instruction.type == ARM_AND)
Rd = Rn & shifter_operand;
else if (instruction.type == ARM_EOR)
@@ -451,7 +451,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
Rd = ~shifter_operand;
else
LOG_WARNING("unhandled instruction type");
if (dry_run_pc)
{
if (instruction.info.data_proc.Rd == 15)
@@ -463,7 +463,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
{
*dry_run_pc = current_pc + instruction_size;
}
return ERROR_OK;
}
else
@@ -471,7 +471,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
LOG_WARNING("no updating of flags yet");

if (instruction.info.data_proc.Rd == 15)
if (instruction.info.data_proc.Rd == 15)
return ERROR_OK;
}
}
@@ -493,11 +493,11 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
{
uint32_t load_address = 0, modified_address = 0, load_value;
uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
/* adjust Rn in case the PC is being read */
if (instruction.info.load_store.Rn == 15)
Rn += 2 * instruction_size;
if (instruction.info.load_store.offset_mode == 0)
{
if (instruction.info.load_store.U)
@@ -512,9 +512,9 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
uint8_t shift = instruction.info.load_store.offset.reg.shift;
uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
uint8_t carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
offset = arm_shift(shift, Rm, shift_imm, &carry);
if (instruction.info.load_store.U)
modified_address = Rn + offset;
else
@@ -524,7 +524,7 @@ int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
{
LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");