Browse Source

rename jtag_khz as adapter_khz

Globally rename "jtag_khz" as "adapter_khz", and move it out of the "jtag"
command group ...  it needs to be used with non-JTAG transports

Includes a migration aid (in jtag/startup.tcl) so that old user scripts
won't break.  That aid should Sunset in about a year.  (We may want to
update it to include a nag message too.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
tags/v0.5.0-rc1
David Brownell 12 years ago
parent
commit
96f9790279
49 changed files with 111 additions and 96 deletions
  1. +5
    -0
      NEWS
  2. +9
    -9
      doc/openocd.texi
  3. +5
    -5
      src/jtag/core.c
  4. +2
    -2
      src/jtag/drivers/presto.c
  5. +9
    -0
      src/jtag/startup.tcl
  6. +11
    -10
      src/jtag/tcl.c
  7. +1
    -1
      src/svf/svf.c
  8. +1
    -1
      tcl/board/at91eb40a.cfg
  9. +2
    -2
      tcl/board/at91rm9200-dk.cfg
  10. +2
    -2
      tcl/board/at91sam9g20-ek.cfg
  11. +2
    -2
      tcl/board/csb337.cfg
  12. +1
    -1
      tcl/board/dm365evm.cfg
  13. +2
    -2
      tcl/board/ek-lm3s1968.cfg
  14. +1
    -1
      tcl/board/ek-lm3s811.cfg
  15. +1
    -1
      tcl/board/ek-lm3s9b9x.cfg
  16. +1
    -1
      tcl/board/ethernut3.cfg
  17. +3
    -3
      tcl/board/hitex_lpc2929.cfg
  18. +1
    -1
      tcl/board/hitex_str9-comstick.cfg
  19. +1
    -1
      tcl/board/imx27lnst.cfg
  20. +1
    -1
      tcl/board/mini2440.cfg
  21. +3
    -3
      tcl/board/phytec_lpc3250.cfg
  22. +2
    -2
      tcl/board/telo.cfg
  23. +1
    -1
      tcl/board/topas910.cfg
  24. +1
    -1
      tcl/board/topasa900.cfg
  25. +1
    -1
      tcl/board/zy1000.cfg
  26. +1
    -1
      tcl/interface/altera-usb-blaster.cfg
  27. +1
    -1
      tcl/interface/oocdlink.cfg
  28. +1
    -1
      tcl/interface/openrd.cfg
  29. +1
    -1
      tcl/interface/sheevaplug.cfg
  30. +1
    -1
      tcl/interface/usb-jtag.cfg
  31. +2
    -2
      tcl/interface/vsllink.cfg
  32. +3
    -3
      tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
  33. +1
    -1
      tcl/target/c100.cfg
  34. +1
    -1
      tcl/target/c100helper.tcl
  35. +1
    -1
      tcl/target/dsp56321.cfg
  36. +1
    -1
      tcl/target/lm3s6965.cfg
  37. +1
    -1
      tcl/target/lpc2124.cfg
  38. +1
    -1
      tcl/target/lpc2378.cfg
  39. +1
    -1
      tcl/target/mc13224v.cfg
  40. +2
    -2
      tcl/target/mega128.cfg
  41. +2
    -2
      tcl/target/pxa255.cfg
  42. +3
    -3
      tcl/target/readme.txt
  43. +2
    -2
      tcl/target/samsung_s3c2450.cfg
  44. +2
    -2
      tcl/target/stellaris.cfg
  45. +1
    -1
      tcl/target/stm32.cfg
  46. +3
    -3
      tcl/target/str710.cfg
  47. +3
    -3
      tcl/target/str730.cfg
  48. +3
    -3
      tcl/target/str750.cfg
  49. +4
    -4
      tcl/target/telo.cfg

+ 5
- 0
NEWS View File

@@ -5,6 +5,11 @@ and other issues not mentioned here.

JTAG Layer:
New driver for "Bus Pirate"
Rename various commands so they're not JTAG-specific
There are migration procedures for these, but you should
convert your scripts to the new names, since those procedures
will not be around forever.
jtag_khz ... is now adapter_khz

Boundary Scan:



+ 9
- 9
doc/openocd.texi View File

@@ -1516,7 +1516,7 @@ solution just avoids using that instruction with JTAG debuggers.
If both the chip and the board support adaptive clocking,
use the @command{jtag_rclk}
command, in case your board is used with JTAG adapter which
also supports it. Otherwise use @command{jtag_khz}.
also supports it. Otherwise use @command{adapter_khz}.
Set the slow rate at the beginning of the reset sequence,
and the faster rate as soon as the clocks are at full speed.

@@ -2342,7 +2342,7 @@ you may encounter a problem.
@deffn Command {parport_toggling_time} [nanoseconds]
Displays how many nanoseconds the hardware needs to toggle TCK;
the parport driver uses this value to obey the
@command{jtag_khz} configuration.
@command{adapter_khz} configuration.
When the optional @var{nanoseconds} parameter is given,
that setting is changed before displaying the current value.

@@ -2353,7 +2353,7 @@ To measure the toggling time with a logic analyzer or a digital storage
oscilloscope, follow the procedure below:
@example
> parport_toggling_time 1000
> jtag_khz 500
> adapter_khz 500
@end example
This sets the maximum JTAG clock speed of the hardware, but
the actual speed probably deviates from the requested 500 kHz.
@@ -2364,14 +2364,14 @@ Update the setting to match your measurement:
@example
> parport_toggling_time <measured nanoseconds>
@end example
Now the clock speed will be a better match for @command{jtag_khz rate}
Now the clock speed will be a better match for @command{adapter_khz rate}
commands given in OpenOCD scripts and event handlers.

You can do something similar with many digital multimeters, but note
that you'll probably need to run the clock continuously for several
seconds before it decides what clock rate to show. Adjust the
toggling time up or down until the measured clock rate is a good
match for the jtag_khz rate you specified; be conservative.
match for the adapter_khz rate you specified; be conservative.
@end quotation
@end deffn

@@ -2470,10 +2470,10 @@ However, it introduces delays to synchronize clocks; so it
may not be the fastest solution.

@b{NOTE:} Script writers should consider using @command{jtag_rclk}
instead of @command{jtag_khz}, but only for (ARM) cores and boards
instead of @command{adapter_khz}, but only for (ARM) cores and boards
which support adaptive clocking.

@deffn {Command} jtag_khz max_speed_kHz
@deffn {Command} adapter_khz max_speed_kHz
A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
JTAG interfaces usually support a limited number of
speeds. The speed actually used won't be faster
@@ -3881,7 +3881,7 @@ the target clocks are fully set up.)
before @command{reset_init} is called.

This is the most robust place to use @command{jtag_rclk}
or @command{jtag_khz} to switch to a low JTAG clock rate,
or @command{adapter_khz} to switch to a low JTAG clock rate,
when reset disables PLLs needed to use a fast clock.
@ignore
@item @b{reset-wait-pos}
@@ -7290,7 +7290,7 @@ To set the JTAG frequency use the command:

@example
# Example: 1.234MHz
jtag_khz 1234
adapter_khz 1234
@end example




+ 5
- 5
src/jtag/core.c View File

@@ -1556,7 +1556,7 @@ unsigned jtag_get_speed_khz(void)
return speed_khz;
}

static int jtag_khz_to_speed(unsigned khz, int* speed)
static int adapter_khz_to_speed(unsigned khz, int* speed)
{
LOG_DEBUG("convert khz to interface specific speed value");
speed_khz = khz;
@@ -1576,11 +1576,11 @@ static int jtag_khz_to_speed(unsigned khz, int* speed)

static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int* speed)
{
int retval = jtag_khz_to_speed(0, speed);
int retval = adapter_khz_to_speed(0, speed);
if ((ERROR_OK != retval) && fallback_speed_khz)
{
LOG_DEBUG("trying fallback speed...");
retval = jtag_khz_to_speed(fallback_speed_khz, speed);
retval = adapter_khz_to_speed(fallback_speed_khz, speed);
}
return retval;
}
@@ -1598,7 +1598,7 @@ int jtag_config_khz(unsigned khz)
LOG_DEBUG("handle jtag khz");
clock_mode = CLOCK_MODE_KHZ;
int speed = 0;
int retval = jtag_khz_to_speed(khz, &speed);
int retval = adapter_khz_to_speed(khz, &speed);
return (ERROR_OK != retval) ? retval : jtag_set_speed(speed);
}

@@ -1621,7 +1621,7 @@ int jtag_get_speed(void)
speed = jtag_speed;
break;
case CLOCK_MODE_KHZ:
jtag_khz_to_speed(jtag_get_speed_khz(), &speed);
adapter_khz_to_speed(jtag_get_speed_khz(), &speed);
break;
case CLOCK_MODE_RCLK:
jtag_rclk_to_speed(rclk_fallback_speed_khz, &speed);


+ 2
- 2
src/jtag/drivers/presto.c View File

@@ -680,7 +680,7 @@ static struct bitq_interface presto_bitq = {

/* -------------------------------------------------------------------------- */

static int presto_jtag_khz(int khz, int *jtag_speed)
static int presto_adapter_khz(int khz, int *jtag_speed)
{
if (khz < 0)
{
@@ -797,7 +797,7 @@ struct jtag_interface presto_interface = {

.execute_queue = bitq_execute_queue,
.speed = presto_jtag_speed,
.khz = presto_jtag_khz,
.khz = presto_adapter_khz,
.speed_div = presto_jtag_speed_div,
.init = presto_jtag_init,
.quit = presto_jtag_quit,


+ 9
- 0
src/jtag/startup.tcl View File

@@ -75,3 +75,12 @@ add_help_text srst_deasserted "Overridable procedure run when srst deassert is d
proc srst_asserted {} {
puts "Sensed nSRST asserted."
}

# BEGIN MIGRATION AIDS ... these adapter operations originally had
# JTAG-specific names despite the fact that the operations were not
# specific to JTAG.
#
# FIXME phase these aids out after about April 2011
#
proc jtag_khz args { eval adapter_khz $args }
# END MIGRATION AIDS

+ 11
- 10
src/jtag/tcl.c View File

@@ -1351,7 +1351,7 @@ COMMAND_HANDLER(handle_jtag_ntrst_assert_width_command)
return ERROR_OK;
}

COMMAND_HANDLER(handle_jtag_khz_command)
COMMAND_HANDLER(handle_adapter_khz_command)
{
if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1608,6 +1608,16 @@ COMMAND_HANDLER(handle_tms_sequence_command)
}

static const struct command_registration interface_command_handlers[] = {
{
.name = "adapter_khz",
.handler = handle_adapter_khz_command,
.mode = COMMAND_ANY,
.help = "With an argument, change to the specified maximum "
"jtag speed. For JTAG, 0 KHz signifies adaptive "
" clocking. "
"With or without argument, display current setting.",
.usage = "[khz]",
},
{
.name = "interface",
.handler = handle_interface_command,
@@ -1636,15 +1646,6 @@ int interface_register_commands(struct command_context *ctx)
}

static const struct command_registration jtag_command_handlers[] = {
{
.name = "jtag_khz",
.handler = handle_jtag_khz_command,
.mode = COMMAND_ANY,
.help = "With an argument, change to the specified maximum "
"jtag speed. Pass 0 to require adaptive clocking. "
"With or without argument, display current setting.",
.usage = "[khz]",
},
{
.name = "jtag_rclk",
.handler = handle_jtag_rclk_command,


+ 1
- 1
src/svf/svf.c View File

@@ -880,7 +880,7 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str)
// TODO: set jtag speed to
if (svf_para.frequency > 0)
{
command_run_linef(cmd_ctx, "jtag_khz %d", (int)svf_para.frequency / 1000);
command_run_linef(cmd_ctx, "adapter_khz %d", (int)svf_para.frequency / 1000);
LOG_DEBUG("\tfrequency = %f", svf_para.frequency);
}
}


+ 1
- 1
tcl/board/at91eb40a.cfg View File

@@ -65,4 +65,4 @@ $_TARGETNAME configure -event reset-init {
}

# This target is pretty snappy...
jtag_khz 16000
adapter_khz 16000

+ 2
- 2
tcl/board/at91rm9200-dk.cfg View File

@@ -15,7 +15,7 @@ flash_bank cfi 0x10000000 0x00200000 2 2 0
proc at91rm9200_dk_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
jtag_khz 8
adapter_khz 8

mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
@@ -41,7 +41,7 @@ proc at91rm9200_dk_init { } {
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
jtag_khz 40000
adapter_khz 40000
#========================================




+ 2
- 2
tcl/board/at91sam9g20-ek.cfg View File

@@ -77,7 +77,7 @@ proc at91sam9g20_init { } {
# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.

jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
halt # Make sure processor is halted, or error will result in following steps.
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
@@ -112,7 +112,7 @@ proc at91sam9g20_init { } {

# Switch over to adaptive clocking.

jtag_khz 0
adapter_khz 0

# Enable faster DCC downloads.



+ 2
- 2
tcl/board/csb337.cfg View File

@@ -19,7 +19,7 @@ if { [info exists ETM_DRIVER] } {

proc csb337_clk_init { } {
# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
jtag_khz 8
adapter_khz 8

# CKGR_MOR: start main oscillator (3.6864 MHz)
mww 0xfffffc20 0xff01
@@ -37,7 +37,7 @@ proc csb337_clk_init { } {
sleep 20

# CPU is in Normal Mode ... allows faster JTAG clock speed
jtag_khz 40000
adapter_khz 40000
}

proc csb337_nor_init { } {


+ 1
- 1
tcl/board/dm365evm.cfg View File

@@ -103,7 +103,7 @@ proc dm365evm_init {} {
echo "Initialize DM365 EVM board"

# CLKIN = 24 MHz ... can't talk quickly to ARM yet
jtag_khz 1500
adapter_khz 1500

# FIXME -- PLL init



+ 2
- 2
tcl/board/ek-lm3s1968.cfg View File

@@ -4,7 +4,7 @@
# http://www.luminarymicro.com/products/lm3s1968_evaluation_kits.html

# NOTE: to use J-Link instead of the on-board interface,
# you may also need to reduce jtag_khz to be about 1200.
# you may also need to reduce adapter_khz to be about 1200.
# source [find interface/jlink.cfg]

# include the FT2232 interface config for on-board JTAG interface
@@ -14,7 +14,7 @@ source [find interface/luminary.cfg]
source [find target/lm3s1968.cfg]

# jtag speed
jtag_khz 3000
adapter_khz 3000

jtag_nsrst_delay 100



+ 1
- 1
tcl/board/ek-lm3s811.cfg View File

@@ -10,7 +10,7 @@ source [find interface/luminary.cfg]
source [find target/lm3s811.cfg]

# jtag speed
jtag_khz 500
adapter_khz 500

jtag_nsrst_delay 100



+ 1
- 1
tcl/board/ek-lm3s9b9x.cfg View File

@@ -9,7 +9,7 @@ source [find interface/luminary-icdi.cfg]
source [find target/lm3s9b9x.cfg]

# jtag speed
jtag_khz 500
adapter_khz 500

jtag_nsrst_delay 100



+ 1
- 1
tcl/board/ethernut3.cfg View File

@@ -26,7 +26,7 @@ jtag_ntrst_delay 300

arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
jtag_khz 16000
adapter_khz 16000


# Target events


+ 3
- 3
tcl/board/hitex_lpc2929.cfg View File

@@ -7,7 +7,7 @@ jtag_ntrst_delay 1

# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# Adaptive clocking through RTCK is not supported.
jtag_khz 2000
adapter_khz 2000

# Target device: LPC29xx with ETB
# The following variables are used by the LPC2900 script:
@@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-
# Event handlers
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
jtag_khz 2000
adapter_khz 2000
}

# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
@@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init {
mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL

# Increase JTAG speed
jtag_khz 6000
adapter_khz 6000

# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
mww 0xE0001138 0x0000001F # P1.14 = D0


+ 1
- 1
tcl/board/hitex_str9-comstick.cfg View File

@@ -5,7 +5,7 @@
source [find interface/hitex_str9-comstick.cfg]

# set jtag speed
jtag_khz 3000
adapter_khz 3000

jtag_nsrst_delay 100
jtag_ntrst_delay 100


+ 1
- 1
tcl/board/imx27lnst.cfg View File

@@ -8,7 +8,7 @@ proc imx27lnst_init { } {
# This setup puts RAM at 0xA0000000

# reset the board correctly
jtag_khz 500
adapter_khz 500
reset run
reset halt



+ 1
- 1
tcl/board/mini2440.cfg View File

@@ -121,7 +121,7 @@ reset_config trst_and_srst
# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------

jtag_khz 12000
adapter_khz 12000
jtag interface

#-------------------------------------------------------------------------


+ 3
- 3
tcl/board/phytec_lpc3250.cfg View File

@@ -2,7 +2,7 @@ source [find target/lpc3250.cfg]

jtag_nsrst_delay 200
jtag_ntrst_delay 1
jtag_khz 200
adapter_khz 200
reset_config trst_and_srst separate

arm7_9 dcc_downloads enable
@@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init }

$_TARGETNAME configure -event reset-start {
arm7_9 fast_memory_access disable
jtag_khz 200
adapter_khz 200
}

$_TARGETNAME configure -event reset-end {
jtag_khz 6000
adapter_khz 6000
arm7_9 fast_memory_access enable
}



+ 2
- 2
tcl/board/telo.cfg View File

@@ -26,11 +26,11 @@ reset_config trst_and_srst separate
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
jtag_khz 100
adapter_khz 100
# this will setup Telo board
setupTelo
#turn up the JTAG speed
jtag_khz 3000
adapter_khz 3000
puts "JTAG speek now 3MHz"
puts "type helpC100 to get help on C100"
}


+ 1
- 1
tcl/board/topas910.cfg View File

@@ -99,7 +99,7 @@ proc topas910_init { } {
mww 0xf4300004 0x00000000

sleep 10
# jtag_khz NNNN
# adapter_khz NNNN

# remap off in case of IROM boot
mww 0xf0000004 0x00000001


+ 1
- 1
tcl/board/topasa900.cfg View File

@@ -105,7 +105,7 @@ proc topasa900_init { } {
mww 0xf4300004 0x00000000

sleep 10
# jtag_khz NNNN
# adapter_khz NNNN

# remap off in case of IROM boot
mww 0xf0000004 0x00000001


+ 1
- 1
tcl/board/zy1000.cfg View File

@@ -66,7 +66,7 @@ $_TARGETNAME configure -event reset-init {
# other things than flash programming.
$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0

jtag_khz 16000
adapter_khz 16000


proc production_info {} {


+ 1
- 1
tcl/interface/altera-usb-blaster.cfg View File

@@ -8,4 +8,4 @@ interface usb_blaster
# These are already the defaults.
# usb_blaster_vid_pid 0x09FB 0x6001
# usb_blaster_device_desc "USB-Blaster"
jtag_khz 3000
adapter_khz 3000

+ 1
- 1
tcl/interface/oocdlink.cfg View File

@@ -8,5 +8,5 @@ interface ft2232
ft2232_device_desc "OOCDLink"
ft2232_layout oocdlink
ft2232_vid_pid 0x0403 0xbaf8
jtag_khz 5
adapter_khz 5


+ 1
- 1
tcl/interface/openrd.cfg View File

@@ -8,5 +8,5 @@ interface ft2232
ft2232_layout sheevaplug
ft2232_vid_pid 0x0403 0x9e90
ft2232_device_desc "OpenRD JTAGKey FT2232D B"
jtag_khz 3000
adapter_khz 3000


+ 1
- 1
tcl/interface/sheevaplug.cfg View File

@@ -8,5 +8,5 @@ interface ft2232
ft2232_layout sheevaplug
ft2232_vid_pid 0x9e88 0x9e8f
ft2232_device_desc "SheevaPlug JTAGKey FT2232D B"
jtag_khz 2000
adapter_khz 2000


+ 1
- 1
tcl/interface/usb-jtag.cfg View File

@@ -7,5 +7,5 @@
interface usb_blaster
usb_blaster_vid_pid 0x16C0 0x06AD
usb_blaster_device_desc "USB-JTAG-IF"
jtag_khz 3000
adapter_khz 3000


+ 2
- 2
tcl/interface/vsllink.cfg View File

@@ -19,7 +19,7 @@ vsllink_usb_bulkout 0x03
vsllink_usb_interface 1

# vsllink mode, dma or normal
# for low jtag_khz, use normal
# for high jtag_khz, use dma
# for low adapter_khz, use normal
# for high adapter_khz, use dma
#vsllink_mode dma
vsllink_mode normal

+ 3
- 3
tcl/target/at91sam9260_ext_RAM_ext_flash.cfg View File

@@ -1,7 +1,7 @@



jtag_khz 4
adapter_khz 4


######################################
@@ -62,7 +62,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
proc at91sam_init { } {

# at reset chip runs at 32khz
jtag_khz 8
adapter_khz 8
halt
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
@@ -79,7 +79,7 @@ proc at91sam_init { } {
sleep 10 # wait 10 ms

# Now run at anything fast... ie: 10mhz!
jtag_khz 10000 # Increase JTAG Speed to 6 MHz
adapter_khz 10000 # Increase JTAG Speed to 6 MHz
arm7_9 dcc_downloads enable # Enable faster DCC downloads

mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit


+ 1
- 1
tcl/target/c100.cfg View File

@@ -3,7 +3,7 @@
# this script only configures one core (that is used to run Linux)

# assume no PLL lock, start slowly
jtag_khz 100
adapter_khz 100

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME


+ 1
- 1
tcl/target/c100helper.tcl View File

@@ -504,7 +504,7 @@ proc reboot {} {
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
puts "JTAG speed lowered to 100kHz"
jtag_khz 100
adapter_khz 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
puts -nonewline "Wating for watchdog to trigger..."


+ 1
- 1
tcl/target/dsp56321.cfg View File

@@ -22,7 +22,7 @@ if { [info exists CPUTAPID ] } {
}

#jtag speed
jtag_khz 4500
adapter_khz 4500

#has only srst
reset_config srst_only


+ 1
- 1
tcl/target/lm3s6965.cfg View File

@@ -13,7 +13,7 @@ if { [info exists CPUTAPID ] } {
}

# jtag speed
jtag_khz 500
adapter_khz 500

jtag_nsrst_delay 100
jtag_ntrst_delay 100


+ 1
- 1
tcl/target/lpc2124.cfg View File

@@ -27,7 +27,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag_nsrst_delay 100
jtag_ntrst_delay 100

jtag_khz 1000
adapter_khz 1000

#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID


+ 1
- 1
tcl/target/lpc2378.cfg View File

@@ -47,4 +47,4 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum

# 4MHz / 6 = 666kHz, so use 500
jtag_khz 500
adapter_khz 500

+ 1
- 1
tcl/target/mc13224v.cfg View File

@@ -36,7 +36,7 @@ jtag_ntrst_delay 200

# rclk hasn't been working well. This maybe the mc13224v or something else.
#jtag_rclk 2000
jtag_khz 2000
adapter_khz 2000

######################
# Target configuration


+ 2
- 2
tcl/target/mega128.cfg View File

@@ -4,7 +4,7 @@
set _ENDIAN little

# jtag speed
jtag_khz 4500
adapter_khz 4500

reset_config srst_only
jtag_nsrst_delay 100
@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME

#to use it, script will be like:
#init
#jtag_khz 4500
#adapter_khz 4500
#reset init
#verify_ircapture disable
#


+ 2
- 2
tcl/target/pxa255.cfg View File

@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
jtag_khz 300
$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
adapter_khz 300
$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }

# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active


+ 3
- 3
tcl/target/readme.txt View File

@@ -26,12 +26,12 @@ assumed that all write-protect mechanisms should be disabled.
flash write_image [file] <parameters>
verify_image [file] <parameters>

4. jtag_khz sets the maximum speed (or alternatively RCLK). If invoked
4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
multiple times only the last setting is used.

interface/xxx.cfg files are always executed *before* target/xxx.cfg
files, so any jtag_khz in interface/xxx.cfg will be overridden by
target/xxx.cfg. jtag_khz in interface/xxx.cfg would then, effectively,
files, so any adapter_khz in interface/xxx.cfg will be overridden by
target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
set the default JTAG speed.

Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,


+ 2
- 2
tcl/target/samsung_s3c2450.cfg View File

@@ -7,11 +7,11 @@
#
# RCLK?
#
# jtag_khz 0
# adapter_khz 0
#
# Really low clock during reset?
#
# jtag_khz 1
# adapter_khz 1

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME


+ 2
- 2
tcl/target/stellaris.cfg View File

@@ -41,8 +41,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
# NOTE: this may be increased by a reset-init handler, after it
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
jtag_khz 500
$_TARGETNAME configure -event reset-start {jtag_khz 500}
adapter_khz 500
$_TARGETNAME configure -event reset-start {adapter_khz 500}

# flash configuration ... autodetects sizes, autoprobed
flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME


+ 1
- 1
tcl/target/stm32.cfg View File

@@ -21,7 +21,7 @@ if { [info exists WORKAREASIZE] } {
}

# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
jtag_khz 1000
adapter_khz 1000

jtag_nsrst_delay 100
jtag_ntrst_delay 100


+ 3
- 3
tcl/target/str710.cfg View File

@@ -1,5 +1,5 @@
#start slow, speed up after reset
jtag_khz 10
adapter_khz 10

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi

$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
jtag_khz 6000
adapter_khz 6000

# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial


+ 3
- 3
tcl/target/str730.cfg View File

@@ -1,6 +1,6 @@
#STR730 CPU

jtag_khz 3000
adapter_khz 3000

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -33,9 +33,9 @@ jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi

$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
jtag_khz 3000
adapter_khz 3000

# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial


+ 3
- 3
tcl/target/str750.cfg View File

@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
}

# jtag speed
jtag_khz 10
adapter_khz 10

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
@@ -35,9 +35,9 @@ jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi

$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
jtag_khz 3000
adapter_khz 3000

# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial


+ 4
- 4
tcl/target/telo.cfg View File

@@ -26,12 +26,12 @@ reset_config trst_and_srst separate
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
jtag_khz 100
adapter_khz 100
# this will setup Telo board
setupTelo
#turn up the JTAG speed
jtag_khz 3000
puts "JTAG speek now 3MHz"
adapter_khz 3000
puts "JTAG speed now 3MHz"
puts "type helpC100 to get help on C100"
}

@@ -58,4 +58,4 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME

# writing data to memory does not work without this
memwrite burst disable
memwrite burst disable

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