This patch helps fix MIPS big endian (elf32-tradbigmips) targets.
If "-endian big" is not set in target create, the endianess defaults to
little. mw and md commands will still work, but binary file loads will
have the incorrect word order loaded into memory.
The EJTAG processor access data register (PrAcc) is little endian
regardless of the CPU endianness; it is always loaded LSB first. This
is confirmed by the fact that mips_ejtag_drscan_32() uses buf_set_u32()
to load the scan field; buf_set_u32() is a little-endian formatter. For
big endian targets, data buffers have to be modified so the LSB of each
u32 or u16 is at the lower (first) memory location. If the drscan
out_value word order is set using buf_set_u32() then it makes sense to
also fixup the in_value with buf_get_u32(); a symmetry argument. This
has no affect on little endian hosts.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2219 b42882b7-edfa-0310-969c-e2dbd0fdcd60
this fn has something to do with the queue, which it does not as such.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2050 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bring the mips step/resume interrupt handling inline with the
rest of openocd.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1850 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- all the register now can be written to, including the special CP0 regs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ejtag_info->ejtag_ctrl variable. It was being overwritten by the value read back from the EJTAG CONTROL register. Because of the way this register works you do not want to use the value returned to write the register, you always want to write the bits explicitly.
The second patch just reduces the DMA retries to 0 in anticipation of removing the retry code altogether.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1049 b42882b7-edfa-0310-969c-e2dbd0fdcd60
duane
zwelch
oharboe
kc8apf
mifi
ntfreak