Browse Source

Remove annoying end-of-line whitespace from tcl/* files

git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
tags/v0.3.0-rc0
dbrownell 12 years ago
parent
commit
71af49ca7f
85 changed files with 682 additions and 683 deletions
  1. +1
    -1
      tcl/bitsbytes.tcl
  2. +1
    -1
      tcl/board/arm_evaluator7t.cfg
  3. +5
    -5
      tcl/board/at91rm9200-dk.cfg
  4. +2
    -2
      tcl/board/at91sam9g20-ek.cfg
  5. +2
    -2
      tcl/board/atmel_at91sam9260-ek.cfg
  6. +1
    -1
      tcl/board/crossbow_tech_imote2.cfg
  7. +6
    -6
      tcl/board/csb732.cfg
  8. +14
    -14
      tcl/board/digi_connectcore_wi-9c.cfg
  9. +12
    -12
      tcl/board/eir.cfg
  10. +8
    -8
      tcl/board/hitex_str9-comstick.cfg
  11. +23
    -23
      tcl/board/imx27ads.cfg
  12. +12
    -12
      tcl/board/imx27lnst.cfg
  13. +1
    -1
      tcl/board/imx31pdk.cfg
  14. +67
    -67
      tcl/board/mini2440.cfg
  15. +1
    -1
      tcl/board/propox_mmnet1001.cfg
  16. +1
    -1
      tcl/board/pxa255_sst.cfg
  17. +1
    -1
      tcl/board/sheevaplug.cfg
  18. +10
    -10
      tcl/board/str910-eval.cfg
  19. +4
    -4
      tcl/board/telo.cfg
  20. +5
    -5
      tcl/board/unknown_at91sam9260.cfg
  21. +3
    -3
      tcl/board/x300t.cfg
  22. +15
    -15
      tcl/board/zy1000.cfg
  23. +3
    -3
      tcl/chip/atmel/at91/aic.tcl
  24. +2
    -2
      tcl/chip/atmel/at91/rtt.tcl
  25. +5
    -5
      tcl/chip/atmel/at91/usarts.tcl
  26. +9
    -9
      tcl/chip/st/stm32/stm32_rcc.tcl
  27. +8
    -8
      tcl/memory.tcl
  28. +2
    -2
      tcl/mmr_helpers.tcl
  29. +0
    -1
      tcl/readable.tcl
  30. +10
    -10
      tcl/target/aduc702x.cfg
  31. +3
    -3
      tcl/target/ar71xx.cfg
  32. +10
    -10
      tcl/target/at91eb40a.cfg
  33. +6
    -6
      tcl/target/at91r40008.cfg
  34. +7
    -7
      tcl/target/at91rm9200.cfg
  35. +6
    -6
      tcl/target/at91sam3uXX.cfg
  36. +14
    -14
      tcl/target/at91sam7sx.cfg
  37. +6
    -6
      tcl/target/at91sam9260.cfg
  38. +7
    -7
      tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
  39. +6
    -6
      tcl/target/c100.cfg
  40. +41
    -41
      tcl/target/c100config.tcl
  41. +56
    -56
      tcl/target/c100helper.tcl
  42. +37
    -37
      tcl/target/c100regs.tcl
  43. +6
    -6
      tcl/target/cs351x.cfg
  44. +6
    -6
      tcl/target/epc9301.cfg
  45. +6
    -6
      tcl/target/feroceon.cfg
  46. +7
    -7
      tcl/target/imx21.cfg
  47. +7
    -7
      tcl/target/imx27.cfg
  48. +10
    -10
      tcl/target/imx31.cfg
  49. +8
    -8
      tcl/target/imx35.cfg
  50. +8
    -8
      tcl/target/is5114.cfg
  51. +6
    -6
      tcl/target/ixp42x.cfg
  52. +3
    -3
      tcl/target/lm3s1968.cfg
  53. +3
    -3
      tcl/target/lm3s3748.cfg
  54. +3
    -3
      tcl/target/lm3s6965.cfg
  55. +3
    -3
      tcl/target/lm3s811.cfg
  56. +3
    -3
      tcl/target/lm3s9b9x.cfg
  57. +2
    -2
      tcl/target/lpc2103.cfg
  58. +6
    -6
      tcl/target/lpc2129.cfg
  59. +3
    -3
      tcl/target/lpc2148.cfg
  60. +6
    -6
      tcl/target/lpc2294.cfg
  61. +6
    -6
      tcl/target/netx500.cfg
  62. +3
    -3
      tcl/target/omap3530.cfg
  63. +6
    -6
      tcl/target/omap5912.cfg
  64. +6
    -6
      tcl/target/pic32mx.cfg
  65. +6
    -6
      tcl/target/pxa255.cfg
  66. +6
    -6
      tcl/target/pxa270.cfg
  67. +7
    -7
      tcl/target/readme.txt
  68. +7
    -7
      tcl/target/sam7se512.cfg
  69. +13
    -13
      tcl/target/sam7x256.cfg
  70. +9
    -9
      tcl/target/samsung_s3c2410.cfg
  71. +6
    -6
      tcl/target/samsung_s3c2440.cfg
  72. +2
    -2
      tcl/target/samsung_s3c2450.cfg
  73. +7
    -7
      tcl/target/samsung_s3c4510.cfg
  74. +6
    -6
      tcl/target/samsung_s3c6410.cfg
  75. +7
    -7
      tcl/target/sharp_lh79532.cfg
  76. +7
    -7
      tcl/target/stm32.cfg
  77. +9
    -9
      tcl/target/str710.cfg
  78. +9
    -9
      tcl/target/str730.cfg
  79. +9
    -9
      tcl/target/str750.cfg
  80. +8
    -8
      tcl/target/str912.cfg
  81. +1
    -1
      tcl/target/telo.cfg
  82. +2
    -2
      tcl/target/test_reset_syntax_error.cfg
  83. +1
    -1
      tcl/target/test_syntax_error.cfg
  84. +7
    -7
      tcl/target/xba_revA3.cfg
  85. +3
    -3
      tcl/test/syntax1.cfg

+ 1
- 1
tcl/bitsbytes.tcl View File

@@ -22,7 +22,7 @@ for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
# Create M bytes values
# __1M ... to __2048K
for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
set vn [format "__%dM" $x]
set vn [format "__%dM" $x]
global $vn
set $vn [expr (1024 * 1024 * $x)]
}


+ 1
- 1
tcl/board/arm_evaluator7t.cfg View File

@@ -2,7 +2,7 @@

source [find target/samsung_s3c4510.cfg]

#
#
# FIXME:
# Add (A) sdram configuration
# Add (B) flash cfi programing configuration


+ 5
- 5
tcl/board/at91rm9200-dk.cfg View File

@@ -16,7 +16,7 @@ proc at91rm9200_dk_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
jtag_khz 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
mww 0xfffffc04 0xfffffffe
@@ -37,14 +37,14 @@ proc at91rm9200_dk_init { } {
mww 0xfffffc30 0x202
## Sleep some - (go read)
sleep 100
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
jtag_khz 40000
#========================================
## set memc for all memories
mww 0xffffff60 0x02
## program smc controller
@@ -55,7 +55,7 @@ proc at91rm9200_dk_init { } {
mww 0xffffff80 0x02
## touch sdram chip to make it work
mww 0x20000000 0
## sdram controller mode register
## sdram controller mode register
mww 0xffffff90 0x04
mww 0x20000000 0
mww 0x20000000 0


+ 2
- 2
tcl/board/at91sam9g20-ek.cfg View File

@@ -62,7 +62,7 @@ proc read_register {register} {
}

proc at91sam9g20_init { } {
# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
# a number of steps that must be carefully performed. The process outline below follows the
# recommended procedure outlined in the AT91SAM9G20 technical manual.
@@ -94,7 +94,7 @@ proc at91sam9g20_init { } {

mww 0xfffffc30 0x00000101
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.



+ 2
- 2
tcl/board/atmel_at91sam9260-ek.cfg View File

@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
arm926ejs mww_phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog

@@ -48,7 +48,7 @@ $_TARGETNAME configure -event reset-init {

mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory

mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)


+ 1
- 1
tcl/board/crossbow_tech_imote2.cfg View File

@@ -4,7 +4,7 @@ set CHIPNAME imote2
source [find target/pxa270.cfg]

# longer-than-normal reset delay
jtag_nsrst_delay 800
jtag_nsrst_delay 800

reset_config trst_and_srst separate



+ 6
- 6
tcl/board/csb732.cfg View File

@@ -11,7 +11,7 @@ $_TARGETNAME configure -event reset-init { csb732_init }

# Bare-bones initialization of core clocks and SDRAM
proc csb732_init { } {
# Disable fast writing only for init
memwrite burst disable

@@ -29,17 +29,17 @@ proc csb732_init { } {

# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
mww 0x53F8001C 0xB2C01
set ESDMISC 0xB8001010
set ESDCFG0 0xB8001004
set ESDCTL0 0xB8001000

# Enable DDR
mww $ESDMISC 0x4
# Timing
mww $ESDCFG0 0x007fff3f

@@ -51,7 +51,7 @@ proc csb732_init { } {

# Enable CS) auto-refresh
mww $ESDCTL0 0xA2120080
# Refresh twice (dummy writes)
mww 0x80000000 0
mww 0x80000000 0
@@ -59,7 +59,7 @@ proc csb732_init { } {
# Enable CS0 load mode register
mww $ESDCTL0 0xB2120080

# Dummy writes
# Dummy writes
mwb 0x80000033 0x01
mwb 0x81000000 0x01



+ 14
- 14
tcl/board/digi_connectcore_wi-9c.cfg View File

@@ -4,15 +4,15 @@

reset_config trst_and_srst

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME ns9360
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# This config file was defaulting to big endian..
set _ENDIAN big
}
@@ -46,17 +46,17 @@ $_TARGETNAME configure -event reset-init {
mww 0x90600104 0x33313333
mww 0xA0700000 0x00000001 # Enable the memory controller.
mww 0xA0700024 0x00000006 # Set the refresh counter 6
mww 0xA0700028 0x00000001 #
mww 0xA0700028 0x00000001 #
mww 0xA0700030 0x00000001 # Set the precharge period
mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
mww 0xA070003C 0x00000001 # tAPR
mww 0xA0700040 0x00000005 # tDAL
mww 0xA0700044 0x00000001 # tWR
mww 0xA0700048 0x00000006 # tRC 32 clock cycles
mww 0xA0700048 0x00000006 # tRC 32 clock cycles
mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
mww 0xA0700054 0x00000001 # tRRD
mww 0xA0700058 0x00000001 # tMRD
mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
@@ -79,11 +79,11 @@ $_TARGETNAME configure -event reset-init {
mww 0xA0900000 0x00000002
mww 0xA0900000 0x00000002
#
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
#
mww 0xA0700024 0x00000030 # Set the refresh counter to 30
mww 0xA0700020 0x00000083 # Issue SDRAM MODE command


+ 12
- 12
tcl/board/eir.cfg View File

@@ -4,7 +4,7 @@
source [find target/sam7se512.cfg]

$_TARGETNAME configure -event reset-init {
# WDT_MR, disable watchdog
# WDT_MR, disable watchdog
mww 0xFFFFFD44 0x00008000

# RSTC_MR, enable user reset
@@ -51,31 +51,31 @@ $_TARGETNAME configure -event reset-init {

# Issue 16 bit SDRAM command: NOP
mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000

# Issue 16 bit SDRAM command: Precharge all
mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000

# Issue 8 auto-refresh cycles
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000

# Issue 16 bit SDRAM command: Set mode register
# Issue 16 bit SDRAM command: Set mode register
mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
mww 0x20000014 0xcafedede



+ 8
- 8
tcl/board/hitex_str9-comstick.cfg View File

@@ -14,15 +14,15 @@ reset_config trst_and_srst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME str912
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

@@ -56,10 +56,10 @@ target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
#jtag_rclk 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
mww 0x5C002034 0x0191
mww 0x5C002034 0x0191

str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off


+ 23
- 23
tcl/board/imx27ads.cfg View File

@@ -24,52 +24,52 @@ proc imx27ads_init { } {
# ========================================
# Configure DDR on CSD0 -- initial reset
# ========================================
mww 0xD8001010 0x00000008
mww 0xD8001010 0x00000008

# ========================================
# Configure PSRAM on CS5
# Configure PSRAM on CS5
# ========================================
mww 0xd8002050 0x0000dcf6
mww 0xd8002054 0x444a4541
mww 0xd8002058 0x44443302
mww 0xd8002054 0x444a4541
mww 0xd8002058 0x44443302

# ========================================
# Configure16 bit NorFlash on CS0
# ========================================
mww 0xd8002000 0x0000CC03
mww 0xd8002004 0xa0330D01
mww 0xd8002008 0x00220800
mww 0xd8002000 0x0000CC03
mww 0xd8002004 0xa0330D01
mww 0xd8002008 0x00220800

# ========================================
# Configure CPLD on CS4
# Configure CPLD on CS4
# ========================================
mww 0xd8002040 0x0000DCF6
mww 0xd8002044 0x444A4541
mww 0xd8002048 0x44443302
mww 0xd8002040 0x0000DCF6
mww 0xd8002044 0x444A4541
mww 0xd8002048 0x44443302

# ========================================
# Configure DDR on CSD0 -- wait 5000 cycle
# Configure DDR on CSD0 -- wait 5000 cycle
# ========================================
mww 0x10027828 0x55555555
mww 0x10027830 0x55555555
mww 0x10027834 0x55555555
mww 0x10027838 0x00005005
mww 0x1002783C 0x15555555
mww 0x10027828 0x55555555
mww 0x10027830 0x55555555
mww 0x10027834 0x55555555
mww 0x10027838 0x00005005
mww 0x1002783C 0x15555555

mww 0xD8001010 0x00000004
mww 0xD8001010 0x00000004

mww 0xD8001004 0x00795729
mww 0xD8001004 0x00795729

mww 0xD8001000 0x92200000
mww 0xD8001000 0x92200000
mww 0xA0000F00 0x0

mww 0xD8001000 0xA2200000
mww 0xD8001000 0xA2200000
mww 0xA0000F00 0x0
mww 0xA0000F00 0x0

mww 0xD8001000 0xB2200000
mww 0xD8001000 0xB2200000
mwb 0xA0000033 0xFF
mwb 0xA1000000 0xAA

mww 0xD8001000 0x82228085
mww 0xD8001000 0x82228085
}

+ 12
- 12
tcl/board/imx27lnst.cfg View File

@@ -22,38 +22,38 @@ proc imx27lnst_init { } {
# ========================================
# Configure DDR on CSD0 -- initial reset
# ========================================
mww 0xD8001010 0x00000008
mww 0xD8001010 0x00000008

sleep 100

# ========================================
# Configure DDR on CSD0 -- wait 5000 cycle
# Configure DDR on CSD0 -- wait 5000 cycle
# ========================================
mww 0x10027828 0x55555555
mww 0x10027830 0x55555555
mww 0x10027834 0x55555555
mww 0x10027838 0x00005005
mww 0x1002783C 0x15555555
mww 0x10027828 0x55555555
mww 0x10027830 0x55555555
mww 0x10027834 0x55555555
mww 0x10027838 0x00005005
mww 0x1002783C 0x15555555

mww 0xD8001010 0x00000004
mww 0xD8001010 0x00000004

mww 0xD8001004 0x00795729
mww 0xD8001004 0x00795729

#mww 0xD8001000 0x92200000
mww 0xD8001000 0x91120000
mww 0xA0000F00 0x0

#mww 0xD8001000 0xA2200000
#mww 0xD8001000 0xA2200000
mww 0xD8001000 0xA1120000
mww 0xA0000F00 0x0
mww 0xA0000F00 0x0

#mww 0xD8001000 0xB2200000
#mww 0xD8001000 0xB2200000
mww 0xD8001000 0xB1120000
mwb 0xA0000033 0xFF
mwb 0xA1000000 0xAA

#mww 0xD8001000 0x82228085
#mww 0xD8001000 0x82228085
mww 0xD8001000 0x81128080

}

+ 1
- 1
tcl/board/imx31pdk.cfg View File

@@ -25,7 +25,7 @@ proc imx31pdk_init { } {
mww 0x53F80010 0x00271C1B

# ========================================
# Configure CPLD on CS5
# Configure CPLD on CS5
# ========================================
mww 0xb8002050 0x0000DCF6
mww 0xb8002054 0x444A4541


+ 67
- 67
tcl/board/mini2440.cfg View File

@@ -1,7 +1,7 @@
#-------------------------------------------------------------------------
# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
# 64 MB NAND (Samsung K9D1208V0M)
# 64 MB NAND (Samsung K9D1208V0M)
# B Findlay 08/09
#
# ----------- Important notes to help you on your way ----------
@@ -9,9 +9,9 @@
# NOR/NAND Boot Switch - I have not read the vivi source, but from
# what I could tell from reading the registers it appears that vivi
# loads itself into DRAM and then flips NFCONT (0x4E000004) bits
# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
# FLASH at the bottom 64MB of memory. This essentially takes the
# NOR Flash out of the circuit so you can't trash it.
# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
# FLASH at the bottom 64MB of memory. This essentially takes the
# NOR Flash out of the circuit so you can't trash it.
#
# I adapted the samsung_s3c2440.cfg file which is why I did not
# include "source [find target/samsung_s3c2440.cfg]". I believe
@@ -22,9 +22,9 @@
# JTAG ADAPTER SPECIFIC
# IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
# FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
# necessary to FORCE setting the clock. Normally this should be configured
# in the openocd.cfg file, but was placed here as it can be a tough
# in the openocd.cfg file, but was placed here as it can be a tough
# problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified
# the openOCD driver jlink.c and posted it here. It may eventually end
# up changed in openOCD, but its a hack in the driver and really should
@@ -42,21 +42,21 @@
# But it should get you way ahead of the game from where I started.
# If you find problems (and fixes) please post them to
# openocd-development@lists.berlios.de and join the developers and
# check in fixes to this and anything else you find. I do not
# provide support, but if you ask really nice and I see anything
# check in fixes to this and anything else you find. I do not
# provide support, but if you ask really nice and I see anything
# obvious I will tell you.. mostly just dig, fix, and submit to openocd.
#
#
# best! brfindla@yahoo.com Nashua, NH USA
#
# Recommended resources:
# - first two are the best Mini2440 resources anywhere
# - maintained by buserror... thanks guy!
#
# http://bliterness.blogspot.com/
# http://bliterness.blogspot.com/
# http://code.google.com/p/mini2440/
#
# others....
#
#
# http://forum.sparkfun.com/viewforum.php?f=18
# http://labs.kernelconcepts.de/Publications/Micro24401/
# http://www.friendlyarm.net/home
@@ -75,19 +75,19 @@
# Target configuration for the Samsung 2440 system on chip
# Tested on a S3C2440 Evaluation board by keesj
# Processor : ARM920Tid(wb) rev 0 (v4l)
# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
# (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
#-------------------------------------------------------------------------

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME s3c2440
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a bigendian
set _ENDIAN little
}
@@ -108,16 +108,16 @@ $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-

#reset configuration
jtag_nsrst_delay 100
jtag_ntrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst

#-------------------------------------------------------------------------
# JTAG ADAPTER SPECIFIC
# IMPORTANT! See README at top of this file.
# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------

jtag_khz 12000
jtag interface
jtag_khz 12000
jtag interface

#-------------------------------------------------------------------------
# GDB Setup
@@ -125,23 +125,23 @@ reset_config trst_and_srst

gdb_port 3333
gdb_detach resume
gdb_breakpoint_override hard
gdb_breakpoint_override hard
gdb_memory_map enable
gdb_flash_program enable
gdb_flash_program enable

#------------------------------------------------
# ARM SPECIFIC
#------------------------------------------------

targets
targets
# arm7_9 dcc_downloads enable
# arm7_9 fast_memory_access enable
nand device s3c2440 0
nand device s3c2440 0

jtag_nsrst_delay 100
jtag_ntrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
init

@@ -180,59 +180,59 @@ proc init_2440 { } {
# OM2 OM3 pulled to ground so main clock and
# usb clock are off 12mHz xtal
#-----------------------------------------------
arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg
arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
# BWSCON configures all banks, NAND, NOR, DRAM
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ?
arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM
arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM
arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM
arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM
arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM
arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
arm920t mww_phys 0x56000000 0x007FFFFF # GPACON
arm920t mww_phys 0x56000010 0x00295559 # GPBCON
arm920t mww_phys 0x56000010 0x00295559 # GPBCON
arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT
arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON
arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT
arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON
arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP
arm920t mww_phys 0x56000024 0x00000020 # GPCDAT
arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON
arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP
arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON
arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP
arm920t mww_phys 0x56000050 0x00001555 # GPFCON
arm920t mww_phys 0x56000058 0x0000007F # GPFUP
arm920t mww_phys 0x56000054 0x00000000 # GPFDAT
arm920t mww_phys 0x56000060 0x00150114 # GPGCON
arm920t mww_phys 0x56000068 0x0000007F # GPGUP
arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON
arm920t mww_phys 0x56000078 0x000003FF # GPGUP
}
arm920t mww_phys 0x56000024 0x00000020 # GPCDAT
arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON
arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP
arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON
arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP
arm920t mww_phys 0x56000050 0x00001555 # GPFCON
arm920t mww_phys 0x56000058 0x0000007F # GPFUP
arm920t mww_phys 0x56000054 0x00000000 # GPFDAT
arm920t mww_phys 0x56000060 0x00150114 # GPGCON
arm920t mww_phys 0x56000068 0x0000007F # GPGUP
arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON
arm920t mww_phys 0x56000078 0x000003FF # GPGUP
}



@@ -243,7 +243,7 @@ proc flash_config { } {
#-----------------------------------------

halt
#flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
nand probe 0
nand list
@@ -275,8 +275,8 @@ proc load_uboot { } {
echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---"
echo "---- Also this: ---"
echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
echo "----------------------------------------------------------"
echo "----------------------------------------------------------"
init_2440
echo "Loading /tftpboot/u-boot-nand512.bin"
load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin


+ 1
- 1
tcl/board/propox_mmnet1001.cfg View File

@@ -9,7 +9,7 @@ $_TARGETNAME configure -event reset-init {at91sam_init}


proc at91sam_init { } {
# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
jtag_rclk 4



+ 1
- 1
tcl/board/pxa255_sst.cfg View File

@@ -1,7 +1,7 @@
# A PXA255 test board with SST 39LF400A flash
#
# At reset the memory map is as follows. Note that
# the memory map changes later on as the application
# the memory map changes later on as the application
# starts...
#
# RAM at 0x4000000


+ 1
- 1
tcl/board/sheevaplug.cfg View File

@@ -1,4 +1,4 @@
# Marvell SheevaPlug
# Marvell SheevaPlug

source [find interface/sheevaplug.cfg]
source [find target/feroceon.cfg]


+ 10
- 10
tcl/board/str910-eval.cfg View File

@@ -1,17 +1,17 @@
# str910-eval eval board
#
# Need reset scripts
#
# Need reset scripts
reset_config trst_and_srst

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME str912
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

@@ -44,10 +44,10 @@ $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -wo
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
#jtag_rclk 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
mww 0x5C002034 0x0191
mww 0x5C002034 0x0191

str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off


+ 4
- 4
tcl/board/telo.cfg View File

@@ -8,7 +8,7 @@ source [find target/c100helper.tcl]


# Telo board & C100 support trst and srst
# however openocd does not support
# however openocd does not support
# 1. setting srst reset pulse width
# 2. setting delay between srst pulse and JTAG access
# This really makes the srst useless for now.
@@ -23,7 +23,7 @@ $_TARGETNAME configure -event reset-init {
# setup GPIO used as control signals for C100
setupGPIO
# This will allow acces to lower 8MB or NOR
lowGPIO5
lowGPIO5
# setup NOR size,timing,etc.
setupNOR
# setup internals + PLL + DDR2
@@ -38,10 +38,10 @@ $_TARGETNAME configure -event reset-deassert-post {
# Force target into ARM state.
# soft_reset_halt # not implemented on ARM11
puts "Detected SRSRT asserted on C100.CPU"
}

proc power_restore {} { puts "Sensed power restore. No action." }
proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }




+ 5
- 5
tcl/board/unknown_at91sam9260.cfg View File

@@ -1,4 +1,4 @@
# Thanks to Pieter Conradie for this script!
# Thanks to Pieter Conradie for this script!
#
# Unknown vendor board contains:
#
@@ -15,12 +15,12 @@ source [find target/at91sam9260.cfg]
$_TARGETNAME configure -event reset-start {
# At reset CPU runs at 22 to 42 kHz.
# JTAG Frequency must be 6 times slower.
jtag_rclk 3
jtag_rclk 3
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
arm926ejs mww_phys 0xfffffd08 0xa5000501
}

$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
@@ -37,7 +37,7 @@ $_TARGETNAME configure -event reset-init {
sleep 10 # wait 10 ms

# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
jtag_rclk 6000

arm7_9 dcc_downloads enable # Enable faster DCC downloads

@@ -51,7 +51,7 @@ $_TARGETNAME configure -event reset-init {
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups
mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
# VDDIOMSEL set for +3V3 memory
# Disable D0..D15 pull-ups


+ 3
- 3
tcl/board/x300t.cfg View File

@@ -18,13 +18,13 @@ proc x300t_init { } {
mww 0xa0030000 0xE34111BA
mww 0xa003fffc 0xa4444
mww 0xa003fffc 0
# remap boot vector in CPU local RAM
mww 0xa006f000 0x60000
# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
mww 0x0006f010 0x48000000
# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
mww 0x00061ff0 0x48000000
}

+ 15
- 15
tcl/board/zy1000.cfg View File

@@ -10,19 +10,19 @@
reset_config srst_only srst_pulls_trst


if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME zy1000
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

#jtag scan chain
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
@@ -39,7 +39,7 @@ arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable

flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
$_TARGETNAME configure -event reset-init {
$_TARGETNAME configure -event reset-init {
# Set up chip selects & timings
mww 0xFFE00000 0x0100273D
mww 0xFFE00004 0x08002125
@@ -51,12 +51,12 @@ $_TARGETNAME configure -event reset-init {
mww 0xFFE0001c 0x70000000
mww 0xFFE00020 0x00000001
mww 0xFFE00024 0x00000000
# remap
mww 0xFFFFF124 0xFFFFFFFF
# remap
mww 0xFFFFF124 0xFFFFFFFF
mww 0xffff0010 0x100
mww 0xffff0034 0x100
#disable 16x5x UART interrupts
mww 0x08020004 0
}
@@ -75,7 +75,7 @@ proc production_info {} {
# There is no return value from this procedure. If it is
# successful it does not throw an exception
#
# Progress messages are output via puts
# Progress messages are output via puts
proc production {firmwarefile serialnumber} {
if {[string length $serialnumber]!=12} {
puts "Invalid serial number"
@@ -92,11 +92,11 @@ proc production {firmwarefile serialnumber} {
verify_image $firmwarefile 0x1000000 bin

# Big endian... weee!!!!
puts "Setting MAC number to $serialnumber"
puts "Setting MAC number to $serialnumber"
flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
puts "Production successful"
}
}


proc production_test {} {


+ 3
- 3
tcl/chip/atmel/at91/aic.tcl View File

@@ -85,12 +85,12 @@ proc show_AIC { } {
incr x
puts [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
incr x
}
}

foreach REG {
AIC_IVR AIC_FVR AIC_ISR
AIC_IVR AIC_FVR AIC_ISR
AIC_IPR AIC_IMR AIC_CISR AIC_IECR AIC_IDCR
AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR
AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR
AIC_FFER AIC_FFDR AIC_FFSR } {
if [catch { show_mmr32_reg $REG } msg ] {
error $msg


+ 2
- 2
tcl/chip/atmel/at91/rtt.tcl View File

@@ -13,7 +13,7 @@ proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
global BIT16 BIT17
if { $rtpres == 0 } {
set rtpres 65536;
}
}
global AT91C_SLOWOSC_FREQ
# Nasty hack, make this a float by tacking a .0 on the end
# otherwise, jim makes the value an integer
@@ -47,7 +47,7 @@ proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
}

proc show_RTTC { } {
show_mmr32_reg RTTC_RTMR
show_mmr32_reg RTTC_RTAR
show_mmr32_reg RTTC_RTVR


+ 5
- 5
tcl/chip/atmel/at91/usarts.tcl View File

@@ -48,7 +48,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {

set x [show_normalize_bitfield $VAL 11 9]
set s "unknown"
switch -exact $x {
switch -exact $x {
0 { set s "Even" }
1 { set s "Odd" }
2 { set s "Force=0" }
@@ -62,7 +62,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
}
}
puts [format "\tParity: %s " $s]
set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
puts [format "\tDatabits: %d" $x]

@@ -80,7 +80,7 @@ foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
set n AT91C_BASE_[set WHO]
set str ""

# Only if it exists on the chip
# Only if it exists on the chip
if [ info exists $n ] {
# Hence: $n - is like AT91C_BASE_USx
# For every sub-register
@@ -114,12 +114,12 @@ set str ""


# For every sub-register
foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {

# Create a command for this specific register.
proc show_$REG { } "show_mmr32_reg $REG"
# Add this command to the Device(as a whole) command
set str "$str\nshow_$REG"
}


+ 9
- 9
tcl/chip/st/stm32/stm32_rcc.tcl View File

@@ -16,7 +16,7 @@ proc show_RCC_CR { } {
error $msg
}

show_mmr_bitfield 0 0 $val HSI { OFF ON }
show_mmr_bitfield 0 0 $val HSI { OFF ON }
show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }
show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }
show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }
@@ -26,8 +26,8 @@ proc show_RCC_CR { } {
show_mmr_bitfield 19 19 $val CSSON { OFF ON }
show_mmr_bitfield 24 24 $val PLLON { OFF ON }
show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }
}
}
proc show_RCC_CFGR { } {
if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
error $msg
@@ -47,12 +47,12 @@ proc show_RCC_CFGR { } {
show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }
}

proc show_RCC_CIR { } {
if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
error $msg
}
}

proc show_RCC_APB2RSTR { } {
@@ -106,7 +106,7 @@ proc show_RCC_APB1RSTR { } {
set bits(13) xxx
set bits(12) xxx
set bits(11) wwdg
set bits(10) xxx
set bits(10) xxx
set bits(9) xxx
set bits(8) xxx
set bits(7) xxx
@@ -118,7 +118,7 @@ proc show_RCC_APB1RSTR { } {
set bits(1) tim3
set bits(0) tim2
show_mmr32_bits bits $val
}

proc show_RCC_AHBENR { } {
@@ -141,7 +141,7 @@ proc show_RCC_AHBENR { } {
set bits(18) xxx
set bits(17) xxx
set bits(16) xxx
set bits(15) xxx
set bits(15) xxx
set bits(14) xxx
set bits(13) xxx
set bits(12) xxx
@@ -180,7 +180,7 @@ proc show_RCC_APB2ENR { } {
set bits(18) xxx
set bits(17) xxx
set bits(16) xxx
set bits(15) adc3
set bits(15) adc3
set bits(14) usart1
set bits(13) tim8
set bits(12) spi1


+ 8
- 8
tcl/memory.tcl View File

@@ -1,4 +1,4 @@
# MEMORY
# MEMORY
#
# All Memory regions have two components.
# (1) A count of regions, in the form N_NAME
@@ -62,7 +62,7 @@ proc iswithin { ADDRESS BASE LEN } {
}

proc address_info { ADDRESS } {
foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
if { info exists $WHERE } {
set lmt [set N_[set WHERE]]
@@ -85,7 +85,7 @@ proc memread32 {ADDR} {
} else {
error "memread32: $msg"
}
}
}

proc memread16 {ADDR} {
set foo(0) 0
@@ -94,7 +94,7 @@ proc memread16 {ADDR} {
} else {
error "memread16: $msg"
}
}
}

proc memread8 {ADDR} {
set foo(0) 0
@@ -103,7 +103,7 @@ proc memread8 {ADDR} {
} else {
error "memread8: $msg"
}
}
}

proc memwrite32 {ADDR DATA} {
set foo(0) $DATA
@@ -112,7 +112,7 @@ proc memwrite32 {ADDR DATA} {
} else {
error "memwrite32: $msg"
}
}
}

proc memwrite16 {ADDR DATA} {
set foo(0) $DATA
@@ -121,7 +121,7 @@ proc memwrite16 {ADDR DATA} {
} else {
error "memwrite16: $msg"
}
}
}

proc memwrite8 {ADDR DATA} {
set foo(0) $DATA
@@ -130,4 +130,4 @@ proc memwrite8 {ADDR DATA} {
} else {
error "memwrite8: $msg"
}
}
}

+ 2
- 2
tcl/mmr_helpers.tcl View File

@@ -7,7 +7,7 @@ proc proc_exists { NAME } {

# Give: REGISTER name - must be a global variable.
proc show_mmr32_reg { NAME } {
global $NAME
# we want $($NAME)
set a [set [set NAME]]
@@ -41,7 +41,7 @@ proc show_mmr32_bits { NAMES VAL } {
set l [string length $N]
if { $l > $w } { set w $l }
}
for { set x 24 } { $x >= 0 } { incr x -8 } {
puts -nonewline " "
for { set y 7 } { $y >= 0 } { incr y -1 } {


+ 0
- 1
tcl/readable.tcl View File

@@ -22,4 +22,3 @@ proc isreadable { ADDRESS } {
}

proc isreadable32 { ADDRESS } {

+ 10
- 10
tcl/target/aduc702x.cfg View File

@@ -2,22 +2,22 @@
##


if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME aduc702x
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# This config file was defaulting to big endian..
set _ENDIAN little
}

if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x3f0f0f0f
}

@@ -26,7 +26,7 @@ jtag_nsrst_delay 200
jtag_ntrst_delay 200

# This is for the case that TRST/SRST is not wired on your JTAG adaptor.
# Don't really need them anyways.
# Don't really need them anyways.
reset_config none

## JTAG scan chain


+ 3
- 3
tcl/target/ar71xx.cfg View File

@@ -29,11 +29,11 @@ $TARGETNAME configure -event reset-init {
mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass
mww 0xb8050008 1 # set clock_switch bit
sleep 1 # wait for lock
# Setup DDR config and flash mapping
mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0)
mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8)
mww 0xb8000010 8 # force precharge all banks
mww 0xb8000010 1 # force EMRS update cycle
mww 0xb800000c 0 # clr ext. mode register
@@ -47,7 +47,7 @@ $TARGETNAME configure -event reset-init {
mww 0xb8000020 0
mww 0xb8000024 0
mww 0xb8000028 0
}
}

# setup working area somewhere in RAM
$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000


+ 10
- 10
tcl/target/at91eb40a.cfg View File

@@ -1,14 +1,14 @@
#Script for AT91EB40a

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91eb40a
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

@@ -28,7 +28,7 @@ if { [info exists CPUTAPID ] } {
#SRST reset, which means that the CPU will run a number
#of cycles before it can be halted(as much as milliseconds).
reset_config srst_only srst_pulls_trst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -53,9 +53,9 @@ $_TARGETNAME configure -event reset-init {
# Reset script for AT91EB40a
reg cpsr 0x000000D3
mww 0xFFE00020 0x1
mww 0xFFE00024 0x00000000
mww 0xFFE00000 0x01002539
mww 0xFFFFF124 0xFFFFFFFF
mww 0xFFE00024 0x00000000
mww 0xFFE00000 0x01002539
mww 0xFFFFF124 0xFFFFFFFF
mww 0xffff0010 0x100
mww 0xffff0034 0x100
}

+ 6
- 6
tcl/target/at91r40008.cfg View File

@@ -1,14 +1,14 @@


if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at9r40008
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}



+ 7
- 7
tcl/target/at91rm9200.cfg View File

@@ -3,15 +3,15 @@

reset_config trst_and_srst

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91rm9200
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

@@ -39,7 +39,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP

# Create the GDB Target.
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME

# AT91RM9200 has a 16K block of sram @ 0x0020.0000
$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 \


+ 6
- 6
tcl/target/at91sam3uXX.cfg View File

@@ -7,15 +7,15 @@
# at91sam3u2c
# at91sam3u1c

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME sam3
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}



+ 14
- 14
tcl/target/at91sam7sx.cfg View File

@@ -1,15 +1,15 @@
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only srst_pulls_trst

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91sam7s
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

@@ -24,26 +24,26 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
set _TARGETNAME $_CHIPNAME.cpu

target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -event reset-init {
$_TARGETNAME configure -event reset-init {
soft_reset_halt
# RSTC_CR : Reset peripherals
mww 0xfffffd00 0xa5000004
# disable watchdog
mww 0xfffffd44 0x00008000
mww 0xfffffd44 0x00008000
# enable user reset
mww 0xfffffd08 0xa5000001
mww 0xfffffd08 0xa5000001
# CKGR_MOR : enable the main oscillator
mww 0xfffffc20 0x00000601
mww 0xfffffc20 0x00000601
sleep 10
# CKGR_PLLR: 96.1097 MHz
mww 0xfffffc2c 0x00481c0e
mww 0xfffffc2c 0x00481c0e
sleep 10
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
mww 0xfffffc30 0x00000007
mww 0xfffffc30 0x00000007
sleep 10
# MC_FMR: flash mode (FWS=1,FMCN=73)
mww 0xffffff60 0x00490100
sleep 100
mww 0xffffff60 0x00490100
sleep 100
}

$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0


+ 6
- 6
tcl/target/at91sam9260.cfg View File

@@ -2,15 +2,15 @@
# Target: Atmel AT91SAM9260
######################################

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91sam9260
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}



+ 7
- 7
tcl/target/at91sam9260_ext_RAM_ext_flash.cfg View File

@@ -8,15 +8,15 @@ jtag_khz 4
# Target: Atmel AT91SAM9260
######################################

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91sam9260
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}

@@ -59,7 +59,7 @@ flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME


proc at91sam_init { } {
# at reset chip runs at 32khz
jtag_khz 8
halt


+ 6
- 6
tcl/target/c100.cfg View File

@@ -5,15 +5,15 @@
# assume no PLL lock, start slowly
jtag_khz 100

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME c100
}

if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}



+ 41
- 41
tcl/target/c100config.tcl View File

@@ -3,7 +3,7 @@

# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
proc config {label} {
return [dict get [configC100] $label ]
return [dict get [configC100] $label ]
}

# show the value for the param. with label
@@ -15,7 +15,7 @@ proc showconfig {label} {
# when there are more then one board config
# use soft links to c100board-config.tcl
# so that only the right board-config gets
# included (just like include/configs/board-configs.h
# included (just like include/configs/board-configs.h
# in u-boot.
proc configC100 {} {
# xtal freq. 24MHz
@@ -28,7 +28,7 @@ proc configC100 {} {
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]

# Arm Clk 450MHz, must be a multiple of 25 MHz
# Arm Clk 450MHz, must be a multiple of 25 MHz
dict set configC100 CFG_ARM_CLOCK 450000000
dict set configC100 w_arm 0
dict set configC100 x_arm 1
@@ -41,17 +41,17 @@ proc configC100 {} {
proc setupNOR {} {
puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]

# enable Expansion Bus Clock + CS0 (NOR)
mww $EX_CSEN_REG 0x3
@@ -62,7 +62,7 @@ proc setupNOR {} {
# set timings to NOR
mww $EX_CS0_TMG1_REG 0x03034006
mww $EX_CS0_TMG2_REG 0x04040002
#mww $EX_CS0_TMG3_REG
#mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
# everthing else is OK with default
@@ -72,7 +72,7 @@ proc bootNOR {} {
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
set DDR_RST [regs DDR_RST]
# put DDR controller in reset (so that it comes reset in u-boot)
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
# setup CS0 controller for NOR
@@ -93,8 +93,8 @@ proc setupGPIO {} {
#GPIO17 reset for DECT module.
#GPIO29 CS_n for NAND

set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
set GPIO_OE_REG [regs GPIO_OE_REG]
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
set GPIO_OE_REG [regs GPIO_OE_REG]

# set GPIO29=GPIO17=1, GPIO5=0
mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
@@ -104,14 +104,14 @@ proc setupGPIO {} {

proc highGPIO5 {} {
puts "GPIO5 high"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=1
mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
}

proc lowGPIO5 {} {
puts "GPIO5 low"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=0
mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
}
@@ -119,31 +119,31 @@ proc lowGPIO5 {} {
proc boardID {id} {
# so far built:
# 4'b1111
dict set boardID 15 name "EVT1"
dict set boardID 15 name "EVT1"
dict set boardID 15 ddr2size 128M
# dict set boardID 15 nandsize 1G
# dict set boardID 15 norsize 16M
# 4'b0000
dict set boardID 0 name "EVT2"
dict set boardID 0 name "EVT2"
dict set boardID 0 ddr2size 128M
# 4'b0001
dict set boardID 1 name "EVT3"
dict set boardID 1 name "EVT3"
dict set boardID 1 ddr2size 256M
# 4'b1110
dict set boardID 14 name "EVT3_old"
dict set boardID 14 ddr2size 128M
# 4'b0010
dict set boardID 2 name "EVT4"
dict set boardID 2 name "EVT4"
dict set boardID 2 ddr2size 256M

return $boardID
}

# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
proc ooma_board_detect {} {
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
# read the current value of the BOOTSRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
@@ -187,9 +187,9 @@ proc configureDDR2regs_128M {} {
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]


set DENALI_CTL_02_VAL 0x0100010000010100
set DENALI_CTL_02_VAL 0x0100010000010100
set DENALI_CTL_11_VAL 0x433A42124A650A37
# set some default values
# set some default values
mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
@@ -218,7 +218,7 @@ proc configureDDR2regs_128M {} {
# wait int_status[2] (DRAM init complete)
puts -nonewline "Waiting for DDR2 controller to init..."
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
while { [expr $tmp & 0x040000] == 0 } {
while { [expr $tmp & 0x040000] == 0 } {
sleep 1
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
}
@@ -237,18 +237,18 @@ proc setupUART0 {} {
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
set UART0_LCR [regs UART0_LCR]
set LCR_DLAB [regs LCR_DLAB]
set UART0_DLL [regs UART0_DLL]
set UART0_DLH [regs UART0_DLH]
set UART0_IIR [regs UART0_IIR]
set UART0_IER [regs UART0_IER]
set LCR_ONE_STOP [regs LCR_ONE_STOP]
set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
set UART0_LCR [regs UART0_LCR]
set LCR_DLAB [regs LCR_DLAB]
set UART0_DLL [regs UART0_DLL]
set UART0_DLH [regs UART0_DLH]
set UART0_IIR [regs UART0_IIR]
set UART0_IER [regs UART0_IER]
set LCR_ONE_STOP [regs LCR_ONE_STOP]
set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
set FCR_XMITRES [regs FCR_XMITRES]
set FCR_RCVRRES [regs FCR_RCVRRES]
set FCR_FIFOEN [regs FCR_FIFOEN]
set IER_UUE [regs IER_UUE]
set FCR_RCVRRES [regs FCR_RCVRRES]
set FCR_FIFOEN [regs FCR_FIFOEN]
set IER_UUE [regs IER_UUE]

# unlock writing to IOCTRL register
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
@@ -274,7 +274,7 @@ proc setupUART0 {} {

proc putcUART0 {char} {

set UART0_LSR [regs UART0_LSR]
set UART0_LSR [regs UART0_LSR]
set UART0_THR [regs UART0_THR]
set LSR_TEMT [regs LSR_TEMT]

@@ -311,7 +311,7 @@ proc trainDDR2 {} {
proc flashUBOOT {} {
# this will update uboot on NOR partition
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
# setup CS0 controller for NOR
setupNOR
# make sure we are accessing the lower part of NOR


+ 56
- 56
tcl/target/c100helper.tcl View File

@@ -61,17 +61,17 @@ proc mmw {reg setbits clearbits} {

proc showNOR {} {
puts "This is the current NOR setup"
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]

puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
@@ -91,21 +91,21 @@ proc showNOR {} {
proc showGPIO {} {
puts "This is the current GPIO register setup"
# GPIO outputs register
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# GPIO Output Enable register
set GPIO_OE_REG [regs GPIO_OE_REG]
set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
set GPIO_OE_REG [regs GPIO_OE_REG]
set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
# GPIO input register
set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set MUX_CONF_REG [regs MUX_CONF_REG]
set SYSCONF_REG [regs SYSCONF_REG]
set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set MUX_CONF_REG [regs MUX_CONF_REG]
set SYSCONF_REG [regs SYSCONF_REG]
set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_DEVID_REG [regs GPIO_DEVID_REG]

puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
@@ -129,7 +129,7 @@ proc showAmbaClk {} {
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode
@@ -153,13 +153,13 @@ proc showAmbaClk {} {
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
proc setupAmbaClk {} {
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
@@ -204,7 +204,7 @@ proc showArmClk {} {
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode
@@ -232,8 +232,8 @@ proc setupArmClk {} {
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]